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Add read_liberty tests of new options

This commit is contained in:
Martin Povišer 2024-10-23 14:55:32 +02:00
parent 5a0cb5d453
commit 56a9202a97
2 changed files with 23 additions and 3 deletions
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23
tests/liberty/options_test.ys Normal file
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# Test memory macro gets ignored due to -ignore_busses
read_verilog -noblackbox <<EOF
module RM_IHPSG13_1P_64x64_c2_bm_bist();
endmodule
EOF
read_liberty -lib -ignore_busses foundry_data/RM_IHPSG13_1P_64x64_c2_bm_bist_typ_1p20V_25C.lib.filtered.gz
# Test memory macro doesn't get ignored without -ignore_busses
# and check the area and capacitance attributes are populated
design -reset
read_liberty -lib foundry_data/RM_IHPSG13_1P_64x64_c2_bm_bist_typ_1p20V_25C.lib.filtered.gz
select -assert-mod-count 1 =RM_IHPSG13_1P_64x64_c2_bm_bist =A:area=50489.1328 %i
select -assert-any =*/i:A_BIST_EN =*/a:capacitance=0.00401111 %i
# Test import of unit delay arcs
design -reset
read_liberty -wb -unit_delay -ignore_miss_func foundry_data/sg13g2_stdcell_typ_1p20V_25C.lib.filtered.gz
# A->Y arc on nand2_1 exists
select -assert-any =sg13g2_nand2_1/i:A %co1:+$specify2[SRC] =sg13g2_nand2_1/o:Y %co1:+$specify2[DST] %i
# D->Q arc on sdfbbp_1 doesn't
select -assert-none =sg13g2_sdfbbp_1/i:D %co1:+$specify2[SRC] =sg13g2_nand2_1/o:Q %co1:+$specify2[DST] %i

3
tests/liberty/unit_delay.ys
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# Nothing gets imported: the file lacks timing data
read_liberty -wb -unit_delay normal.lib
select -assert-none =*/t:$specify*