diff --git a/tests/verilog/bug2042-sv.ys b/tests/verilog/bug2042-sv.ys index 9a0d419c8..e815d7fc5 100644 --- a/tests/verilog/bug2042-sv.ys +++ b/tests/verilog/bug2042-sv.ys @@ -20,6 +20,31 @@ proc sat -verify -prove-asserts +design -reset +read_verilog -sv <