mirror of https://github.com/YosysHQ/yosys.git
Remove now-redundant dff2dffs pass.
This commit is contained in:
Marcelina Kościelnicka
parent
a0e99a9f3f
commit
5693386a4e
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@ -42,7 +42,6 @@ OBJS += passes/techmap/attrmvcp.o
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OBJS += passes/techmap/attrmap.o
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OBJS += passes/techmap/zinit.o
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OBJS += passes/techmap/dfflegalize.o
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OBJS += passes/techmap/dff2dffs.o
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OBJS += passes/techmap/dffunmap.o
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OBJS += passes/techmap/flowmap.o
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OBJS += passes/techmap/extractinv.o
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@ -1,165 +0,0 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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* Copyright (C) 2018 David Shah <dave@ds0.me>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct Dff2dffsPass : public Pass {
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Dff2dffsPass() : Pass("dff2dffs", "process sync set/reset with SR over CE priority") { }
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void help() override
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{
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log("\n");
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log(" dff2dffs [options] [selection]\n");
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log("\n");
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log("Merge synchronous set/reset $_MUX_ cells to create $_SDFF_[NP][NP][01]_, to be run before\n");
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log("dff2dffe for SR over CE priority.\n");
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log("\n");
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log(" -match-init\n");
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log(" Disallow merging synchronous set/reset that has polarity opposite of the\n");
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log(" output wire's init attribute (if any).\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing dff2dffs pass (merge synchronous set/reset into FF cells).\n");
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bool match_init = false;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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// if (args[argidx] == "-singleton") {
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// singleton_mode = true;
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// continue;
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// }
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if (args[argidx] == "-match-init") {
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match_init = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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pool<IdString> dff_types;
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dff_types.insert(ID($_DFF_N_));
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dff_types.insert(ID($_DFF_P_));
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for (auto module : design->selected_modules())
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{
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log("Merging set/reset $_MUX_ cells into DFFs in %s.\n", log_id(module));
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SigMap sigmap(module);
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dict<SigBit, Cell*> sr_muxes;
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vector<Cell*> ff_cells;
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for (auto cell : module->selected_cells())
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{
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if (dff_types.count(cell->type)) {
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ff_cells.push_back(cell);
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continue;
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}
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if (cell->type != ID($_MUX_))
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continue;
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SigBit bit_a = sigmap(cell->getPort(ID::A));
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SigBit bit_b = sigmap(cell->getPort(ID::B));
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if (bit_a.wire == nullptr || bit_b.wire == nullptr)
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sr_muxes[sigmap(cell->getPort(ID::Y))] = cell;
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}
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for (auto cell : ff_cells)
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{
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SigSpec sig_d = cell->getPort(ID::D);
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if (GetSize(sig_d) < 1)
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continue;
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SigBit bit_d = sigmap(sig_d[0]);
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if (sr_muxes.count(bit_d) == 0)
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continue;
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Cell *mux_cell = sr_muxes.at(bit_d);
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SigBit bit_a = sigmap(mux_cell->getPort(ID::A));
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SigBit bit_b = sigmap(mux_cell->getPort(ID::B));
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SigBit bit_s = sigmap(mux_cell->getPort(ID::S));
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SigBit sr_val, sr_sig;
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bool invert_sr;
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sr_sig = bit_s;
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if (bit_a.wire == nullptr) {
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bit_d = bit_b;
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sr_val = bit_a;
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invert_sr = true;
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} else {
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log_assert(bit_b.wire == nullptr);
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bit_d = bit_a;
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sr_val = bit_b;
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invert_sr = false;
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}
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if (match_init) {
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SigBit bit_q = cell->getPort(ID::Q);
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if (bit_q.wire) {
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auto it = bit_q.wire->attributes.find(ID::init);
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if (it != bit_q.wire->attributes.end()) {
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auto init_val = it->second[bit_q.offset];
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if (init_val == State::S1 && sr_val != State::S1)
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continue;
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if (init_val == State::S0 && sr_val != State::S0)
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continue;
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}
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}
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}
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log(" Merging %s (A=%s, B=%s, S=%s) into %s (%s).\n", log_id(mux_cell),
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log_signal(bit_a), log_signal(bit_b), log_signal(bit_s), log_id(cell), log_id(cell->type));
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if (sr_val == State::S1) {
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if (cell->type == ID($_DFF_N_)) {
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if (invert_sr) cell->type = ID($_SDFF_NN1_);
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else cell->type = ID($_SDFF_NP1_);
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} else {
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log_assert(cell->type == ID($_DFF_P_));
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if (invert_sr) cell->type = ID($_SDFF_PN1_);
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else cell->type = ID($_SDFF_PP1_);
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}
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} else {
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if (cell->type == ID($_DFF_N_)) {
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if (invert_sr) cell->type = ID($_SDFF_NN0_);
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else cell->type = ID($_SDFF_NP0_);
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} else {
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log_assert(cell->type == ID($_DFF_P_));
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if (invert_sr) cell->type = ID($_SDFF_PN0_);
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else cell->type = ID($_SDFF_PP0_);
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}
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}
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cell->setPort(ID::R, sr_sig);
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cell->setPort(ID::D, bit_d);
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}
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}
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}
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} Dff2dffsPass;
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PRIVATE_NAMESPACE_END
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@ -1,50 +0,0 @@
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read_verilog << EOT
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module top(...);
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input clk;
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input d;
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input sr;
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output reg q0, q1, q2, q3, q4, q5;
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initial q0 = 1'b0;
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initial q1 = 1'b0;
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initial q2 = 1'b1;
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initial q3 = 1'b1;
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initial q4 = 1'bx;
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initial q5 = 1'bx;
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always @(posedge clk) begin
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q0 <= sr ? 1'b0 : d;
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q1 <= sr ? 1'b1 : d;
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q2 <= sr ? 1'b0 : d;
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q3 <= sr ? 1'b1 : d;
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q4 <= sr ? 1'b0 : d;
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q5 <= sr ? 1'b1 : d;
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end
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endmodule
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EOT
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proc
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simplemap
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design -save ref
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dff2dffs
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clean
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select -assert-count 1 w:q0 %x t:$_SDFF_PP0_ %i
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select -assert-count 1 w:q1 %x t:$_SDFF_PP1_ %i
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select -assert-count 1 w:q2 %x t:$_SDFF_PP0_ %i
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select -assert-count 1 w:q3 %x t:$_SDFF_PP1_ %i
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select -assert-count 1 w:q4 %x t:$_SDFF_PP0_ %i
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select -assert-count 1 w:q5 %x t:$_SDFF_PP1_ %i
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design -load ref
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dff2dffs -match-init
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clean
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select -assert-count 1 w:q0 %x t:$_SDFF_PP0_ %i
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select -assert-count 0 w:q1 %x t:$_SDFF_PP1_ %i
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select -assert-count 0 w:q2 %x t:$_SDFF_PP0_ %i
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select -assert-count 1 w:q3 %x t:$_SDFF_PP1_ %i
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select -assert-count 1 w:q4 %x t:$_SDFF_PP0_ %i
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select -assert-count 1 w:q5 %x t:$_SDFF_PP1_ %i
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