riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

More meaningful error message

This commit is contained in:
Eddie Hung 2019-06-24 22:12:55 -07:00
parent 4fadb471a3
commit 5605002d8a
1 changed files with 2 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
passes/techmap/abc9.cc
View File

@ -118,6 +118,8 @@ void handle_loops(RTLIL::Design *design)
auto jt = box_module->attributes.find("\\abc_scc_break"); auto jt = box_module->attributes.find("\\abc_scc_break");
if (jt != box_module->attributes.end()) { if (jt != box_module->attributes.end()) {
auto it = cell->connections_.find(RTLIL::escape_id(jt->second.decode_string())); auto it = cell->connections_.find(RTLIL::escape_id(jt->second.decode_string()));
if (it == cell->connections_.end())
log_error("abc_scc_break attribute value '%s' does not exist as port on module '%s'\n", jt->second.decode_string().c_str(), log_id(box_module));
log_assert(it != cell->connections_.end()); log_assert(it != cell->connections_.end());
auto &c = *it; auto &c = *it;
SigBit b = cell->getPort(RTLIL::escape_id(jt->second.decode_string())); SigBit b = cell->getPort(RTLIL::escape_id(jt->second.decode_string()));