Share common tests

tests/arch/anlogic/add_sub.ys

@@ -1,4 +1,4 @@
-read_verilog add_sub.v
+read_verilog ../common/add_sub.v
 hierarchy -top top
 proc
 equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check

tests/arch/anlogic/counter.ys

@@ -1,4 +1,4 @@
-read_verilog counter.v
+read_verilog ../common/counter.v
 hierarchy -top top
 proc
 flatten

tests/arch/anlogic/dffs.ys

@@ -1,4 +1,4 @@
-read_verilog dffs.v
+read_verilog ../common/dffs.v
 design -save read
 
 hierarchy -top dff

tests/arch/anlogic/fsm.ys

@@ -1,4 +1,4 @@
-read_verilog fsm.v
+read_verilog ../common/fsm.v
 hierarchy -top fsm
 proc
 #flatten

tests/arch/anlogic/latches.ys

@@ -1,4 +1,4 @@
-read_verilog latches.v
+read_verilog ../common/latches.v
 design -save read
 
 hierarchy -top latchp

tests/arch/anlogic/logic.ys

@@ -0,0 +1,11 @@
+read_verilog ../common/logic.v
+hierarchy -top top
+proc
+equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 1 t:AL_MAP_LUT1
+select -assert-count 6 t:AL_MAP_LUT2
+select -assert-count 2 t:AL_MAP_LUT4
+select -assert-none t:AL_MAP_LUT1 t:AL_MAP_LUT2 t:AL_MAP_LUT4 %% t:* %D

tests/arch/anlogic/mux.ys

@@ -1,4 +1,4 @@
-read_verilog mux.v
+read_verilog ../common/mux.v
 design -save read
 
 hierarchy -top mux2

tests/arch/anlogic/shifter.ys

@@ -1,4 +1,4 @@
-read_verilog shifter.v
+read_verilog ../common/shifter.v
 hierarchy -top top
 proc
 flatten

tests/arch/anlogic/tribuf.v

@@ -1,8 +0,0 @@
-module tristate (en, i, o);
-    input en;
-    input i;
-    output o;
-
-	assign o = en ? i : 1'bz;
-
-endmodule

tests/arch/anlogic/tribuf.ys

@@ -1,4 +1,4 @@
-read_verilog tribuf.v
+read_verilog ../common/tribuf.v
 hierarchy -top tristate
 proc
 flatten

tests/arch/ecp5/add_sub.v

@@ -1,13 +0,0 @@
-module top
-(
- input [3:0] x,
- input [3:0] y,
-
- output [3:0] A,
- output [3:0] B
- );
-
-assign A =  x + y;
-assign B =  x - y;
-
-endmodule

tests/arch/ecp5/add_sub.ys

@@ -1,4 +1,4 @@
-read_verilog add_sub.v
+read_verilog ../common/add_sub.v
 hierarchy -top top
 proc
 equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check

tests/arch/ecp5/adffs.ys

@@ -1,4 +1,4 @@
-read_verilog adffs.v
+read_verilog ../common/adffs.v
 design -save read
 
 hierarchy -top adff

tests/arch/ecp5/counter.v

@@ -1,17 +0,0 @@
-module top    (
-out,
-clk,
-reset
-);
-    output [7:0] out;
-    input clk, reset;
-    reg [7:0] out;
-
-    always @(posedge clk, posedge reset)
-		if (reset) begin
-			out <= 8'b0 ;
-		end else
-			out <= out + 1;
-
-
-endmodule

tests/arch/ecp5/counter.ys

@@ -1,4 +1,4 @@
-read_verilog counter.v
+read_verilog ../common/counter.v
 hierarchy -top top
 proc
 flatten

tests/arch/ecp5/dffs.v

@@ -1,15 +0,0 @@
-module dff
-    ( input d, clk, output reg q );
-	always @( posedge clk )
-            q <= d;
-endmodule
-
-module dffe
-    ( input d, clk, en, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk )
-		if ( en )
-			q <= d;
-endmodule

tests/arch/ecp5/dffs.ys

@@ -1,4 +1,4 @@
-read_verilog dffs.v
+read_verilog ../common/dffs.v
 design -save read
 
 hierarchy -top dff

tests/arch/ecp5/fsm.v

@@ -1,55 +0,0 @@
- module fsm (
- clock,
- reset,
- req_0,
- req_1,
- gnt_0,
- gnt_1
- );
- input   clock,reset,req_0,req_1;
- output  gnt_0,gnt_1;
- wire    clock,reset,req_0,req_1;
- reg     gnt_0,gnt_1;
-
- parameter SIZE = 3           ;
- parameter IDLE  = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
-
- reg [SIZE-1:0] state;
- reg [SIZE-1:0] next_state;
-
- always @ (posedge clock)
- begin : FSM
- if (reset == 1'b1) begin
-   state <=  #1  IDLE;
-   gnt_0 <= 0;
-   gnt_1 <= 0;
- end else
-  case(state)
-    IDLE : if (req_0 == 1'b1) begin
-                 state <=  #1  GNT0;
-                 gnt_0 <= 1;
-               end else if (req_1 == 1'b1) begin
-                 gnt_1 <= 1;
-                 state <=  #1  GNT0;
-               end else begin
-                 state <=  #1  IDLE;
-               end
-    GNT0 : if (req_0 == 1'b1) begin
-                 state <=  #1  GNT0;
-               end else begin
-                 gnt_0 <= 0;
-                 state <=  #1  IDLE;
-               end
-    GNT1 : if (req_1 == 1'b1) begin
-                 state <=  #1  GNT2;
-				 gnt_1 <= req_0;
-               end
-    GNT2 : if (req_0 == 1'b1) begin
-                 state <=  #1  GNT1;
-				 gnt_1 <= req_1;
-               end
-    default : state <=  #1  IDLE;
- endcase
- end
-
-endmodule

tests/arch/ecp5/fsm.ys

@@ -1,4 +1,4 @@
-read_verilog fsm.v
+read_verilog ../common/fsm.v
 hierarchy -top fsm
 proc
 flatten

tests/arch/ecp5/latches.v

@@ -1,24 +0,0 @@
-module latchp
-    ( input d, clk, en, output reg q );
-	always @*
-		if ( en )
-			q <= d;
-endmodule
-
-module latchn
-    ( input d, clk, en, output reg q );
-	always @*
-		if ( !en )
-			q <= d;
-endmodule
-
-module latchsr
-    ( input d, clk, en, clr, pre, output reg q );
-	always @*
-		if ( clr )
-			q <= 1'b0;
-		else if ( pre )
-			q <= 1'b1;
-		else if ( en )
-			q <= d;
-endmodule

tests/arch/ecp5/latches.ys

@@ -1,5 +1,4 @@
-
-read_verilog latches.v
+read_verilog ../common/latches.v
 design -save read
 
 hierarchy -top latchp

tests/arch/ecp5/logic.ys

@@ -1,4 +1,4 @@
-read_verilog logic.v
+read_verilog ../common/logic.v
 hierarchy -top top
 proc
 equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check

tests/arch/ecp5/mul.ys

@@ -1,4 +1,4 @@
-read_verilog mul.v
+read_verilog ../common/mul.v
 hierarchy -top top
 proc
 # Blocked by issue #1358 (Missing ECP5 simulation models)

tests/arch/ecp5/mux.v

@@ -1,66 +0,0 @@
-module mux2 (S,A,B,Y);
-    input S;
-    input A,B;
-    output reg Y;
-
-    always @(*)
-		Y = (S)? B : A;
-endmodule
-
-module mux4 ( S, D, Y );
-
-input[1:0] S;
-input[3:0] D;
-output Y;
-
-reg Y;
-wire[1:0] S;
-wire[3:0] D;
-
-always @*
-begin
-    case( S )
-       0 : Y = D[0];
-       1 : Y = D[1];
-       2 : Y = D[2];
-       3 : Y = D[3];
-   endcase
-end
-
-endmodule
-
-module mux8 ( S, D, Y );
-
-input[2:0] S;
-input[7:0] D;
-output Y;
-
-reg Y;
-wire[2:0] S;
-wire[7:0] D;
-
-always @*
-begin
-   case( S )
-       0 : Y = D[0];
-       1 : Y = D[1];
-       2 : Y = D[2];
-       3 : Y = D[3];
-       4 : Y = D[4];
-       5 : Y = D[5];
-       6 : Y = D[6];
-       7 : Y = D[7];
-   endcase
-end
-
-endmodule
-
-module mux16 (D, S, Y);
- 	input  [15:0] D;
- 	input  [3:0] S;
- 	output Y;
-
-assign Y = D[S];
-
-endmodule
-

tests/arch/ecp5/mux.ys

@@ -1,4 +1,4 @@
-read_verilog mux.v
+read_verilog ../common/mux.v
 design -save read
 
 hierarchy -top mux2

tests/arch/ecp5/shifter.v

@@ -1,16 +0,0 @@
-module top    (
-out,
-clk,
-in
-);
-    output [7:0] out;
-    input signed clk, in;
-    reg signed [7:0] out = 0;
-
-    always @(posedge clk)
-	begin
-		out    <= out >> 1;
-		out[7] <= in;
-	end
-
-endmodule

tests/arch/ecp5/shifter.ys

@@ -1,4 +1,4 @@
-read_verilog shifter.v
+read_verilog ../common/shifter.v
 hierarchy -top top
 proc
 flatten

tests/arch/ecp5/tribuf.v

@@ -1,8 +0,0 @@
-module tristate (en, i, o);
-    input en;
-    input i;
-    output o;
-
-	assign o = en ? i : 1'bz;
-
-endmodule

tests/arch/ecp5/tribuf.ys

@@ -1,4 +1,4 @@
-read_verilog tribuf.v
+read_verilog ../common/tribuf.v
 hierarchy -top tristate
 proc
 flatten

tests/arch/efinix/add_sub.v

@@ -1,13 +0,0 @@
-module top
-(
- input [3:0] x,
- input [3:0] y,
-
- output [3:0] A,
- output [3:0] B
- );
-
-assign A =  x + y;
-assign B =  x - y;
-
-endmodule

tests/arch/efinix/add_sub.ys

@@ -1,4 +1,4 @@
-read_verilog add_sub.v
+read_verilog ../common/add_sub.v
 hierarchy -top top
 proc
 equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check

tests/arch/efinix/adffs.v

@@ -1,47 +0,0 @@
-module adff
-    ( input d, clk, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk, posedge clr )
-		if ( clr )
-			q <= 1'b0;
-		else
-            q <= d;
-endmodule
-
-module adffn
-    ( input d, clk, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk, negedge clr )
-		if ( !clr )
-			q <= 1'b0;
-		else
-            q <= d;
-endmodule
-
-module dffs
-    ( input d, clk, pre, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk )
-		if ( pre )
-			q <= 1'b1;
-		else
-            q <= d;
-endmodule
-
-module ndffnr
-    ( input d, clk, pre, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( negedge clk )
-		if ( !clr )
-			q <= 1'b0;
-		else
-            q <= d;
-endmodule

tests/arch/efinix/adffs.ys

@@ -1,4 +1,4 @@
-read_verilog adffs.v
+read_verilog ../common/adffs.v
 design -save read
 
 hierarchy -top adff

tests/arch/efinix/counter.v

@@ -1,17 +0,0 @@
-module top    (
-out,
-clk,
-reset
-);
-    output [7:0] out;
-    input clk, reset;
-    reg [7:0] out;
-
-    always @(posedge clk, posedge reset)
-		if (reset) begin
-			out <= 8'b0 ;
-		end else
-			out <= out + 1;
-
-
-endmodule

tests/arch/efinix/counter.ys

@@ -1,4 +1,4 @@
-read_verilog counter.v
+read_verilog ../common/counter.v
 hierarchy -top top
 proc
 flatten

tests/arch/efinix/dffs.v

@@ -1,15 +0,0 @@
-module dff
-    ( input d, clk, output reg q );
-	always @( posedge clk )
-            q <= d;
-endmodule
-
-module dffe
-    ( input d, clk, en, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk )
-		if ( en )
-			q <= d;
-endmodule

tests/arch/efinix/dffs.ys

@@ -1,4 +1,4 @@
-read_verilog dffs.v
+read_verilog ../common/dffs.v
 design -save read
 
 hierarchy -top dff

tests/arch/efinix/fsm.v

@@ -1,55 +0,0 @@
- module fsm (
- clock,
- reset,
- req_0,
- req_1,
- gnt_0,
- gnt_1
- );
- input   clock,reset,req_0,req_1;
- output  gnt_0,gnt_1;
- wire    clock,reset,req_0,req_1;
- reg     gnt_0,gnt_1;
-
- parameter SIZE = 3           ;
- parameter IDLE  = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
-
- reg [SIZE-1:0] state;
- reg [SIZE-1:0] next_state;
-
- always @ (posedge clock)
- begin : FSM
- if (reset == 1'b1) begin
-   state <=  #1  IDLE;
-   gnt_0 <= 0;
-   gnt_1 <= 0;
- end else
-  case(state)
-    IDLE : if (req_0 == 1'b1) begin
-                 state <=  #1  GNT0;
-                 gnt_0 <= 1;
-               end else if (req_1 == 1'b1) begin
-                 gnt_1 <= 1;
-                 state <=  #1  GNT0;
-               end else begin
-                 state <=  #1  IDLE;
-               end
-    GNT0 : if (req_0 == 1'b1) begin
-                 state <=  #1  GNT0;
-               end else begin
-                 gnt_0 <= 0;
-                 state <=  #1  IDLE;
-               end
-    GNT1 : if (req_1 == 1'b1) begin
-                 state <=  #1  GNT2;
-				 gnt_1 <= req_0;
-               end
-    GNT2 : if (req_0 == 1'b1) begin
-                 state <=  #1  GNT1;
-				 gnt_1 <= req_1;
-               end
-    default : state <=  #1  IDLE;
- endcase
- end
-
-endmodule

tests/arch/efinix/fsm.ys

@@ -1,4 +1,4 @@
-read_verilog fsm.v
+read_verilog ../common/fsm.v
 hierarchy -top fsm
 proc
 flatten

tests/arch/efinix/latches.v

@@ -1,24 +0,0 @@
-module latchp
-    ( input d, clk, en, output reg q );
-	always @*
-		if ( en )
-			q <= d;
-endmodule
-
-module latchn
-    ( input d, clk, en, output reg q );
-	always @*
-		if ( !en )
-			q <= d;
-endmodule
-
-module latchsr
-    ( input d, clk, en, clr, pre, output reg q );
-	always @*
-		if ( clr )
-			q <= 1'b0;
-		else if ( pre )
-			q <= 1'b1;
-		else if ( en )
-			q <= d;
-endmodule

tests/arch/efinix/latches.ys

@@ -1,4 +1,4 @@
-read_verilog latches.v
+read_verilog ../common/latches.v
 design -save read
 
 hierarchy -top latchp

tests/arch/efinix/logic.v

@@ -1,18 +0,0 @@
-module top
-(
- input [0:7] in,
- output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10
- );
-
-   assign     B1 =  in[0] & in[1];
-   assign     B2 =  in[0] | in[1];
-   assign     B3 =  in[0] ~& in[1];
-   assign     B4 =  in[0] ~| in[1];
-   assign     B5 =  in[0] ^ in[1];
-   assign     B6 =  in[0] ~^ in[1];
-   assign     B7 =  ~in[0];
-   assign     B8 =  in[0];
-   assign     B9 =  in[0:1] && in [2:3];
-   assign     B10 =  in[0:1] || in [2:3];
-
-endmodule

tests/arch/efinix/logic.ys

@@ -1,4 +1,4 @@
-read_verilog logic.v
+read_verilog ../common/logic.v
 hierarchy -top top
 proc
 equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check

tests/arch/efinix/mux.v

@@ -1,65 +0,0 @@
-module mux2 (S,A,B,Y);
-    input S;
-    input A,B;
-    output reg Y;
-
-    always @(*)
-		Y = (S)? B : A;
-endmodule
-
-module mux4 ( S, D, Y );
-
-input[1:0] S;
-input[3:0] D;
-output Y;
-
-reg Y;
-wire[1:0] S;
-wire[3:0] D;
-
-always @*
-begin
-    case( S )
-       0 : Y = D[0];
-       1 : Y = D[1];
-       2 : Y = D[2];
-       3 : Y = D[3];
-   endcase
-end
-
-endmodule
-
-module mux8 ( S, D, Y );
-
-input[2:0] S;
-input[7:0] D;
-output Y;
-
-reg Y;
-wire[2:0] S;
-wire[7:0] D;
-
-always @*
-begin
-   case( S )
-       0 : Y = D[0];
-       1 : Y = D[1];
-       2 : Y = D[2];
-       3 : Y = D[3];
-       4 : Y = D[4];
-       5 : Y = D[5];
-       6 : Y = D[6];
-       7 : Y = D[7];
-   endcase
-end
-
-endmodule
-
-module mux16 (D, S, Y);
- 	input  [15:0] D;
- 	input  [3:0] S;
- 	output Y;
-
-assign Y = D[S];
-
-endmodule

tests/arch/efinix/mux.ys

@@ -1,4 +1,4 @@
-read_verilog mux.v
+read_verilog ../common/mux.v
 design -save read
 
 hierarchy -top mux2

tests/arch/efinix/shifter.v

@@ -1,16 +0,0 @@
-module top    (
-out,
-clk,
-in
-);
-    output [7:0] out;
-    input signed clk, in;
-    reg signed [7:0] out = 0;
-
-    always @(posedge clk)
-	begin
-		out    <= out << 1;
-		out[7] <= in;
-	end
-
-endmodule

tests/arch/efinix/shifter.ys

@@ -1,4 +1,4 @@
-read_verilog shifter.v
+read_verilog ../common/shifter.v
 hierarchy -top top
 proc
 flatten

tests/arch/efinix/tribuf.ys

@@ -1,4 +1,4 @@
-read_verilog tribuf.v
+read_verilog ../common/tribuf.v
 hierarchy -top tristate
 proc
 tribuf

tests/arch/ice40/add_sub.v

@@ -1,13 +0,0 @@
-module top
-(
- input [3:0] x,
- input [3:0] y,
-
- output [3:0] A,
- output [3:0] B
- );
-
-assign A =  x + y;
-assign B =  x - y;
-
-endmodule

tests/arch/ice40/add_sub.ys

@@ -1,4 +1,4 @@
-read_verilog add_sub.v
+read_verilog ../common/add_sub.v
 hierarchy -top top
 equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)

tests/arch/ice40/adffs.v

@@ -1,87 +0,0 @@
-module adff
-    ( input d, clk, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk, posedge clr )
-		if ( clr )
-			q <= 1'b0;
-		else
-            q <= d;
-endmodule
-
-module adffn
-    ( input d, clk, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk, negedge clr )
-		if ( !clr )
-			q <= 1'b0;
-		else
-            q <= d;
-endmodule
-
-module dffs
-    ( input d, clk, pre, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk, posedge pre )
-		if ( pre )
-			q <= 1'b1;
-		else
-            q <= d;
-endmodule
-
-module ndffnr
-    ( input d, clk, pre, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( negedge clk, negedge pre )
-		if ( !pre )
-			q <= 1'b1;
-		else
-            q <= d;
-endmodule
-
-module top (
-input clk,
-input clr,
-input pre,
-input a,
-output b,b1,b2,b3
-);
-
-dffs u_dffs (
-        .clk (clk ),
-        .clr (clr),
-        .pre (pre),
-        .d (a ),
-        .q (b )
-    );
-
-ndffnr u_ndffnr (
-        .clk (clk ),
-        .clr (clr),
-        .pre (pre),
-        .d (a ),
-        .q (b1 )
-    );
-
-adff u_adff (
-        .clk (clk ),
-        .clr (clr),
-        .d (a ),
-        .q (b2 )
-    );
-
-adffn u_adffn (
-        .clk (clk ),
-        .clr (clr),
-        .d (a ),
-        .q (b3 )
-    );
-
-endmodule

tests/arch/ice40/adffs.ys

@@ -1,11 +1,39 @@
-read_verilog adffs.v
+read_verilog ../common/adffs.v
+design -save read
+
+hierarchy -top adff
 proc
-flatten
-equiv_opt -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-select -assert-count 1 t:SB_DFFNS
-select -assert-count 2 t:SB_DFFR
-select -assert-count 1 t:SB_DFFS
-select -assert-count 2 t:SB_LUT4
-select -assert-none t:SB_DFFNS t:SB_DFFR t:SB_DFFS t:SB_LUT4 %% t:* %D
+cd adff # Constrain all select calls below inside the top module
+select -assert-count 1 t:SB_DFFR
+select -assert-none t:SB_DFFR %% t:* %D
+
+design -load read
+hierarchy -top adffn
+proc
+equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd adffn # Constrain all select calls below inside the top module
+select -assert-count 1 t:SB_DFFR
+select -assert-count 1 t:SB_LUT4
+select -assert-none t:SB_DFFR t:SB_LUT4 %% t:* %D
+
+design -load read
+hierarchy -top dffs
+proc
+equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffs # Constrain all select calls below inside the top module
+select -assert-count 1 t:SB_DFFSS
+select -assert-none t:SB_DFFSS %% t:* %D
+
+design -load read
+hierarchy -top ndffnr
+proc
+equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd ndffnr # Constrain all select calls below inside the top module
+select -assert-count 1 t:SB_DFFNSR
+select -assert-count 1 t:SB_LUT4
+select -assert-none t:SB_DFFNSR t:SB_LUT4 %% t:* %D

tests/arch/ice40/counter.v

@@ -1,17 +0,0 @@
-module top    (
-out,
-clk,
-reset
-);
-    output [7:0] out;
-    input clk, reset;
-    reg [7:0] out;
-
-    always @(posedge clk, posedge reset)
-		if (reset) begin
-			out <= 8'b0 ;
-		end else
-			out <= out + 1;
-
-
-endmodule

tests/arch/ice40/counter.ys

@@ -1,4 +1,4 @@
-read_verilog counter.v
+read_verilog ../common/counter.v
 hierarchy -top top
 proc
 flatten

tests/arch/ice40/dffs.v

@@ -1,37 +0,0 @@
-module dff
-    ( input d, clk, output reg q );
-	always @( posedge clk )
-            q <= d;
-endmodule
-
-module dffe
-    ( input d, clk, en, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk )
-		if ( en )
-			q <= d;
-endmodule
-
-module top (
-input clk,
-input en,
-input a,
-output b,b1,
-);
-
-dff u_dff (
-        .clk (clk ),
-        .d (a ),
-        .q (b )
-    );
-
-dffe u_ndffe (
-        .clk (clk ),
-        .en (en),
-        .d (a ),
-        .q (b1 )
-    );
-
-endmodule

tests/arch/ice40/dffs.ys

@@ -1,10 +1,19 @@
-read_verilog dffs.v
-hierarchy -top top
+read_verilog ../common/dffs.v
+design -save read
+
+hierarchy -top dff
 proc
-flatten
 equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd dff # Constrain all select calls below inside the top module
 select -assert-count 1 t:SB_DFF
+select -assert-none t:SB_DFF %% t:* %D
+
+design -load read
+hierarchy -top dffe
+proc
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffe # Constrain all select calls below inside the top module
 select -assert-count 1 t:SB_DFFE
-select -assert-none t:SB_DFF t:SB_DFFE %% t:* %D
+select -assert-none t:SB_DFFE %% t:* %D

tests/arch/ice40/fsm.v

@@ -1,73 +0,0 @@
- module fsm (
- clock,
- reset,
- req_0,
- req_1,
- gnt_0,
- gnt_1
- );
- input   clock,reset,req_0,req_1;
- output  gnt_0,gnt_1;
- wire    clock,reset,req_0,req_1;
- reg     gnt_0,gnt_1;
-
- parameter SIZE = 3           ;
- parameter IDLE  = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
-
- reg [SIZE-1:0] state;
- reg [SIZE-1:0] next_state;
-
- always @ (posedge clock)
- begin : FSM
- if (reset == 1'b1) begin
-   state <=  #1  IDLE;
-   gnt_0 <= 0;
-   gnt_1 <= 0;
- end else
-  case(state)
-    IDLE : if (req_0 == 1'b1) begin
-                 state <=  #1  GNT0;
-                 gnt_0 <= 1;
-               end else if (req_1 == 1'b1) begin
-                 gnt_1 <= 1;
-                 state <=  #1  GNT0;
-               end else begin
-                 state <=  #1  IDLE;
-               end
-    GNT0 : if (req_0 == 1'b1) begin
-                 state <=  #1  GNT0;
-               end else begin
-                 gnt_0 <= 0;
-                 state <=  #1  IDLE;
-               end
-    GNT1 : if (req_1 == 1'b1) begin
-                 state <=  #1  GNT2;
-				 gnt_1 <= req_0;
-               end
-    GNT2 : if (req_0 == 1'b1) begin
-                 state <=  #1  GNT1;
-				 gnt_1 <= req_1;
-               end
-    default : state <=  #1  IDLE;
- endcase
- end
-
- endmodule
-
- module top (
-input clk,
-input rst,
-input a,
-input b,
-output g0,
-output g1
-);
-
-fsm u_fsm ( .clock(clk),
-            .reset(rst),
-            .req_0(a),
-            .req_1(b),
-            .gnt_0(g0),
-            .gnt_1(g1));
-
-endmodule

tests/arch/ice40/fsm.ys

@@ -1,10 +1,10 @@
-read_verilog fsm.v
-hierarchy -top top
+read_verilog ../common/fsm.v
+hierarchy -top fsm
 proc
 flatten
 equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd fsm # Constrain all select calls below inside the top module
 
 select -assert-count 2 t:SB_DFFESR
 select -assert-count 2 t:SB_DFFSR

tests/arch/ice40/latches.v

@@ -1,58 +0,0 @@
-module latchp
-    ( input d, clk, en, output reg q );
-	always @*
-		if ( en )
-			q <= d;
-endmodule
-
-module latchn
-    ( input d, clk, en, output reg q );
-	always @*
-		if ( !en )
-			q <= d;
-endmodule
-
-module latchsr
-    ( input d, clk, en, clr, pre, output reg q );
-	always @*
-		if ( clr )
-			q <= 1'b0;
-		else if ( pre )
-			q <= 1'b1;
-		else if ( en )
-			q <= d;
-endmodule
-
-
-module top (
-input clk,
-input clr,
-input pre,
-input a,
-output b,b1,b2
-);
-
-
-latchp u_latchp (
-        .en (clk ),
-        .d (a ),
-        .q (b )
-    );
-
-
-latchn u_latchn (
-        .en (clk ),
-        .d (a ),
-        .q (b1 )
-    );
-
-
-latchsr u_latchsr (
-        .en (clk ),
-        .clr (clr),
-        .pre (pre),
-        .d (a ),
-        .q (b2 )
-    );
-
-endmodule

tests/arch/ice40/latches.ys

@@ -1,12 +1,33 @@
-read_verilog latches.v
+read_verilog ../common/latches.v
+design -save read
 
+hierarchy -top latchp
 proc
-flatten
 # Can't run any sort of equivalence check because latches are blown to LUTs
-#equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
-
-#design -load preopt
 synth_ice40
-cd top
-select -assert-count 4 t:SB_LUT4
+cd latchp # Constrain all select calls below inside the top module
+select -assert-count 1 t:SB_LUT4
+
+select -assert-none t:SB_LUT4 %% t:* %D
+
+
+design -load read
+hierarchy -top latchn
+proc
+# Can't run any sort of equivalence check because latches are blown to LUTs
+synth_ice40
+cd latchn # Constrain all select calls below inside the top module
+select -assert-count 1 t:SB_LUT4
+
+select -assert-none t:SB_LUT4 %% t:* %D
+
+
+design -load read
+hierarchy -top latchsr
+proc
+# Can't run any sort of equivalence check because latches are blown to LUTs
+synth_ice40
+cd latchsr # Constrain all select calls below inside the top module
+select -assert-count 2 t:SB_LUT4
+
 select -assert-none t:SB_LUT4 %% t:* %D

tests/arch/ice40/logic.v

@@ -1,18 +0,0 @@
-module top
-(
- input [0:7] in,
- output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10
- );
-
-   assign     B1 =  in[0] & in[1];
-   assign     B2 =  in[0] | in[1];
-   assign     B3 =  in[0] ~& in[1];
-   assign     B4 =  in[0] ~| in[1];
-   assign     B5 =  in[0] ^ in[1];
-   assign     B6 =  in[0] ~^ in[1];
-   assign     B7 =  ~in[0];
-   assign     B8 =  in[0];
-   assign     B9 =  in[0:1] && in [2:3];
-   assign     B10 =  in[0:1] || in [2:3];
-
-endmodule

tests/arch/ice40/logic.ys

@@ -1,4 +1,4 @@
-read_verilog logic.v
+read_verilog ../common/logic.v
 hierarchy -top top
 equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)

tests/arch/ice40/mul.v

@@ -1,11 +0,0 @@
-module top
-(
- input [5:0] x,
- input [5:0] y,
-
- output [11:0] A,
- );
-
-assign A =  x * y;
-
-endmodule

tests/arch/ice40/mul.ys

@@ -1,4 +1,4 @@
-read_verilog mul.v
+read_verilog ../common/mul.v
 hierarchy -top top
 equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)

tests/arch/ice40/mux.v

@@ -1,100 +0,0 @@
-module mux2 (S,A,B,Y);
-    input S;
-    input A,B;
-    output reg Y;
-
-    always @(*)
-		Y = (S)? B : A;
-endmodule
-
-module mux4 ( S, D, Y );
-
-input[1:0] S;
-input[3:0] D;
-output Y;
-
-reg Y;
-wire[1:0] S;
-wire[3:0] D;
-
-always @*
-begin
-    case( S )
-       0 : Y = D[0];
-       1 : Y = D[1];
-       2 : Y = D[2];
-       3 : Y = D[3];
-   endcase
-end
-
-endmodule
-
-module mux8 ( S, D, Y );
-
-input[2:0] S;
-input[7:0] D;
-output Y;
-
-reg Y;
-wire[2:0] S;
-wire[7:0] D;
-
-always @*
-begin
-   case( S )
-       0 : Y = D[0];
-       1 : Y = D[1];
-       2 : Y = D[2];
-       3 : Y = D[3];
-       4 : Y = D[4];
-       5 : Y = D[5];
-       6 : Y = D[6];
-       7 : Y = D[7];
-   endcase
-end
-
-endmodule
-
-module mux16 (D, S, Y);
- 	input  [15:0] D;
- 	input  [3:0] S;
- 	output Y;
-
-assign Y = D[S];
-
-endmodule
-
-
-module top (
-input [3:0] S,
-input [15:0] D,
-output M2,M4,M8,M16
-);
-
-mux2 u_mux2 (
-        .S (S[0]),
-        .A (D[0]),
-        .B (D[1]),
-        .Y (M2)
-    );
-
-
-mux4 u_mux4 (
-        .S (S[1:0]),
-        .D (D[3:0]),
-        .Y (M4)
-    );
-
-mux8 u_mux8 (
-        .S (S[2:0]),
-        .D (D[7:0]),
-        .Y (M8)
-    );
-
-mux16 u_mux16 (
-        .S (S[3:0]),
-        .D (D[15:0]),
-        .Y (M16)
-    );
-
-endmodule

tests/arch/ice40/mux.ys

@@ -1,8 +1,40 @@
-read_verilog mux.v
+read_verilog ../common/mux.v
+design -save read
+
+hierarchy -top mux2
 proc
-flatten
 equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-select -assert-count 19 t:SB_LUT4
+cd mux2 # Constrain all select calls below inside the top module
+select -assert-count 1 t:SB_LUT4
+select -assert-none t:SB_LUT4 %% t:* %D
+
+design -load read
+hierarchy -top mux4
+proc
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux4 # Constrain all select calls below inside the top module
+select -assert-count 2 t:SB_LUT4
+
+select -assert-none t:SB_LUT4 %% t:* %D
+
+design -load read
+hierarchy -top mux8
+proc
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux8 # Constrain all select calls below inside the top module
+select -assert-count 5 t:SB_LUT4
+
+select -assert-none t:SB_LUT4 %% t:* %D
+
+design -load read
+hierarchy -top mux16
+proc
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux16 # Constrain all select calls below inside the top module
+select -assert-count 11 t:SB_LUT4
+
 select -assert-none t:SB_LUT4 %% t:* %D

tests/arch/ice40/shifter.v

@@ -1,22 +0,0 @@
-module top    (
-out,
-clk,
-in
-);
-    output [7:0] out;
-    input signed clk, in;
-    reg signed [7:0] out = 0;
-
-    always @(posedge clk)
-	begin
-`ifndef BUG
-		out    <= out >> 1;
-		out[7] <= in;
-`else
-
-		out    <= out << 1;
-		out[7] <= in;
-`endif
-	end
-
-endmodule

tests/arch/ice40/shifter.ys

@@ -1,4 +1,4 @@
-read_verilog shifter.v
+read_verilog ../common/shifter.v
 hierarchy -top top
 proc
 flatten

tests/arch/ice40/tribuf.v

@@ -1,23 +0,0 @@
-module tristate (en, i, o);
-    input en;
-    input i;
-    output o;
-
-	assign o = en ? i : 1'bz;
-
-endmodule
-
-
-module top (
-input en,
-input a,
-output b
-);
-
-tristate u_tri (
-        .en (en ),
-        .i (a ),
-        .o (b )
-    );
-
-endmodule

tests/arch/ice40/tribuf.ys

@@ -1,9 +1,11 @@
-read_verilog tribuf.v
-hierarchy -top top
+read_verilog ../common/tribuf.v
+hierarchy -top tristate
 proc
+tribuf
 flatten
+synth
 equiv_opt -assert -map +/ice40/cells_sim.v -map +/simcells.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd tristate # Constrain all select calls below inside the top module
 select -assert-count 1 t:$_TBUF_
 select -assert-none t:$_TBUF_ %% t:* %D

tests/arch/xilinx/add_sub.v

@@ -1,13 +0,0 @@
-module top
-(
- input [3:0] x,
- input [3:0] y,
-
- output [3:0] A,
- output [3:0] B
- );
-
-assign A =  x + y;
-assign B =  x - y;
-
-endmodule

tests/arch/xilinx/add_sub.ys

@@ -1,4 +1,4 @@
-read_verilog add_sub.v
+read_verilog ../common/add_sub.v
 hierarchy -top top
 proc
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check

tests/arch/xilinx/adffs.v

@@ -1,47 +0,0 @@
-module adff
-    ( input d, clk, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk, posedge clr )
-		if ( clr )
-			q <= 1'b0;
-		else
-            q <= d;
-endmodule
-
-module adffn
-    ( input d, clk, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk, negedge clr )
-		if ( !clr )
-			q <= 1'b0;
-		else
-            q <= d;
-endmodule
-
-module dffs
-    ( input d, clk, pre, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk )
-		if ( pre )
-			q <= 1'b1;
-		else
-            q <= d;
-endmodule
-
-module ndffnr
-    ( input d, clk, pre, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( negedge clk )
-		if ( !clr )
-			q <= 1'b0;
-		else
-            q <= d;
-endmodule

tests/arch/xilinx/adffs.ys

@@ -1,4 +1,4 @@
-read_verilog adffs.v
+read_verilog ../common/adffs.v
 design -save read
 
 hierarchy -top adff

tests/arch/xilinx/counter.v

@@ -1,17 +0,0 @@
-module top    (
-out,
-clk,
-reset
-);
-    output [7:0] out;
-    input clk, reset;
-    reg [7:0] out;
-
-    always @(posedge clk, posedge reset)
-		if (reset) begin
-			out <= 8'b0 ;
-		end else
-			out <= out + 1;
-
-
-endmodule

tests/arch/xilinx/counter.ys

@@ -1,4 +1,4 @@
-read_verilog counter.v
+read_verilog ../common/counter.v
 hierarchy -top top
 proc
 flatten

tests/arch/xilinx/dffs.v

@@ -1,15 +0,0 @@
-module dff
-    ( input d, clk, output reg q );
-	always @( posedge clk )
-            q <= d;
-endmodule
-
-module dffe
-    ( input d, clk, en, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk )
-		if ( en )
-			q <= d;
-endmodule

tests/arch/xilinx/dffs.ys

@@ -1,4 +1,4 @@
-read_verilog dffs.v
+read_verilog ../common/dffs.v
 design -save read
 
 hierarchy -top dff

tests/arch/xilinx/fsm.v

@@ -1,55 +0,0 @@
- module fsm (
- clock,
- reset,
- req_0,
- req_1,
- gnt_0,
- gnt_1
- );
- input   clock,reset,req_0,req_1;
- output  gnt_0,gnt_1;
- wire    clock,reset,req_0,req_1;
- reg     gnt_0,gnt_1;
-
- parameter SIZE = 3           ;
- parameter IDLE  = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
-
- reg [SIZE-1:0] state;
- reg [SIZE-1:0] next_state;
-
- always @ (posedge clock)
- begin : FSM
- if (reset == 1'b1) begin
-   state <=  #1  IDLE;
-   gnt_0 <= 0;
-   gnt_1 <= 0;
- end else
-  case(state)
-    IDLE : if (req_0 == 1'b1) begin
-                 state <=  #1  GNT0;
-                 gnt_0 <= 1;
-               end else if (req_1 == 1'b1) begin
-                 gnt_1 <= 1;
-                 state <=  #1  GNT0;
-               end else begin
-                 state <=  #1  IDLE;
-               end
-    GNT0 : if (req_0 == 1'b1) begin
-                 state <=  #1  GNT0;
-               end else begin
-                 gnt_0 <= 0;
-                 state <=  #1  IDLE;
-               end
-    GNT1 : if (req_1 == 1'b1) begin
-                 state <=  #1  GNT2;
-				 gnt_1 <= req_0;
-               end
-    GNT2 : if (req_0 == 1'b1) begin
-                 state <=  #1  GNT1;
-				 gnt_1 <= req_1;
-               end
-    default : state <=  #1  IDLE;
- endcase
- end
-
-endmodule

tests/arch/xilinx/fsm.ys

@@ -1,4 +1,4 @@
-read_verilog fsm.v
+read_verilog ../common/fsm.v
 hierarchy -top fsm
 proc
 flatten

tests/arch/xilinx/latches.v

@@ -1,24 +0,0 @@
-module latchp
-    ( input d, clk, en, output reg q );
-	always @*
-		if ( en )
-			q <= d;
-endmodule
-
-module latchn
-    ( input d, clk, en, output reg q );
-	always @*
-		if ( !en )
-			q <= d;
-endmodule
-
-module latchsr
-    ( input d, clk, en, clr, pre, output reg q );
-	always @*
-		if ( clr )
-			q <= 1'b0;
-		else if ( pre )
-			q <= 1'b1;
-		else if ( en )
-			q <= d;
-endmodule

tests/arch/xilinx/latches.ys

@@ -1,4 +1,4 @@
-read_verilog latches.v
+read_verilog ../common/latches.v
 design -save read
 
 hierarchy -top latchp

tests/arch/xilinx/logic.v

@@ -1,18 +0,0 @@
-module top
-(
- input [0:7] in,
- output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10
- );
-
-   assign     B1 =  in[0] & in[1];
-   assign     B2 =  in[0] | in[1];
-   assign     B3 =  in[0] ~& in[1];
-   assign     B4 =  in[0] ~| in[1];
-   assign     B5 =  in[0] ^ in[1];
-   assign     B6 =  in[0] ~^ in[1];
-   assign     B7 =  ~in[0];
-   assign     B8 =  in[0];
-   assign     B9 =  in[0:1] && in [2:3];
-   assign     B10 =  in[0:1] || in [2:3];
-
-endmodule

tests/arch/xilinx/logic.ys

@@ -1,4 +1,4 @@
-read_verilog logic.v
+read_verilog ../common/logic.v
 hierarchy -top top
 proc
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check

tests/arch/xilinx/mul.v

@@ -1,11 +0,0 @@
-module top
-(
- input [5:0] x,
- input [5:0] y,
-
- output [11:0] A,
- );
-
-assign A =  x * y;
-
-endmodule

tests/arch/xilinx/mul.ys

@@ -1,4 +1,4 @@
-read_verilog mul.v
+read_verilog ../common/mul.v
 hierarchy -top top
 proc
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check

tests/arch/xilinx/mux.v

@@ -1,65 +0,0 @@
-module mux2 (S,A,B,Y);
-    input S;
-    input A,B;
-    output reg Y;
-
-    always @(*)
-		Y = (S)? B : A;
-endmodule
-
-module mux4 ( S, D, Y );
-
-input[1:0] S;
-input[3:0] D;
-output Y;
-
-reg Y;
-wire[1:0] S;
-wire[3:0] D;
-
-always @*
-begin
-    case( S )
-       0 : Y = D[0];
-       1 : Y = D[1];
-       2 : Y = D[2];
-       3 : Y = D[3];
-   endcase
-end
-
-endmodule
-
-module mux8 ( S, D, Y );
-
-input[2:0] S;
-input[7:0] D;
-output Y;
-
-reg Y;
-wire[2:0] S;
-wire[7:0] D;
-
-always @*
-begin
-   case( S )
-       0 : Y = D[0];
-       1 : Y = D[1];
-       2 : Y = D[2];
-       3 : Y = D[3];
-       4 : Y = D[4];
-       5 : Y = D[5];
-       6 : Y = D[6];
-       7 : Y = D[7];
-   endcase
-end
-
-endmodule
-
-module mux16 (D, S, Y);
- 	input  [15:0] D;
- 	input  [3:0] S;
- 	output Y;
-
-assign Y = D[S];
-
-endmodule

tests/arch/xilinx/mux.ys

@@ -1,4 +1,4 @@
-read_verilog mux.v
+read_verilog ../common/mux.v
 design -save read
 
 hierarchy -top mux2

tests/arch/xilinx/shifter.v

@@ -1,16 +0,0 @@
-module top    (
-out,
-clk,
-in
-);
-    output [7:0] out;
-    input signed clk, in;
-    reg signed [7:0] out = 0;
-
-    always @(posedge clk)
-	begin
-		out    <= out >> 1;
-		out[7] <= in;
-	end
-
-endmodule