riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge pull request #1260 from YosysHQ/dave/ecp5_cell_fixes 

ecp5: Make cells_sim.v consistent with nextpnr
This commit is contained in:
David Shah 2019-08-07 15:35:29 +01:00 committed by GitHub
parent e9a756aa7a a36fd8582e
commit 5545cd3c10
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 237 additions and 94 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

177
techlibs/ecp5/cells_sim.v
View File

@ -333,6 +333,31 @@ module TRELLIS_SLICE(
parameter [127:0] CCU2_INJECT1_0 = "NO"; parameter [127:0] CCU2_INJECT1_0 = "NO";
parameter [127:0] CCU2_INJECT1_1 = "NO"; parameter [127:0] CCU2_INJECT1_1 = "NO";
parameter WREMUX = "WRE"; parameter WREMUX = "WRE";
parameter WCKMUX = "WCK";
parameter A0MUX = "A0";
parameter A1MUX = "A1";
parameter B0MUX = "B0";
parameter B1MUX = "B1";
parameter C0MUX = "C0";
parameter C1MUX = "C1";
parameter D0MUX = "D0";
parameter D1MUX = "D1";
wire A0m, B0m, C0m, D0m;
wire A1m, B1m, C1m, D1m;
generate
if (A0MUX == "1") assign A0m = 1'b1; else assign A0m = A0;
if (B0MUX == "1") assign B0m = 1'b1; else assign B0m = B0;
if (C0MUX == "1") assign C0m = 1'b1; else assign C0m = C0;
if (D0MUX == "1") assign D0m = 1'b1; else assign D0m = D0;
if (A1MUX == "1") assign A1m = 1'b1; else assign A1m = A1;
if (B1MUX == "1") assign B1m = 1'b1; else assign B1m = B1;
if (C1MUX == "1") assign C1m = 1'b1; else assign C1m = C1;
if (D1MUX == "1") assign D1m = 1'b1; else assign D1m = D1;
endgenerate
function [15:0] permute_initval; function [15:0] permute_initval;
input [15:0] initval; input [15:0] initval;
@ -350,13 +375,13 @@ module TRELLIS_SLICE(
LUT4 #( LUT4 #(
.INIT(LUT0_INITVAL) .INIT(LUT0_INITVAL)
) lut4_0 ( ) lut4_0 (
.A(A0), .B(B0), .C(C0), .D(D0), .A(A0m), .B(B0m), .C(C0m), .D(D0m),
.Z(F0) .Z(F0)
); );
LUT4 #( LUT4 #(
.INIT(LUT1_INITVAL) .INIT(LUT1_INITVAL)
) lut4_1 ( ) lut4_1 (
.A(A1), .B(B1), .C(C1), .D(D1), .A(A1m), .B(B1m), .C(C1m), .D(D1m),
.Z(F1) .Z(F1)
); );
// LUT expansion muxes // LUT expansion muxes
@ -370,20 +395,20 @@ module TRELLIS_SLICE(
.INJECT1_1(CCU2_INJECT1_1) .INJECT1_1(CCU2_INJECT1_1)
) ccu2c_i ( ) ccu2c_i (
.CIN(FCI), .CIN(FCI),
.A0(A0), .B0(B0), .C0(C0), .D0(D0), .A0(A0m), .B0(B0m), .C0(C0m), .D0(D0m),
.A1(A1), .B1(B1), .C1(C1), .D1(D1), .A1(A1m), .B1(B1m), .C1(C1m), .D1(D1m),
.S0(F0), .S1(F1), .S0(F0), .S1(F1),
.COUT(FCO) .COUT(FCO)
); );
end else if (MODE == "RAMW") begin end else if (MODE == "RAMW") begin
assign WDO0 = C1; assign WDO0 = C1m;
assign WDO1 = A1; assign WDO1 = A1m;
assign WDO2 = D1; assign WDO2 = D1m;
assign WDO3 = B1; assign WDO3 = B1m;
assign WADO0 = D0; assign WADO0 = D0m;
assign WADO1 = B0; assign WADO1 = B0m;
assign WADO2 = C0; assign WADO2 = C0m;
assign WADO3 = A0; assign WADO3 = A0m;
end else if (MODE == "DPRAM") begin end else if (MODE == "DPRAM") begin
TRELLIS_RAM16X2 #( TRELLIS_RAM16X2 #(
.INITVAL_0(permute_initval(LUT0_INITVAL)), .INITVAL_0(permute_initval(LUT0_INITVAL)),
@ -393,17 +418,19 @@ module TRELLIS_SLICE(
.DI0(WD0), .DI1(WD1), .DI0(WD0), .DI1(WD1),
.WAD0(WAD0), .WAD1(WAD1), .WAD2(WAD2), .WAD3(WAD3), .WAD0(WAD0), .WAD1(WAD1), .WAD2(WAD2), .WAD3(WAD3),
.WRE(WRE), .WCK(WCK), .WRE(WRE), .WCK(WCK),
.RAD0(D0), .RAD1(B0), .RAD2(C0), .RAD3(A0), .RAD0(D0m), .RAD1(B0m), .RAD2(C0m), .RAD3(A0m),
.DO0(F0), .DO1(F1) .DO0(F0), .DO1(F1)
); );
// TODO: confirm RAD and INITVAL ordering // TODO: confirm RAD and INITVAL ordering
// DPRAM mode contract? // DPRAM mode contract?
`ifdef FORMAL
always @(*) begin always @(*) begin
assert(A0==A1); assert(A0m==A1m);
assert(B0==B1); assert(B0m==B1m);
assert(C0==C1); assert(C0m==C1m);
assert(D0==D1); assert(D0m==D1m);
end end
`endif
end else begin end else begin
ERROR_UNKNOWN_SLICE_MODE error(); ERROR_UNKNOWN_SLICE_MODE error();
end end
@ -470,8 +497,124 @@ module DP16KD(
parameter WRITEMODE_A = "NORMAL"; parameter WRITEMODE_A = "NORMAL";
parameter WRITEMODE_B = "NORMAL"; parameter WRITEMODE_B = "NORMAL";
parameter DIA17MUX = "DIA17";
parameter DIA16MUX = "DIA16";
parameter DIA15MUX = "DIA15";
parameter DIA14MUX = "DIA14";
parameter DIA13MUX = "DIA13";
parameter DIA12MUX = "DIA12";
parameter DIA11MUX = "DIA11";
parameter DIA10MUX = "DIA10";
parameter DIA9MUX = "DIA9";
parameter DIA8MUX = "DIA8";
parameter DIA7MUX = "DIA7";
parameter DIA6MUX = "DIA6";
parameter DIA5MUX = "DIA5";
parameter DIA4MUX = "DIA4";
parameter DIA3MUX = "DIA3";
parameter DIA2MUX = "DIA2";
parameter DIA1MUX = "DIA1";
parameter DIA0MUX = "DIA0";
parameter ADA13MUX = "ADA13";
parameter ADA12MUX = "ADA12";
parameter ADA11MUX = "ADA11";
parameter ADA10MUX = "ADA10";
parameter ADA9MUX = "ADA9";
parameter ADA8MUX = "ADA8";
parameter ADA7MUX = "ADA7";
parameter ADA6MUX = "ADA6";
parameter ADA5MUX = "ADA5";
parameter ADA4MUX = "ADA4";
parameter ADA3MUX = "ADA3";
parameter ADA2MUX = "ADA2";
parameter ADA1MUX = "ADA1";
parameter ADA0MUX = "ADA0";
parameter CEAMUX = "CEA";
parameter OCEAMUX = "OCEA";
parameter CLKAMUX = "CLKA"; parameter CLKAMUX = "CLKA";
parameter WEAMUX = "WEA";
parameter RSTAMUX = "RSTA";
parameter CSA2MUX = "CSA2";
parameter CSA1MUX = "CSA1";
parameter CSA0MUX = "CSA0";
parameter DOA17MUX = "DOA17";
parameter DOA16MUX = "DOA16";
parameter DOA15MUX = "DOA15";
parameter DOA14MUX = "DOA14";
parameter DOA13MUX = "DOA13";
parameter DOA12MUX = "DOA12";
parameter DOA11MUX = "DOA11";
parameter DOA10MUX = "DOA10";
parameter DOA9MUX = "DOA9";
parameter DOA8MUX = "DOA8";
parameter DOA7MUX = "DOA7";
parameter DOA6MUX = "DOA6";
parameter DOA5MUX = "DOA5";
parameter DOA4MUX = "DOA4";
parameter DOA3MUX = "DOA3";
parameter DOA2MUX = "DOA2";
parameter DOA1MUX = "DOA1";
parameter DOA0MUX = "DOA0";
parameter DIB17MUX = "DIB17";
parameter DIB16MUX = "DIB16";
parameter DIB15MUX = "DIB15";
parameter DIB14MUX = "DIB14";
parameter DIB13MUX = "DIB13";
parameter DIB12MUX = "DIB12";
parameter DIB11MUX = "DIB11";
parameter DIB10MUX = "DIB10";
parameter DIB9MUX = "DIB9";
parameter DIB8MUX = "DIB8";
parameter DIB7MUX = "DIB7";
parameter DIB6MUX = "DIB6";
parameter DIB5MUX = "DIB5";
parameter DIB4MUX = "DIB4";
parameter DIB3MUX = "DIB3";
parameter DIB2MUX = "DIB2";
parameter DIB1MUX = "DIB1";
parameter DIB0MUX = "DIB0";
parameter ADB13MUX = "ADB13";
parameter ADB12MUX = "ADB12";
parameter ADB11MUX = "ADB11";
parameter ADB10MUX = "ADB10";
parameter ADB9MUX = "ADB9";
parameter ADB8MUX = "ADB8";
parameter ADB7MUX = "ADB7";
parameter ADB6MUX = "ADB6";
parameter ADB5MUX = "ADB5";
parameter ADB4MUX = "ADB4";
parameter ADB3MUX = "ADB3";
parameter ADB2MUX = "ADB2";
parameter ADB1MUX = "ADB1";
parameter ADB0MUX = "ADB0";
parameter CEBMUX = "CEB";
parameter OCEBMUX = "OCEB";
parameter CLKBMUX = "CLKB"; parameter CLKBMUX = "CLKB";
parameter WEBMUX = "WEB";
parameter RSTBMUX = "RSTB";
parameter CSB2MUX = "CSB2";
parameter CSB1MUX = "CSB1";
parameter CSB0MUX = "CSB0";
parameter DOB17MUX = "DOB17";
parameter DOB16MUX = "DOB16";
parameter DOB15MUX = "DOB15";
parameter DOB14MUX = "DOB14";
parameter DOB13MUX = "DOB13";
parameter DOB12MUX = "DOB12";
parameter DOB11MUX = "DOB11";
parameter DOB10MUX = "DOB10";
parameter DOB9MUX = "DOB9";
parameter DOB8MUX = "DOB8";
parameter DOB7MUX = "DOB7";
parameter DOB6MUX = "DOB6";
parameter DOB5MUX = "DOB5";
parameter DOB4MUX = "DOB4";
parameter DOB3MUX = "DOB3";
parameter DOB2MUX = "DOB2";
parameter DOB1MUX = "DOB1";
parameter DOB0MUX = "DOB0";
parameter WID = 0;
parameter GSR = "ENABLED"; parameter GSR = "ENABLED";