riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig

This commit is contained in:
Eddie Hung 2019-06-27 15:30:00 -07:00
parent a625854ac5 9a371cfba9
commit 550760cc72
2 changed files with 19 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Makefile
View File

@ -681,6 +681,7 @@ test: $(TARGETS) $(EXTRA_TARGETS)
+cd tests/svinterfaces && bash run-test.sh $(SEEDOPT) +cd tests/svinterfaces && bash run-test.sh $(SEEDOPT)
+cd tests/opt && bash run-test.sh +cd tests/opt && bash run-test.sh
+cd tests/aiger && bash run-test.sh +cd tests/aiger && bash run-test.sh
+cd tests/arch && bash run-test.sh
+cd tests/simple_abc9 && bash run-test.sh $(SEEDOPT) +cd tests/simple_abc9 && bash run-test.sh $(SEEDOPT)
@echo "" @echo ""
@echo " Passed \"make test\"." @echo " Passed \"make test\"."

18
tests/arch/run-test.sh Executable file
View File

@ -0,0 +1,18 @@
#!/bin/bash
set -e
echo "Running syntax check on arch sim models"
for arch in ../../techlibs/*; do
find $arch -name cells_sim.v | while read path; do
echo -n "Test $path ->"
iverilog -t null -I$arch $path
echo " ok"
done
done
for path in "../../techlibs/common/simcells.v" "../../techlibs/common/simlib.v"; do
echo -n "Test $path ->"
iverilog -t null $path
echo " ok"
done