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Remove delays from abc_map.v

This commit is contained in:
Eddie Hung 2019-08-20 17:52:27 -07:00
parent 96f00e9147
commit 54284aaa98
1 changed files with 2 additions and 5 deletions
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7
techlibs/xilinx/abc_map.v
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@ -20,8 +20,6 @@
// ============================================================================ // ============================================================================
// Max delays from https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L237-L251
module FDRE (output reg Q, input C, CE, D, R); module FDRE (output reg Q, input C, CE, D, R);
parameter [0:0] INIT = 1'b0; parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0;
@ -205,9 +203,8 @@ module SRL16E (
endmodule endmodule
module SRLC32E ( module SRLC32E (
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905 output Q,
(* abc_arrival=1472 *) output Q, output Q31,
(* abc_arrival=1114 *) output Q31,
input [4:0] A, input [4:0] A,
input CE, CLK, D input CE, CLK, D
); );