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Basic support for tag primitives

This commit is contained in:
Miodrag Milanovic 2023-06-07 10:20:16 +02:00 committed by Jannis Harder
parent 9e004426e0
commit 54050a8c16
6 changed files with 176 additions and 0 deletions
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32
frontends/verific/verific.cc
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@ -1103,6 +1103,38 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
return true; return true;
} }
if (inst->Type() == OPER_YOSYSHQ_SET_TAG)
{
RTLIL::SigSpec sig_expr = operatorInport(inst, "expr");
RTLIL::SigSpec sig_set_mask = operatorInport(inst, "set_mask");
RTLIL::SigSpec sig_clr_mask = operatorInport(inst, "clr_mask");
RTLIL::SigSpec sig_o = operatorOutput(inst);
std::string tag = inst->GetAtt("tag") ? inst->GetAttValue("tag") : "";
module->connect(sig_o, module->SetTag(new_verific_id(inst), tag, sig_expr, sig_set_mask, sig_clr_mask));
return true;
}
if (inst->Type() == OPER_YOSYSHQ_GET_TAG)
{
std::string tag = inst->GetAtt("tag") ? inst->GetAttValue("tag") : "";
module->connect(operatorOutput(inst),module->GetTag(new_verific_id(inst), tag, operatorInput(inst)));
return true;
}
if (inst->Type() == OPER_YOSYSHQ_OVERWRITE_TAG)
{
RTLIL::SigSpec sig_signal = operatorInport(inst, "signal");
RTLIL::SigSpec sig_set_mask = operatorInport(inst, "set_mask");
RTLIL::SigSpec sig_clr_mask = operatorInport(inst, "clr_mask");
std::string tag = inst->GetAtt("tag") ? inst->GetAttValue("tag") : "";
module->addOverwriteTag(new_verific_id(inst), tag, sig_signal, sig_set_mask, sig_clr_mask);
return true;
}
if (inst->Type() == OPER_YOSYSHQ_ORIGINAL_TAG)
{
std::string tag = inst->GetAtt("tag") ? inst->GetAttValue("tag") : "";
module->connect(operatorOutput(inst),module->OriginalTag(new_verific_id(inst), tag, operatorInput(inst)));
return true;
}
#undef IN #undef IN
#undef IN1 #undef IN1
#undef IN2 #undef IN2

4
kernel/celltypes.h
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@ -102,6 +102,10 @@ struct CellTypes
setup_type(ID($specify3), {ID::EN, ID::SRC, ID::DST, ID::DAT}, pool<RTLIL::IdString>(), true); setup_type(ID($specify3), {ID::EN, ID::SRC, ID::DST, ID::DAT}, pool<RTLIL::IdString>(), true);
setup_type(ID($specrule), {ID::EN_SRC, ID::EN_DST, ID::SRC, ID::DST}, pool<RTLIL::IdString>(), true); setup_type(ID($specrule), {ID::EN_SRC, ID::EN_DST, ID::SRC, ID::DST}, pool<RTLIL::IdString>(), true);
setup_type(ID($print), {ID::EN, ID::ARGS, ID::TRG}, pool<RTLIL::IdString>()); setup_type(ID($print), {ID::EN, ID::ARGS, ID::TRG}, pool<RTLIL::IdString>());
setup_type(ID($set_tag), {ID::A, ID::SET, ID::CLR}, {ID::Y});
setup_type(ID($get_tag), {ID::A}, {ID::Y});
setup_type(ID($overwrite_tag), {ID::A, ID::SET, ID::CLR}, pool<RTLIL::IdString>());
setup_type(ID($original_tag), {ID::A}, {ID::Y});
} }
void setup_internals_eval() void setup_internals_eval()

1
kernel/constids.inc
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@ -208,6 +208,7 @@ X(syn_romstyle)
X(S_WIDTH) X(S_WIDTH)
X(T) X(T)
X(TABLE) X(TABLE)
X(TAG)
X(techmap_autopurge) X(techmap_autopurge)
X(_TECHMAP_BITS_CONNMAP_) X(_TECHMAP_BITS_CONNMAP_)
X(_TECHMAP_CELLNAME_) X(_TECHMAP_CELLNAME_)

77
kernel/rtlil.cc
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@ -1828,6 +1828,33 @@ namespace {
ID($_DLATCHSR_PNN_), ID($_DLATCHSR_PNP_), ID($_DLATCHSR_PPN_), ID($_DLATCHSR_PPP_))) ID($_DLATCHSR_PNN_), ID($_DLATCHSR_PNP_), ID($_DLATCHSR_PPN_), ID($_DLATCHSR_PPP_)))
{ port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; } { port(ID::E,1); port(ID::S,1); port(ID::R,1); port(ID::D,1); port(ID::Q,1); check_expected(); return; }
if (cell->type.in(ID($set_tag))) {
param(ID::WIDTH);
param(ID::TAG);
port(ID::A, param(ID::WIDTH));
port(ID::SET, param(ID::WIDTH));
port(ID::CLR, param(ID::WIDTH));
port(ID::Y, param(ID::WIDTH));
check_expected();
return;
}
if (cell->type.in(ID($get_tag),ID($original_tag))) {
param(ID::WIDTH);
param(ID::TAG);
port(ID::A, param(ID::WIDTH));
port(ID::Y, param(ID::WIDTH));
check_expected();
return;
}
if (cell->type.in(ID($overwrite_tag))) {
param(ID::WIDTH);
param(ID::TAG);
port(ID::A, param(ID::WIDTH));
port(ID::SET, param(ID::WIDTH));
port(ID::CLR, param(ID::WIDTH));
check_expected();
return;
}
error(__LINE__); error(__LINE__);
} }
}; };
@ -3246,6 +3273,56 @@ RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string
return sig; return sig;
} }
RTLIL::SigSpec RTLIL::Module::SetTag(RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_e, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src)
{
RTLIL::SigSpec sig = addWire(NEW_ID, sig_e.size());
Cell *cell = addCell(name, ID($set_tag));
cell->parameters[ID::WIDTH] = sig_e.size();
cell->parameters[ID::TAG] = tag;
cell->setPort(ID::A, sig_e);
cell->setPort(ID::SET, sig_s);
cell->setPort(ID::CLR, sig_c);
cell->setPort(ID::Y, sig);
cell->set_src_attribute(src);
return sig;
}
RTLIL::SigSpec RTLIL::Module::GetTag(RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_e, const std::string &src)
{
RTLIL::SigSpec sig = addWire(NEW_ID, sig_e.size());
Cell *cell = addCell(name, ID($get_tag));
cell->parameters[ID::WIDTH] = sig_e.size();
cell->parameters[ID::TAG] = tag;
cell->setPort(ID::A, sig_e);
cell->setPort(ID::Y, sig);
cell->set_src_attribute(src);
return sig;
}
RTLIL::Cell* RTLIL::Module::addOverwriteTag(RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_e, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, ID($overwrite_tag));
cell->parameters[ID::WIDTH] = sig_e.size();
cell->parameters[ID::TAG] = tag;
cell->setPort(ID::A, sig_e);
cell->setPort(ID::SET, sig_s);
cell->setPort(ID::CLR, sig_c);
cell->set_src_attribute(src);
return cell;
}
RTLIL::SigSpec RTLIL::Module::OriginalTag(RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_e, const std::string &src)
{
RTLIL::SigSpec sig = addWire(NEW_ID, sig_e.size());
Cell *cell = addCell(name, ID($original_tag));
cell->parameters[ID::WIDTH] = sig_e.size();
cell->parameters[ID::TAG] = tag;
cell->setPort(ID::A, sig_e);
cell->setPort(ID::Y, sig);
cell->set_src_attribute(src);
return sig;
}
RTLIL::Wire::Wire() RTLIL::Wire::Wire()
{ {
static unsigned int hashidx_count = 123456789; static unsigned int hashidx_count = 123456789;

5
kernel/rtlil.h
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@ -1465,6 +1465,11 @@ public:
RTLIL::SigSpec Allseq (RTLIL::IdString name, int width = 1, const std::string &src = ""); RTLIL::SigSpec Allseq (RTLIL::IdString name, int width = 1, const std::string &src = "");
RTLIL::SigSpec Initstate (RTLIL::IdString name, const std::string &src = ""); RTLIL::SigSpec Initstate (RTLIL::IdString name, const std::string &src = "");
RTLIL::SigSpec SetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_e, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src = "");
RTLIL::SigSpec GetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_e, const std::string &src = "");
RTLIL::Cell* addOverwriteTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_e, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const std::string &src = "");
RTLIL::SigSpec OriginalTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_e, const std::string &src = "");
#ifdef WITH_PYTHON #ifdef WITH_PYTHON
static std::map<unsigned int, RTLIL::Module*> *get_all_modules(void); static std::map<unsigned int, RTLIL::Module*> *get_all_modules(void);
#endif #endif

57
techlibs/common/simlib.v
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@ -2671,3 +2671,60 @@ endmodule
`endif `endif
// -------------------------------------------------------- // --------------------------------------------------------
module \$set_tag (A, SET, CLR, Y);
parameter TAG = "";
parameter WIDTH = 0;
input [WIDTH-1:0] A;
input [WIDTH-1:0] SET;
input [WIDTH-1:0] CLR;
output [WIDTH-1:0] Y;
assign Y = A;
endmodule
// --------------------------------------------------------
module \$get_tag (A, Y);
parameter TAG = "";
parameter WIDTH = 0;
input [WIDTH-1:0] A;
output [WIDTH-1:0] Y;
assign Y = A;
endmodule
// --------------------------------------------------------
module \$overwrite_tag (A, SET, CLR);
parameter TAG = "";
parameter WIDTH = 0;
input [WIDTH-1:0] A;
input [WIDTH-1:0] SET;
input [WIDTH-1:0] CLR;
endmodule
// --------------------------------------------------------
module \$original_tag (A, Y);
parameter TAG = "";
parameter WIDTH = 0;
input [WIDTH-1:0] A;
output [WIDTH-1:0] Y;
assign Y = A;
endmodule
// --------------------------------------------------------