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Call 'wreduce' after mul2dsp to avoid unextend()

This commit is contained in:
Eddie Hung 2019-09-25 14:04:36 -07:00
parent 93363c94a2
commit 53ea5daa42
2 changed files with 5 additions and 5 deletions
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9
passes/pmgen/xilinx_dsp.pmg
View File

@ -1,6 +1,5 @@
pattern xilinx_dsp_pack
udata <std::function<SigSpec(const SigSpec&)>> unextend
state <SigBit> clock
state <SigSpec> sigA sigB sigC sigD sigM sigP
state <IdString> postAddAB postAddMuxAB
@ -25,7 +24,7 @@ match dsp
endmatch
code sigA sigB sigC sigD sigM clock
unextend = [](const SigSpec &sig) {
auto unextend = [](const SigSpec &sig) {
int i;
for (i = GetSize(sig)-1; i > 0; i--)
if (sig[i] != sig[i-1])
@ -272,9 +271,9 @@ match postAdd
filter !ffMcemux || nusers(port(postAdd, AB)) == 3
index <SigBit> port(postAdd, AB)[0] === sigP[0]
filter GetSize(unextend(port(postAdd, AB))) <= GetSize(sigP)
filter unextend(port(postAdd, AB)) == sigP.extract(0, GetSize(unextend(port(postAdd, AB))))
filter nusers(sigP.extract_end(GetSize(unextend(port(postAdd, AB))))) <= 1
filter GetSize(port(postAdd, AB)) <= GetSize(sigP)
filter port(postAdd, AB) == sigP.extract(0, GetSize(port(postAdd, AB)))
filter nusers(sigP.extract_end(GetSize(port(postAdd, AB)))) <= 1
set postAddAB AB
optional
endmatch

1
techlibs/xilinx/synth_xilinx.cc
View File

@ -346,6 +346,7 @@ struct SynthXilinxPass : public ScriptPass
"-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers
"-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller
"-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18");
run("wreduce t:$add");
run("xilinx_dsp");
run("chtype -set $mul t:$__soft_mul");
}