Clean verilog code from not used define block

tests/xilinx/shifter.v

@@ -9,14 +9,8 @@ in
 
     always @(posedge clk)
 	begin
-`ifndef BUG
 		out    <= out >> 1;
 		out[7] <= in;
-`else
-
-		out    <= out << 1;
-		out[7] <= in;
-`endif
 	end
 
 endmodule

tests/xilinx/tribuf.v

@@ -2,15 +2,9 @@ module tristate (en, i, o);
     input en;
     input i;
     output reg o;
-`ifndef BUG 
     
     always @(en or i)
 		o <= (en)? i : 1'bZ;
-`else
-	
-    always @(en or i)
-		o <= (en)? ~i : 1'bZ;
-`endif
 endmodule