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Use new port/param overload in pmg

This commit is contained in:
Eddie Hung 2019-09-20 14:21:22 -07:00
parent d122083a11
commit 53817b8575
4 changed files with 22 additions and 22 deletions
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4
passes/pmgen/ice40_dsp.pmg
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@ -225,9 +225,9 @@ endcode
code argD ffO ffOholdmux ffOrstmux ffOholdpol ffOrstpol sigO sigCD clock clock_pol cd_signed o_lo code argD ffO ffOholdmux ffOrstmux ffOholdpol ffOrstpol sigO sigCD clock clock_pol cd_signed o_lo
if (mul->type != \SB_MAC16 || if (mul->type != \SB_MAC16 ||
// Ensure that register is not already used // Ensure that register is not already used
((mul->parameters.at(\TOPOUTPUT_SELECT, 0).as_int() != 1 && mul->parameters.at(\BOTOUTPUT_SELECT, 0).as_int() != 1) && ((param(mul, \TOPOUTPUT_SELECT, 0).as_int() != 1 && param(mul, \BOTOUTPUT_SELECT, 0).as_int() != 1) &&
// Ensure that OLOADTOP/OLOADBOT is unused or zero // Ensure that OLOADTOP/OLOADBOT is unused or zero
(mul->connections_.at(\OLOADTOP, State::S0).is_fully_zero() && mul->connections_.at(\OLOADBOT, State::S0).is_fully_zero()))) { (port(mul, \OLOADTOP, State::S0).is_fully_zero() && port(mul, \OLOADBOT, State::S0).is_fully_zero()))) {
dff = nullptr; dff = nullptr;

2
passes/pmgen/xilinx_dsp.cc
View File

@ -290,7 +290,7 @@ void pack_xilinx_dsp(xilinx_dsp_pm &pm)
st.sigD.extend_u0(25, D_SIGNED); st.sigD.extend_u0(25, D_SIGNED);
cell->setPort(ID(A), st.sigA); cell->setPort(ID(A), st.sigA);
cell->setPort(ID(D), st.sigD); cell->setPort(ID(D), st.sigD);
cell->connections_.at(ID(INMODE)) = Const::from_string("00100"); cell->setPort(ID(INMODE), Const::from_string("00100"));
if (st.ffAD) { if (st.ffAD) {
if (st.ffADcemux) { if (st.ffADcemux) {

8
passes/pmgen/xilinx_dsp.pmg
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@ -42,7 +42,7 @@ code sigA sigB sigC sigD sigM
sigD = dsp->connections_.at(\D, SigSpec()); sigD = dsp->connections_.at(\D, SigSpec());
SigSpec P = port(dsp, \P); SigSpec P = port(dsp, \P);
if (dsp->parameters.at(\USE_MULT, Const("MULTIPLY")).decode_string() == "MULTIPLY") { if (param(dsp, \USE_MULT, Const("MULTIPLY")).decode_string() == "MULTIPLY") {
// Only care about those bits that are used // Only care about those bits that are used
int i; int i;
for (i = 0; i < GetSize(P); i++) { for (i = 0; i < GetSize(P); i++) {
@ -79,8 +79,8 @@ endcode
match preAdd match preAdd
if sigD.empty() || sigD.is_fully_zero() if sigD.empty() || sigD.is_fully_zero()
// Ensure that preAdder not already used // Ensure that preAdder not already used
if dsp->parameters.at(\USE_DPORT, Const("FALSE")).decode_string() == "FALSE" if param(dsp, \USE_DPORT, Const("FALSE")).decode_string() == "FALSE"
if dsp->connections_.at(\INMODE, Const(0, 5)).is_fully_zero() if port(dsp, \INMODE, Const(0, 5)).is_fully_zero()
select preAdd->type.in($add) select preAdd->type.in($add)
// Output has to be 25 bits or less // Output has to be 25 bits or less
@ -348,7 +348,7 @@ endcode
match overflow match overflow
if ffP if ffP
if dsp->parameters.at(\USE_PATTERN_DETECT, Const("NO_PATDET")).decode_string() == "NO_PATDET" if param(dsp, \USE_PATTERN_DETECT, Const("NO_PATDET")).decode_string() == "NO_PATDET"
select overflow->type.in($ge) select overflow->type.in($ge)
select GetSize(port(overflow, \Y)) <= 48 select GetSize(port(overflow, \Y)) <= 48
select port(overflow, \B).is_fully_const() select port(overflow, \B).is_fully_const()

30
passes/pmgen/xilinx_srl.pmg
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@ -13,9 +13,9 @@ endcode
match first match first
select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1) select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
select !first->has_keep_attr() select !first->has_keep_attr()
select !first->type.in(\FDRE) || !first->parameters.at(\IS_R_INVERTED, State::S0).as_bool() select !first->type.in(\FDRE) || !param(first, \IS_R_INVERTED, State::S0).as_bool()
select !first->type.in(\FDRE) || !first->parameters.at(\IS_D_INVERTED, State::S0).as_bool() select !first->type.in(\FDRE) || !param(first, \IS_D_INVERTED, State::S0).as_bool()
select !first->type.in(\FDRE, \FDRE_1) || first->connections_.at(\R, State::S0).is_fully_zero() select !first->type.in(\FDRE, \FDRE_1) || port(first, \R, State::S0).is_fully_zero()
filter !non_first_cells.count(first) filter !non_first_cells.count(first)
generate generate
SigSpec C = module->addWire(NEW_ID); SigSpec C = module->addWire(NEW_ID);
@ -84,9 +84,9 @@ arg en_port
match first match first
select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1) select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
select !first->has_keep_attr() select !first->has_keep_attr()
select !first->type.in(\FDRE) || !first->parameters.at(\IS_R_INVERTED, State::S0).as_bool() select !first->type.in(\FDRE) || !param(first, \IS_R_INVERTED, State::S0).as_bool()
select !first->type.in(\FDRE) || !first->parameters.at(\IS_D_INVERTED, State::S0).as_bool() select !first->type.in(\FDRE) || !param(first, \IS_D_INVERTED, State::S0).as_bool()
select !first->type.in(\FDRE, \FDRE_1) || first->connections_.at(\R, State::S0).is_fully_zero() select !first->type.in(\FDRE, \FDRE_1) || port(first, \R, State::S0).is_fully_zero()
endmatch endmatch
code clk_port en_port code clk_port en_port
@ -111,10 +111,10 @@ match next
index <SigBit> port(next, \Q) === port(first, \D) index <SigBit> port(next, \Q) === port(first, \D)
filter port(next, clk_port) == port(first, clk_port) filter port(next, clk_port) == port(first, clk_port)
filter en_port == IdString() || port(next, en_port) == port(first, en_port) filter en_port == IdString() || port(next, en_port) == port(first, en_port)
filter !first->type.in(\FDRE) || next->parameters.at(\IS_C_INVERTED, State::S0).as_bool() == first->parameters.at(\IS_C_INVERTED, State::S0).as_bool() filter !first->type.in(\FDRE) || param(next, \IS_C_INVERTED, State::S0).as_bool() == param(first, \IS_C_INVERTED, State::S0).as_bool()
filter !first->type.in(\FDRE) || next->parameters.at(\IS_D_INVERTED, State::S0).as_bool() == first->parameters.at(\IS_D_INVERTED, State::S0).as_bool() filter !first->type.in(\FDRE) || param(next, \IS_D_INVERTED, State::S0).as_bool() == param(first, \IS_D_INVERTED, State::S0).as_bool()
filter !first->type.in(\FDRE) || next->parameters.at(\IS_R_INVERTED, State::S0).as_bool() == first->parameters.at(\IS_R_INVERTED, State::S0).as_bool() filter !first->type.in(\FDRE) || param(next, \IS_R_INVERTED, State::S0).as_bool() == param(first, \IS_R_INVERTED, State::S0).as_bool()
filter !first->type.in(\FDRE, \FDRE_1) || next->connections_.at(\R, State::S0).is_fully_zero() filter !first->type.in(\FDRE, \FDRE_1) || port(next, \R, State::S0).is_fully_zero()
endmatch endmatch
code code
@ -138,10 +138,10 @@ match next
index <SigBit> port(next, \Q) === port(chain.back(), \D) index <SigBit> port(next, \Q) === port(chain.back(), \D)
filter port(next, clk_port) == port(first, clk_port) filter port(next, clk_port) == port(first, clk_port)
filter en_port == IdString() || port(next, en_port) == port(first, en_port) filter en_port == IdString() || port(next, en_port) == port(first, en_port)
filter !first->type.in(\FDRE) || next->parameters.at(\IS_C_INVERTED, State::S0).as_bool() == first->parameters.at(\IS_C_INVERTED, State::S0).as_bool() filter !first->type.in(\FDRE) || param(next, \IS_C_INVERTED, State::S0).as_bool() == param(first, \IS_C_INVERTED, State::S0).as_bool()
filter !first->type.in(\FDRE) || next->parameters.at(\IS_D_INVERTED, State::S0).as_bool() == first->parameters.at(\IS_D_INVERTED, State::S0).as_bool() filter !first->type.in(\FDRE) || param(next, \IS_D_INVERTED, State::S0).as_bool() == param(first, \IS_D_INVERTED, State::S0).as_bool()
filter !first->type.in(\FDRE) || next->parameters.at(\IS_R_INVERTED, State::S0).as_bool() == first->parameters.at(\IS_R_INVERTED, State::S0).as_bool() filter !first->type.in(\FDRE) || param(next, \IS_R_INVERTED, State::S0).as_bool() == param(first, \IS_R_INVERTED, State::S0).as_bool()
filter !first->type.in(\FDRE, \FDRE_1) || next->connections_.at(\R, State::S0).is_fully_zero() filter !first->type.in(\FDRE, \FDRE_1) || port(next, \R, State::S0).is_fully_zero()
generate generate
Cell *cell = module->addCell(NEW_ID, chain.back()->type); Cell *cell = module->addCell(NEW_ID, chain.back()->type);
cell->setPort(\C, chain.back()->getPort(\C)); cell->setPort(\C, chain.back()->getPort(\C));
@ -149,7 +149,7 @@ generate
cell->setPort(\Q, chain.back()->getPort(\D)); cell->setPort(\Q, chain.back()->getPort(\D));
if (cell->type == \FDRE) { if (cell->type == \FDRE) {
if (rng(2) == 0) if (rng(2) == 0)
cell->setPort(\R, chain.back()->connections_.at(\R, State::S0)); cell->setPort(\R, port(chain.back(), \R, State::S0));
cell->setPort(\CE, chain.back()->getPort(\CE)); cell->setPort(\CE, chain.back()->getPort(\CE));
} }
else if (cell->type.begins_with("$_DFFE_")) else if (cell->type.begins_with("$_DFFE_"))