mirror of https://github.com/YosysHQ/yosys.git
Prepare for situation when port of the signal cannot be found
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291b36afeb
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53695e6729
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@ -58,10 +58,14 @@ struct Netlist {
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return sigbit_driver_map.at(sig);
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return sigbit_driver_map.at(sig);
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}
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}
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RTLIL::SigBit& driver_port(RTLIL::SigBit sig)
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RTLIL::SigSpec driver_port(RTLIL::SigBit sig)
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{
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{
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RTLIL::Cell *cell = driver_cell(sig);
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RTLIL::Cell *cell = driver_cell(sig);
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if (!cell) {
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return RTLIL::SigSpec();
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}
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for (auto &port : cell->connections_) {
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for (auto &port : cell->connections_) {
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if (ct.cell_output(cell->type, port.first)) {
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if (ct.cell_output(cell->type, port.first)) {
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RTLIL::SigSpec port_sig = sigmap(port.second);
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RTLIL::SigSpec port_sig = sigmap(port.second);
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@ -72,6 +76,8 @@ struct Netlist {
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}
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}
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}
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}
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}
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}
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return RTLIL::SigSpec();
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}
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}
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void setup_netlist(RTLIL::Module *module, const CellTypes &ct)
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void setup_netlist(RTLIL::Module *module, const CellTypes &ct)
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@ -503,7 +503,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
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// If the register bit cannot change, we can replace it with a constant
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// If the register bit cannot change, we can replace it with a constant
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if (!counter_example_found) {
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if (!counter_example_found) {
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RTLIL::SigBit &driver_port = net.driver_port(q_sigbit);
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RTLIL::SigSpec driver_port = net.driver_port(q_sigbit);
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RTLIL::Wire *dummy_wire = mod->addWire(NEW_ID, 1);
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RTLIL::Wire *dummy_wire = mod->addWire(NEW_ID, 1);
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for (auto &conn : mod->connections_)
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for (auto &conn : mod->connections_)
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