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abc9_ops: -break_scc -> -mark_scc using (* keep *), remove -unbreak_scc

This commit is contained in:
Eddie Hung 2020-01-13 23:42:27 -08:00
parent b678b15c6d
commit 531fddf797
2 changed files with 20 additions and 46 deletions
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7
passes/techmap/abc9.cc
View File

@ -244,9 +244,9 @@ struct Abc9Pass : public ScriptPass
if (check_label("pre")) { if (check_label("pre")) {
run("scc -set_attr abc9_scc_id {}"); run("scc -set_attr abc9_scc_id {}");
if (help_mode) if (help_mode)
run("abc9_ops -break_scc -prep_holes [-dff]", "(option for -dff)"); run("abc9_ops -mark_scc -prep_holes [-dff]", "(option for -dff)");
else else
run("abc9_ops -break_scc -prep_holes" + std::string(dff_mode ? " -dff" : ""), "(option for -dff)"); run("abc9_ops -mark_scc -prep_holes" + std::string(dff_mode ? " -dff" : ""), "(option for -dff)");
run("select -set abc9_holes A:abc9_holes"); run("select -set abc9_holes A:abc9_holes");
run("flatten -wb @abc9_holes"); run("flatten -wb @abc9_holes");
run("techmap @abc9_holes"); run("techmap @abc9_holes");
@ -315,9 +315,6 @@ struct Abc9Pass : public ScriptPass
active_design->selection_stack.pop_back(); active_design->selection_stack.pop_back();
} }
} }
if (check_label("post"))
run("abc9_ops -unbreak_scc");
} }
} Abc9Pass; } Abc9Pass;

59
passes/techmap/abc9_ops.cc
View File

@ -33,7 +33,7 @@ inline std::string remap_name(RTLIL::IdString abc9_name)
return stringf("$abc$%d$%s", map_autoidx, abc9_name.c_str()+1); return stringf("$abc$%d$%s", map_autoidx, abc9_name.c_str()+1);
} }
void break_scc(RTLIL::Module *module) void mark_scc(RTLIL::Module *module)
{ {
// For every unique SCC found, (arbitrarily) find the first // For every unique SCC found, (arbitrarily) find the first
// cell in the component, and convert all wires driven by // cell in the component, and convert all wires driven by
@ -44,7 +44,8 @@ void break_scc(RTLIL::Module *module)
auto it = cell->attributes.find(ID(abc9_scc_id)); auto it = cell->attributes.find(ID(abc9_scc_id));
if (it == cell->attributes.end()) if (it == cell->attributes.end())
continue; continue;
auto r = ids_seen.insert(it->second); auto id = it->second;
auto r = ids_seen.insert(id);
cell->attributes.erase(it); cell->attributes.erase(it);
if (!r.second) if (!r.second)
continue; continue;
@ -54,6 +55,7 @@ void break_scc(RTLIL::Module *module)
SigBit b = c.second.as_bit(); SigBit b = c.second.as_bit();
Wire *w = b.wire; Wire *w = b.wire;
w->set_bool_attribute(ID::keep); w->set_bool_attribute(ID::keep);
w->attributes[ID(abc9_scc_id)] = id.as_int();
} }
} }
} }
@ -61,28 +63,6 @@ void break_scc(RTLIL::Module *module)
module->fixup_ports(); module->fixup_ports();
} }
void unbreak_scc(RTLIL::Module *module)
{
// Now 'unexpose' those wires by undoing
// the expose operation -- remove them from PO/PI
// and re-connecting them back together
for (auto wire : module->wires()) {
auto it = wire->attributes.find(ID(abc9_scc_break));
if (it != wire->attributes.end()) {
wire->attributes.erase(it);
log_assert(wire->port_output);
wire->port_output = false;
std::string name = wire->name.str();
RTLIL::Wire *i_wire = module->wire(name.substr(0, GetSize(name) - 5));
log_assert(i_wire);
log_assert(i_wire->port_input);
i_wire->port_input = false;
module->connect(i_wire, wire);
}
}
module->fixup_ports();
}
void prep_dff(RTLIL::Module *module) void prep_dff(RTLIL::Module *module)
{ {
auto design = module->design; auto design = module->design;
@ -676,21 +656,25 @@ void reintegrate(RTLIL::Module *module)
// Stitch in mapped_mod's inputs/outputs into module // Stitch in mapped_mod's inputs/outputs into module
for (auto port : mapped_mod->ports) { for (auto port : mapped_mod->ports) {
RTLIL::Wire *w = mapped_mod->wire(port); RTLIL::Wire *mapped_wire = mapped_mod->wire(port);
RTLIL::Wire *wire = module->wire(port); RTLIL::Wire *wire = module->wire(port);
log_assert(wire); log_assert(wire);
if (wire->attributes.erase(ID(abc9_scc_id))) {
auto r YS_ATTRIBUTE(unused) = wire->attributes.erase(ID::keep);
log_assert(r);
}
RTLIL::Wire *remap_wire = module->wire(remap_name(port)); RTLIL::Wire *remap_wire = module->wire(remap_name(port));
RTLIL::SigSpec signal(wire, 0, GetSize(remap_wire)); RTLIL::SigSpec signal(wire, 0, GetSize(remap_wire));
log_assert(GetSize(signal) >= GetSize(remap_wire)); log_assert(GetSize(signal) >= GetSize(remap_wire));
RTLIL::SigSig conn; RTLIL::SigSig conn;
if (w->port_output) { if (mapped_wire->port_output) {
conn.first = signal; conn.first = signal;
conn.second = remap_wire; conn.second = remap_wire;
out_wires++; out_wires++;
module->connect(conn); module->connect(conn);
} }
else if (w->port_input) { else if (mapped_wire->port_input) {
conn.first = remap_wire; conn.first = remap_wire;
conn.second = signal; conn.second = signal;
in_wires++; in_wires++;
@ -791,8 +775,7 @@ struct Abc9OpsPass : public Pass {
{ {
log_header(design, "Executing ABC9_OPS pass (helper functions for ABC9).\n"); log_header(design, "Executing ABC9_OPS pass (helper functions for ABC9).\n");
bool break_scc_mode = false; bool mark_scc_mode = false;
bool unbreak_scc_mode = false;
bool prep_dff_mode = false; bool prep_dff_mode = false;
bool prep_holes_mode = false; bool prep_holes_mode = false;
bool reintegrate_mode = false; bool reintegrate_mode = false;
@ -801,12 +784,8 @@ struct Abc9OpsPass : public Pass {
size_t argidx; size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) { for (argidx = 1; argidx < args.size(); argidx++) {
std::string arg = args[argidx]; std::string arg = args[argidx];
if (arg == "-break_scc") { if (arg == "-mark_scc") {
break_scc_mode = true; mark_scc_mode = true;
continue;
}
if (arg == "-unbreak_scc") {
unbreak_scc_mode = true;
continue; continue;
} }
if (arg == "-prep_dff") { if (arg == "-prep_dff") {
@ -829,8 +808,8 @@ struct Abc9OpsPass : public Pass {
} }
extra_args(args, argidx, design); extra_args(args, argidx, design);
if (!(break_scc_mode || unbreak_scc_mode || prep_dff_mode || reintegrate_mode)) if (!(mark_scc_mode || prep_dff_mode || reintegrate_mode))
log_cmd_error("At least one of -{,un}break_scc, -prep_{dff,holes}, -reintegrate must be specified.\n"); log_cmd_error("At least one of -mark_scc, -prep_{dff,holes}, -reintegrate must be specified.\n");
if (dff_mode && !prep_holes_mode) if (dff_mode && !prep_holes_mode)
log_cmd_error("'-dff' option is only relevant for -prep_holes.\n"); log_cmd_error("'-dff' option is only relevant for -prep_holes.\n");
@ -847,10 +826,8 @@ struct Abc9OpsPass : public Pass {
if (!design->selected_whole_module(mod)) if (!design->selected_whole_module(mod))
log_error("Can't handle partially selected module %s!\n", log_id(mod)); log_error("Can't handle partially selected module %s!\n", log_id(mod));
if (break_scc_mode) if (mark_scc_mode)
break_scc(mod); mark_scc(mod);
if (unbreak_scc_mode)
unbreak_scc(mod);
if (prep_dff_mode) if (prep_dff_mode)
prep_dff(mod); prep_dff(mod);
if (prep_holes_mode) if (prep_holes_mode)