mirror of https://github.com/YosysHQ/yosys.git
Add recover_names pass to recover names post-mapping
This commit is contained in:
gatecat
myrtle
parent
57c9eb70fe
commit
52c8c28d2c
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@ -84,6 +84,12 @@ template<> struct hash_ops<int64_t> : hash_int_ops
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return mkhash((unsigned int)(a), (unsigned int)(a >> 32));
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}
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};
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template<> struct hash_ops<uint32_t> : hash_int_ops
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{
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static inline unsigned int hash(uint32_t a) {
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return a;
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}
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};
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template<> struct hash_ops<std::string> {
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static inline bool cmp(const std::string &a, const std::string &b) {
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@ -16,6 +16,7 @@ OBJS += passes/sat/fmcombine.o
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OBJS += passes/sat/mutate.o
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OBJS += passes/sat/cutpoint.o
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OBJS += passes/sat/fminit.o
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OBJS += passes/sat/recover_names.o
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ifeq ($(DISABLE_SPAWN),0)
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OBJS += passes/sat/qbfsat.o
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endif
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@ -0,0 +1,730 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2021 gatecat <gatecat@ds0.me>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/consteval.h"
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#include "kernel/celltypes.h"
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#include "kernel/utils.h"
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#include "kernel/satgen.h"
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#include <algorithm>
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#include <queue>
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USING_YOSYS_NAMESPACE
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template<> struct hashlib::hash_ops<uint64_t> : hashlib::hash_int_ops
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{
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static inline unsigned int hash(uint64_t a) {
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return mkhash((unsigned int)(a), (unsigned int)(a >> 32));
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}
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};
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PRIVATE_NAMESPACE_BEGIN
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// xorshift128 params
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#define INIT_X 123456789
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#define INIT_Y 362436069
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#define INIT_Z 521288629
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#define INIT_W 88675123
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// Similar to a SigBit; but module-independent
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struct IdBit {
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IdBit() : name(), bit(0) {};
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IdBit(IdString name, int bit = 0) : name(name), bit(bit) {};
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bool operator==(const IdBit &other) const { return name == other.name && bit == other.bit; };
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bool operator!=(const IdBit &other) const { return name != other.name || bit != other.bit; };
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unsigned hash() const
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{
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return mkhash_add(name.hash(), bit);
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}
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IdString name;
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int bit;
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};
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// As above; but can be inverted
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struct InvBit {
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InvBit() : bit(), inverted(false) {};
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explicit InvBit(IdBit bit, bool inverted = false) : bit(bit), inverted(inverted) {};
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bool operator==(const InvBit &other) const { return bit == other.bit && inverted == other.inverted; };
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bool operator!=(const InvBit &other) const { return bit != other.bit || inverted != other.inverted; };
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unsigned hash() const
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{
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return mkhash(bit.hash(), inverted);
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}
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IdBit bit;
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bool inverted;
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};
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typedef uint64_t equiv_cls_t;
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static const int sim_length = sizeof(equiv_cls_t) * 8;
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struct RecoverModuleWorker {
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Design *design = nullptr;
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Module *mod, *flat = nullptr;
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RecoverModuleWorker(Module *mod) : design(mod->design), mod(mod) {};
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ConstEval *ce = nullptr;
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SigMap *sigmap = nullptr;
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dict<IdBit, SigBit> flat2orig;
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dict<IdBit, IdBit> bit2primary;
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dict<IdBit, Cell*> bit2driver;
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void prepare()
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{
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// Create a derivative of the module with whiteboxes flattened so we can
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// run eval and sat on it
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flat = design->addModule(NEW_ID);
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mod->cloneInto(flat);
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Pass::call_on_module(design, flat, "flatten -wb");
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ce = new ConstEval(flat);
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sigmap = new SigMap(flat);
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// Create a mapping from primary name-bit in the box-flattened module to original sigbit
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SigMap orig_sigmap(mod);
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for (auto wire : mod->wires()) {
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Wire *flat_wire = flat->wire(wire->name);
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if (!flat_wire)
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continue;
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for (int i = 0; i < wire->width; i++) {
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SigBit orig_sigbit = orig_sigmap(SigBit(wire, i));
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SigBit flat_sigbit = (*sigmap)(SigBit(flat_wire, i));
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if (!orig_sigbit.wire || !flat_sigbit.wire)
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continue;
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flat2orig[IdBit(flat_sigbit.wire->name, flat_sigbit.offset)] = orig_sigbit;
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}
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}
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find_driven_bits();
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}
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void find_driven_bits()
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{
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// Add primary inputs
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for (auto wire : flat->wires()) {
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if (!wire->port_input)
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continue;
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for (int i = 0; i < wire->width; i++) {
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SigBit bit(wire, i);
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bit = (*sigmap)(bit);
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if (bit.wire)
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bit2driver[IdBit(bit.wire->name, bit.offset)] = nullptr;
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}
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}
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// Add cell outputs
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for (auto cell : flat->cells()) {
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for (auto conn : cell->connections()) {
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if (!cell->output(conn.first))
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continue;
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for (auto bit : conn.second) {
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auto resolved = (*sigmap)(bit);
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if (resolved.wire)
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bit2driver[IdBit(resolved.wire->name, resolved.offset)] = cell;
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}
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}
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}
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// Setup bit2primary
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for (auto wire : flat->wires()) {
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for (int i = 0; i < wire->width; i++) {
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SigBit bit(wire, i);
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bit = (*sigmap)(bit);
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if (bit.wire)
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bit2primary[IdBit(wire->name, i)] = IdBit(bit.wire->name, bit.offset);
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}
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}
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}
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// Mapping from bit to (candidate) equivalence classes
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dict<IdBit, equiv_cls_t> bit2cls;
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void sim_cycle(int t, const dict<IdBit, RTLIL::State> &anchors)
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{
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ce->clear();
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for (auto anchor : anchors) {
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SigBit bit = (*sigmap)(SigBit(flat->wire(anchor.first.name), anchor.first.bit));
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// Ignore in the rare case that it's already determined
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SigSpec res(bit);
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if (ce->eval(res))
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continue;
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ce->set(bit, anchor.second);
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}
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// Only evaluate IdBits that exist in the non-flat design; as they are all we care about
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for (auto idbit : flat2orig) {
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if (anchors.count(idbit.first))
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continue;
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SigBit bit = (*sigmap)(SigBit(flat->wire(idbit.first.name), idbit.first.bit));
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SigSpec res(bit);
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if (!ce->eval(res))
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continue;
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if (res != State::S0 && res != State::S1)
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continue;
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// Update equivalence classes
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if (res == State::S1)
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bit2cls[idbit.first] = bit2cls[idbit.first] | (equiv_cls_t(1) << t);
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}
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}
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// Update the equivalence class groupings
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void group_classes(dict<equiv_cls_t, std::pair<pool<IdBit>, pool<InvBit>>> &cls2bits, bool is_gate)
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{
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equiv_cls_t all_ones = 0;
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for (int i = 0; i < sim_length; i++) all_ones |= (equiv_cls_t(1) << i);
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for (auto pair : bit2cls) {
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if (pair.second == 0 || pair.second == all_ones)
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continue; // skip stuck-ats
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if (is_gate) {
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// True doesn't exist in gold; but inverted does
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if (!cls2bits.count(pair.second) && cls2bits.count(pair.second ^ all_ones))
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cls2bits[pair.second ^ all_ones].second.emplace(pair.first, true);
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else
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cls2bits[pair.second].second.emplace(pair.first, false);
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} else {
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cls2bits[pair.second].first.insert(pair.first);
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}
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}
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}
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// Compute depths of IdBits
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dict<IdBit, int> bit2depth;
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void compute_depths(const dict<IdBit, IdBit> &anchor_bits)
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{
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dict<SigBit, pool<IdString>> bit_drivers, bit_users;
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TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
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for (auto cell : flat->cells())
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for (auto conn : cell->connections())
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{
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for (auto bit : (*sigmap)(conn.second)) {
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if (!bit.wire)
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continue;
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IdBit idbit(bit.wire->name, bit.offset);
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if (anchor_bits.count(idbit))
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continue;
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if (cell->input(conn.first))
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bit_users[bit].insert(cell->name);
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if (cell->output(conn.first))
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bit_drivers[bit].insert(cell->name);
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}
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toposort.node(cell->name);
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}
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for (auto &it : bit_users)
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if (bit_drivers.count(it.first))
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for (auto driver_cell : bit_drivers.at(it.first))
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for (auto user_cell : it.second)
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toposort.edge(driver_cell, user_cell);
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toposort.sort();
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for (auto cell_name : toposort.sorted) {
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Cell *cell = flat->cell(cell_name);
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int cell_depth = 0;
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for (auto conn : cell->connections()) {
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if (!cell->input(conn.first))
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continue;
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for (auto bit : (*sigmap)(conn.second)) {
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if (!bit.wire)
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continue;
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IdBit idbit(bit.wire->name, bit.offset);
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if (!bit2depth.count(idbit))
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continue;
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cell_depth = std::max(cell_depth, bit2depth.at(idbit));
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}
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}
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for (auto conn : cell->connections()) {
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if (!cell->output(conn.first))
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continue;
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for (auto bit : (*sigmap)(conn.second)) {
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if (!bit.wire)
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continue;
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IdBit idbit(bit.wire->name, bit.offset);
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bit2depth[idbit] = std::max(bit2depth[idbit], cell_depth + 1);
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}
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}
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}
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}
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// SAT thresholds
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const int max_sat_cells = 50;
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SigBit id2bit(IdBit bit) { return SigBit(flat->wire(bit.name), bit.bit); }
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// Set up the SAT problem for an IdBit
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// the value side of 'anchors' will be populated with the SAT variable for anchor bits
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int setup_sat(SatGen *sat, const std::string &prefix, IdBit bit, const dict<IdBit, IdBit> &anchor_bits, dict<IdBit, int> &anchor2var)
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{
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sat->setContext(sigmap, prefix);
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pool<IdString> imported_cells;
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int result = sat->importSigBit(id2bit(bit));
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// Recursively import driving cells
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std::queue<IdBit> to_import;
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to_import.push(bit);
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while (!to_import.empty()) {
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// Too many cells imported
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if (GetSize(imported_cells) > max_sat_cells)
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return -1;
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IdBit cursor = to_import.front();
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to_import.pop();
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if (anchor_bits.count(cursor)) {
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if (!anchor2var.count(cursor)) {
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anchor2var[cursor] = sat->importSigBit(id2bit(cursor));
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}
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continue;
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}
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// Import driver if it exists
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if (!bit2driver.count(cursor))
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continue;
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Cell *driver = bit2driver.at(cursor);
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if (!driver || imported_cells.count(driver->name))
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continue;
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if (!sat->importCell(driver))
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return -1; // cell can't be imported
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imported_cells.insert(driver->name);
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// Add cell inputs to queue
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for (auto conn : driver->connections()) {
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if (!driver->input(conn.first))
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continue;
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for (SigBit in_bit : (*sigmap)(conn.second)) {
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if (!in_bit.wire)
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continue;
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IdBit in_idbit(in_bit.wire->name, in_bit.offset);
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to_import.push(in_idbit);
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}
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}
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}
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return result;
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}
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void find_buffers(const pool<IdString> &buffer_types, dict<SigBit, pool<SigBit>> &root2buffered)
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{
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SigMap orig_sigmap(mod);
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dict<SigBit, SigBit> buffer2root;
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for (auto cell : mod->cells()) {
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if (!buffer_types.count(cell->type))
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continue;
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SigBit in, out;
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for (auto conn : cell->connections()) {
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if (cell->input(conn.first)) {
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in = orig_sigmap(conn.second[0]);
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}
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if (cell->output(conn.first)) {
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out = orig_sigmap(conn.second[0]);
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}
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}
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if (!in.wire || !out.wire)
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continue;
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SigBit root = in;
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if (buffer2root.count(root))
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root = buffer2root[root];
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if (root2buffered.count(out)) {
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for (auto out_sig : root2buffered.at(out))
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root2buffered[root].insert(out_sig);
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root2buffered.erase(out);
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}
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root2buffered[root].insert(out);
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buffer2root[out] = root;
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}
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}
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void do_rename(Module *gold, const dict<IdBit, InvBit> &gate2gold, const pool<IdString> &buffer_types)
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{
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dict<SigBit, std::vector<std::tuple<Cell*, IdString, int>>> bit2port;
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pool<SigBit> unused_bits;
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SigMap orig_sigmap(mod);
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for (auto wire : mod->wires()) {
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if (wire->port_input || wire->port_output)
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continue;
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for (int i = 0; i < wire->width; i++)
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unused_bits.insert(orig_sigmap(SigBit(wire, i)));
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}
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for (auto cell : mod->cells()) {
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for (auto conn : cell->connections()) {
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for (int i = 0; i < GetSize(conn.second); i++) {
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SigBit bit = orig_sigmap(conn.second[i]);
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if (!bit.wire)
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continue;
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bit2port[bit].emplace_back(cell, conn.first, i);
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unused_bits.erase(bit);
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}
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}
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}
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dict<SigBit, pool<SigBit>> root2buffered;
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find_buffers(buffer_types, root2buffered);
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// An extension of gate2gold that deals with buffers too
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// gate sigbit --> (new name, invert, gold wire)
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dict<SigBit, std::pair<InvBit, Wire*>> rename_map;
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for (auto pair : gate2gold) {
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SigBit gate_bit = flat2orig.at(pair.first);
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Wire *gold_wire = gold->wire(pair.second.bit.name);
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rename_map[gate_bit] = std::make_pair(pair.second, gold_wire);
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if (root2buffered.count(gate_bit)) {
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int buf_idx = 0;
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for (auto buf_bit : root2buffered.at(gate_bit)) {
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std::string buf_name_str = stringf("%s_buf_%d", pair.second.bit.name.c_str(), ++buf_idx);
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if (buf_name_str[0] == '\\')
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buf_name_str[0] = '$';
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rename_map[buf_bit] = std::make_pair(
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InvBit(IdBit(IdString(buf_name_str), pair.second.bit.bit), pair.second.inverted), gold_wire);
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}
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}
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}
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for (auto rule : rename_map) {
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// Pick a uniq new name
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IdBit new_name = rule.second.first.bit;
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int dup_idx = 0;
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bool must_invert_name = rule.second.first.inverted;
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while (must_invert_name ||
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(mod->wire(new_name.name) && !unused_bits.count(SigBit(mod->wire(new_name.name), new_name.bit)))) {
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std::string new_name_str = stringf("%s_%s_%d", rule.second.first.bit.name.c_str(),
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rule.second.first.inverted ? "inv" : "dup", ++dup_idx);
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if (new_name_str[0] == '\\')
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new_name_str[0] = '$';
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new_name.name = IdString(new_name_str);
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must_invert_name = false;
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}
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// Create the wire if needed
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Wire *new_wire = mod->wire(new_name.name);
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if (!new_wire) {
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Wire *gold_wire = rule.second.second;
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new_wire = mod->addWire(new_name.name, gold_wire->width);
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new_wire->start_offset = gold_wire->start_offset;
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new_wire->upto = gold_wire->upto;
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for (const auto &attr : gold_wire->attributes)
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new_wire->attributes[attr.first] = attr.second;
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for (int i = 0; i < new_wire->width; i++)
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unused_bits.insert(SigBit(new_wire, i));
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}
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// Ensure it's wide enough
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if (new_wire->width <= new_name.bit)
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new_wire->width = new_name.bit + 1;
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SigBit old_bit = rule.first;
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||||
SigBit new_bit(new_wire, new_name.bit);
|
||||
unused_bits.erase(new_bit);
|
||||
// Replace all users
|
||||
if (bit2port.count(old_bit))
|
||||
for (auto port_ref : bit2port.at(old_bit)) {
|
||||
Cell *cell = std::get<0>(port_ref);
|
||||
IdString port_name = std::get<1>(port_ref);
|
||||
int port_bit = std::get<2>(port_ref);
|
||||
SigSpec port_sig = cell->getPort(port_name);
|
||||
port_sig.replace(port_bit, new_bit);
|
||||
cell->unsetPort(port_name);
|
||||
cell->setPort(port_name, port_sig);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
~RecoverModuleWorker()
|
||||
{
|
||||
delete ce;
|
||||
delete sigmap;
|
||||
if (flat)
|
||||
design->remove(flat);
|
||||
}
|
||||
};
|
||||
|
||||
struct RecoverNamesWorker {
|
||||
Design *design, *gold_design = nullptr;
|
||||
CellTypes ct_all;
|
||||
RecoverNamesWorker(Design *design) : design(design) {}
|
||||
|
||||
pool<IdString> comb_whiteboxes, buffer_types;
|
||||
|
||||
// class -> (gold, (gate, inverted))
|
||||
dict<equiv_cls_t, std::pair<pool<IdBit>, dict<IdBit, bool>>> cls2bits;
|
||||
|
||||
void analyse_boxes()
|
||||
{
|
||||
for (auto mod : design->modules()) {
|
||||
if (!mod->get_bool_attribute(ID::whitebox))
|
||||
continue;
|
||||
bool is_comb = true;
|
||||
for (auto cell : mod->cells()) {
|
||||
if (ct_all.cell_evaluable(cell->type)) {
|
||||
is_comb = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (!is_comb)
|
||||
continue;
|
||||
comb_whiteboxes.insert(mod->name);
|
||||
// Buffers have one input and one output; exactly
|
||||
SigBit in{}, out{};
|
||||
ConstEval eval(mod);
|
||||
for (auto wire : mod->wires()) {
|
||||
if (wire->port_input) {
|
||||
if (wire->width != 1 || in.wire)
|
||||
goto not_buffer;
|
||||
in = SigBit(wire, 0);
|
||||
}
|
||||
if (wire->port_output) {
|
||||
if (wire->width != 1 || out.wire)
|
||||
goto not_buffer;
|
||||
out = SigBit(wire, 0);
|
||||
}
|
||||
}
|
||||
if (!in.wire || !out.wire)
|
||||
goto not_buffer;
|
||||
// Buffer input mirrors output
|
||||
for (auto bit : {State::S0, State::S1}) {
|
||||
eval.clear();
|
||||
eval.set(in, bit);
|
||||
SigSpec result(out);
|
||||
if (!eval.eval(result))
|
||||
goto not_buffer;
|
||||
if (result != bit)
|
||||
goto not_buffer;
|
||||
}
|
||||
buffer_types.insert(mod->name);
|
||||
if (false) {
|
||||
not_buffer:
|
||||
continue;
|
||||
}
|
||||
}
|
||||
log_debug("Found %d combinational cells and %d buffer whiteboxes.\n", GetSize(comb_whiteboxes), GetSize(buffer_types));
|
||||
}
|
||||
|
||||
uint32_t x, y, z, w, rng_val;
|
||||
int rng_bit;
|
||||
void rng_init()
|
||||
{
|
||||
x = INIT_X;
|
||||
y = INIT_Y;
|
||||
z = INIT_Z;
|
||||
w = INIT_W;
|
||||
rng_bit = 32;
|
||||
}
|
||||
uint32_t xorshift128()
|
||||
{
|
||||
uint32_t t = x ^ (x << 11);
|
||||
x = y; y = z; z = w;
|
||||
w ^= (w >> 19) ^ t ^ (t >> 8);
|
||||
return w;
|
||||
}
|
||||
RTLIL::State next_randbit()
|
||||
{
|
||||
if (rng_bit >= 32) {
|
||||
rng_bit = 0;
|
||||
rng_val = xorshift128();
|
||||
}
|
||||
return ((rng_val >> (rng_bit++)) & 0x1) ? RTLIL::State::S1 : RTLIL::State::S0;
|
||||
}
|
||||
|
||||
int popcount(equiv_cls_t cls) {
|
||||
int result = 0;
|
||||
for (unsigned i = 0; i < 8*sizeof(equiv_cls_t); i++)
|
||||
if ((cls >> i) & 0x1)
|
||||
++result;
|
||||
return result;
|
||||
}
|
||||
|
||||
bool prove_equiv(RecoverModuleWorker &gold_worker, RecoverModuleWorker &gate_worker,
|
||||
const dict<IdBit, IdBit> &gold_anchors, const dict<IdBit, IdBit> &gate_anchors,
|
||||
IdBit gold_bit, IdBit gate_bit, bool invert) {
|
||||
ezSatPtr ez;
|
||||
SatGen satgen(ez.get(), nullptr);
|
||||
dict<IdBit, int> anchor2var_gold, anchor2var_gate;
|
||||
int gold_var = gold_worker.setup_sat(&satgen, "gold", gold_bit, gold_anchors, anchor2var_gold);
|
||||
if (gold_var == -1)
|
||||
return false;
|
||||
int gate_var = gate_worker.setup_sat(&satgen, "gate", gate_bit, gate_anchors, anchor2var_gate);
|
||||
if (gate_var == -1)
|
||||
return false;
|
||||
// Assume anchors are equal
|
||||
for (auto anchor : anchor2var_gate) {
|
||||
IdBit gold_anchor = gate_anchors.at(anchor.first);
|
||||
if (!anchor2var_gold.count(gold_anchor))
|
||||
continue;
|
||||
ez->assume(ez->IFF(anchor.second, anchor2var_gold.at(gold_anchor)));
|
||||
}
|
||||
// Prove equivalence
|
||||
return !ez->solve(ez->NOT(ez->IFF(gold_var, invert ? ez->NOT(gate_var) : gate_var)));
|
||||
}
|
||||
|
||||
void analyse_mod(Module *gate_mod)
|
||||
{
|
||||
Module *gold_mod = gold_design->module(gate_mod->name);
|
||||
if (!gold_mod)
|
||||
return;
|
||||
|
||||
RecoverModuleWorker gold_worker(gold_mod);
|
||||
RecoverModuleWorker gate_worker(gate_mod);
|
||||
|
||||
gold_worker.prepare();
|
||||
gate_worker.prepare();
|
||||
|
||||
// Find anchors (same-name wire-bits driven in both gold and gate)
|
||||
dict<IdBit, IdBit> gold_anchors, gate_anchors;
|
||||
|
||||
for (auto gold_bit : gold_worker.bit2driver) {
|
||||
if (gate_worker.bit2primary.count(gold_bit.first)) {
|
||||
IdBit gate_bit = gate_worker.bit2primary.at(gold_bit.first);
|
||||
if (!gate_worker.bit2driver.count(gate_bit))
|
||||
continue;
|
||||
gold_anchors[gold_bit.first] = gate_bit;
|
||||
gate_anchors[gate_bit] = gold_bit.first;
|
||||
}
|
||||
}
|
||||
// Run a random-value combinational simulation to find candidate equivalence classes
|
||||
dict<IdBit, RTLIL::State> gold_anchor_vals, gate_anchor_vals;
|
||||
rng_init();
|
||||
for (int t = 0; t < sim_length; t++) {
|
||||
for (auto anchor : gold_anchors) {
|
||||
gold_anchor_vals[anchor.first] = next_randbit();
|
||||
gate_anchor_vals[anchor.second] = gold_anchor_vals[anchor.first];
|
||||
}
|
||||
gold_worker.sim_cycle(t, gold_anchor_vals);
|
||||
gate_worker.sim_cycle(t, gate_anchor_vals);
|
||||
}
|
||||
log_debug("%d candidate equiv classes in gold; %d in gate\n", GetSize(gold_worker.bit2cls), GetSize(gate_worker.bit2cls));
|
||||
// Group bits by equivalence classes together
|
||||
dict<equiv_cls_t, std::pair<pool<IdBit>, pool<InvBit>>> cls2bits;
|
||||
gold_worker.group_classes(cls2bits, false);
|
||||
gate_worker.group_classes(cls2bits, true);
|
||||
gate_worker.compute_depths(gate_anchors);
|
||||
// Sort equivalence classes by shallowest first (so we have as many anchors as possible when reaching deeper bits)
|
||||
std::vector<std::pair<equiv_cls_t, int>> cls_depth;
|
||||
for (auto &cls : cls2bits) {
|
||||
if (cls.second.second.empty())
|
||||
continue;
|
||||
int depth = 0;
|
||||
for (auto gate_bit : cls.second.second) {
|
||||
if (!gate_worker.bit2depth.count(gate_bit.bit))
|
||||
continue;
|
||||
depth = std::max(depth, gate_worker.bit2depth.at(gate_bit.bit));
|
||||
}
|
||||
cls_depth.emplace_back(cls.first, depth);
|
||||
}
|
||||
std::stable_sort(cls_depth.begin(), cls_depth.end(),
|
||||
[](const std::pair<equiv_cls_t, int> &a, const std::pair<equiv_cls_t, int> &b) {
|
||||
return a.second < b.second;
|
||||
});
|
||||
// The magic result we've worked hard for....
|
||||
dict<IdBit, InvBit> gate2gold;
|
||||
// Solve starting from shallowest
|
||||
for (auto cls : cls_depth) {
|
||||
int pop = popcount(cls.first);
|
||||
// Equivalence classes with only one set bit are invariably a waste of SAT time
|
||||
if (pop == 1 || pop == (8*sizeof(equiv_cls_t) - 1))
|
||||
continue;
|
||||
|
||||
log_debug("equivalence class: %016lx\n", cls.first);
|
||||
const pool<IdBit> &gold_bits = cls2bits.at(cls.first).first;
|
||||
const pool<InvBit> &gate_bits = cls2bits.at(cls.first).second;
|
||||
if (gold_bits.empty() || gate_bits.empty())
|
||||
continue;
|
||||
pool<IdBit> solved_gate;
|
||||
if (GetSize(gold_bits) > 10)
|
||||
continue; // large equivalence classes are not very interesting; skip
|
||||
for (IdBit gold_bit : gold_bits) {
|
||||
for (auto gate_bit : gate_bits) {
|
||||
if (solved_gate.count(gate_bit.bit))
|
||||
continue;
|
||||
log_debug(" attempting to prove %s[%d] == %s%s[%d]\n", log_id(gold_bit.name), gold_bit.bit,
|
||||
gate_bit.inverted ? "" : "!", log_id(gate_bit.bit.name), gate_bit.bit.bit);
|
||||
if (!prove_equiv(gold_worker, gate_worker, gold_anchors, gate_anchors, gold_bit, gate_bit.bit, gate_bit.inverted))
|
||||
continue;
|
||||
log_debug(" success!\n");
|
||||
// Success!
|
||||
gate2gold[gate_bit.bit] = InvBit(gold_bit, gate_bit.inverted);
|
||||
if (!gate_bit.inverted) {
|
||||
// Only add as anchor if not inverted
|
||||
gold_anchors[gold_bit] = gate_bit.bit;
|
||||
gate_anchors[gate_bit.bit] = gold_bit;
|
||||
}
|
||||
solved_gate.insert(gate_bit.bit);
|
||||
}
|
||||
// All solved...
|
||||
if (GetSize(solved_gate) == GetSize(gate_bits))
|
||||
break;
|
||||
}
|
||||
}
|
||||
log("Recovered %d net name pairs in module `%s' out.\n", GetSize(gate2gold), log_id(gate_mod));
|
||||
gate_worker.do_rename(gold_mod, gate2gold, buffer_types);
|
||||
}
|
||||
|
||||
void operator()(string command)
|
||||
{
|
||||
// Make a backup copy of the pre-mapping design for later
|
||||
gold_design = new RTLIL::Design;
|
||||
|
||||
for (auto mod : design->modules())
|
||||
gold_design->add(mod->clone());
|
||||
|
||||
run_pass(command, design);
|
||||
|
||||
analyse_boxes();
|
||||
|
||||
// keeping our own std::vector here avoids modify-while-iterating issues
|
||||
std::vector<Module *> to_analyse;
|
||||
for (auto mod : design->modules())
|
||||
if (!mod->get_blackbox_attribute())
|
||||
to_analyse.push_back(mod);
|
||||
for (auto mod : to_analyse)
|
||||
analyse_mod(mod);
|
||||
}
|
||||
~RecoverNamesWorker() {
|
||||
delete gold_design;
|
||||
}
|
||||
};
|
||||
|
||||
struct RecoverNamesPass : public Pass {
|
||||
RecoverNamesPass() : Pass("recover_names", "Execute a lossy mapping command and recover original netnames") { }
|
||||
void help() override
|
||||
{
|
||||
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
||||
log("\n");
|
||||
log(" recover_names [command]\n");
|
||||
log("\n");
|
||||
log("This pass executes a lossy mapping command and uses a combination of simulation\n");
|
||||
log(" to find candidate equivalences and SAT to recover exact original net names.\n");
|
||||
log("\n");
|
||||
}
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) override
|
||||
{
|
||||
log_header(design, "Executing RECOVER_NAMES pass (run mapping and recover original names).\n");
|
||||
string command;
|
||||
|
||||
size_t argidx = 1;
|
||||
for (; argidx < args.size(); argidx++) {
|
||||
if (command.empty()) {
|
||||
if (args[argidx].compare(0, 1, "-") == 0)
|
||||
cmd_error(args, argidx, "Unknown option.");
|
||||
} else {
|
||||
command += " ";
|
||||
}
|
||||
command += args[argidx];
|
||||
}
|
||||
|
||||
if (command.empty())
|
||||
log_cmd_error("No mapping pass specified!\n");
|
||||
|
||||
RecoverNamesWorker worker(design);
|
||||
worker(command);
|
||||
|
||||
}
|
||||
} RecoverNamesPass;
|
||||
|
||||
PRIVATE_NAMESPACE_END
|
||||
Loading…
Reference in New Issue