From 3a5a65829cc593965304537ddcb4d6d1d3e3ca8b Mon Sep 17 00:00:00 2001 From: Diego H Date: Tue, 26 Nov 2019 17:14:41 -0600 Subject: [PATCH 1/5] Adjusting Vivado's BRAM min bits threshold for RAMB18E1 --- techlibs/xilinx/xc7_xcu_brams.txt | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/techlibs/xilinx/xc7_xcu_brams.txt b/techlibs/xilinx/xc7_xcu_brams.txt index f1161114e..ee961fff8 100644 --- a/techlibs/xilinx/xc7_xcu_brams.txt +++ b/techlibs/xilinx/xc7_xcu_brams.txt @@ -81,7 +81,7 @@ match $__XILINX_RAMB36_SDP endmatch match $__XILINX_RAMB18_SDP - min bits 4096 + min bits 1024 min efficiency 5 shuffle_enable B make_transp @@ -97,9 +97,12 @@ match $__XILINX_RAMB36_TDP endmatch match $__XILINX_RAMB18_TDP - min bits 4096 + min bits 1024 min efficiency 5 shuffle_enable B make_transp endmatch +# [[CITE]] 7 Series FPGAs Memory Resources User Guide (UG473), +# v1.14 ed., p 29-30, July, 2019. + From 937ec1ee78e5470c148d8c39387c7a80711af8a7 Mon Sep 17 00:00:00 2001 From: Diego H Date: Thu, 12 Dec 2019 13:50:36 -0600 Subject: [PATCH 2/5] Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1 --- techlibs/xilinx/xc7_xcu_brams.txt | 4 +-- tests/arch/common/memory_params.v | 45 ++++++++++++++++++++++++++++++ tests/arch/xilinx/memory_params.ys | 45 ++++++++++++++++++++++++++++++ 3 files changed, 92 insertions(+), 2 deletions(-) create mode 100644 tests/arch/common/memory_params.v create mode 100644 tests/arch/xilinx/memory_params.ys diff --git a/techlibs/xilinx/xc7_xcu_brams.txt b/techlibs/xilinx/xc7_xcu_brams.txt index ee961fff8..87e659bbc 100644 --- a/techlibs/xilinx/xc7_xcu_brams.txt +++ b/techlibs/xilinx/xc7_xcu_brams.txt @@ -73,7 +73,7 @@ bram $__XILINX_RAMB18_TDP endbram match $__XILINX_RAMB36_SDP - min bits 4096 + min bits 1024 min efficiency 5 shuffle_enable B make_transp @@ -89,7 +89,7 @@ match $__XILINX_RAMB18_SDP endmatch match $__XILINX_RAMB36_TDP - min bits 4096 + min bits 1024 min efficiency 5 shuffle_enable B make_transp diff --git a/tests/arch/common/memory_params.v b/tests/arch/common/memory_params.v new file mode 100644 index 000000000..dbc6ca65c --- /dev/null +++ b/tests/arch/common/memory_params.v @@ -0,0 +1,45 @@ +`default_nettype none +module sync_ram_sp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) + (input wire write_enable, clk, + input wire [DATA_WIDTH-1:0] data_in, + input wire [ADDRESS_WIDTH-1:0] address_in, + output wire [DATA_WIDTH-1:0] data_out); + + localparam WORD = (DATA_WIDTH-1); + localparam DEPTH = (2**ADDRESS_WIDTH-1); + + reg [WORD:0] data_out_r; + reg [WORD:0] memory [0:DEPTH]; + + always @(posedge clk) begin + if (write_enable) + memory[address_in] <= data_in; + data_out_r <= memory[address_in]; + end + + assign data_out = data_out_r; +endmodule // sync_ram_sp + + +`default_nettype none +module sync_ram_sdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) + (input wire clk, write_enable, + input wire [DATA_WIDTH-1:0] data_in, + input wire [ADDRESS_WIDTH-1:0] address_in_r, address_in_w, + output wire [DATA_WIDTH-1:0] data_out); + + localparam WORD = (DATA_WIDTH-1); + localparam DEPTH = (2**ADDRESS_WIDTH-1); + + reg [WORD:0] data_out_r; + reg [WORD:0] memory [0:DEPTH]; + + always @(posedge clk) begin + if (write_enable) + memory[address_in_w] <= data_in; + data_out_r <= memory[address_in_r]; + end + + assign data_out = data_out_r; +endmodule // sync_ram_sdp + diff --git a/tests/arch/xilinx/memory_params.ys b/tests/arch/xilinx/memory_params.ys new file mode 100644 index 000000000..f279a4a6e --- /dev/null +++ b/tests/arch/xilinx/memory_params.ys @@ -0,0 +1,45 @@ +# Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1 +read_verilog ../common/memory_params.v +chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/memory_params.v +chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/memory_params.v +chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/memory_params.v +chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +# Anything memory bits < 1024 -> LUTRAM +design -reset +read_verilog ../common/memory_params.v +chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 0 t:RAMB18E1 +select -assert-count 4 t:RAM128X1D + +# More than 18K bits and addr <= 36: -> RAMB36E1 +design -reset +read_verilog ../common/memory_params.v +chparam -set ADDRESS_WIDTH 15 -set DATA_WIDTH 1 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB36E1 + From e33f407655fa516cb2f6754103973eb156ca90cf Mon Sep 17 00:00:00 2001 From: Diego H Date: Thu, 12 Dec 2019 16:06:46 -0600 Subject: [PATCH 3/5] Adding a note (TODO) in the memory_params.ys check file --- tests/arch/xilinx/memory_params.ys | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/arch/xilinx/memory_params.ys b/tests/arch/xilinx/memory_params.ys index f279a4a6e..657629e0f 100644 --- a/tests/arch/xilinx/memory_params.ys +++ b/tests/arch/xilinx/memory_params.ys @@ -1,3 +1,5 @@ +## TODO: Not running equivalence checking because BRAM models does not exists +## currently. Checking instance counts instead. # Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1 read_verilog ../common/memory_params.v chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp From 751a18d7e974123352e372c75bb17226e6fabec0 Mon Sep 17 00:00:00 2001 From: Diego H Date: Thu, 12 Dec 2019 17:32:58 -0600 Subject: [PATCH 4/5] Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test. --- techlibs/xilinx/xc7_xcu_brams.txt | 10 +++++----- tests/arch/xilinx/memory_params.ys | 4 ++-- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/techlibs/xilinx/xc7_xcu_brams.txt b/techlibs/xilinx/xc7_xcu_brams.txt index 87e659bbc..b7c893ff7 100644 --- a/techlibs/xilinx/xc7_xcu_brams.txt +++ b/techlibs/xilinx/xc7_xcu_brams.txt @@ -1,4 +1,3 @@ - bram $__XILINX_RAMB36_SDP init 1 abits 9 @@ -72,6 +71,11 @@ bram $__XILINX_RAMB18_TDP clkpol 2 3 endbram +# The "min bits" value were taken from: +# [[CITE]] 7 Series FPGAs Memory Resources User Guide (UG473), +# v1.14 ed., p 29-30, July, 2019. +# https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf + match $__XILINX_RAMB36_SDP min bits 1024 min efficiency 5 @@ -102,7 +106,3 @@ match $__XILINX_RAMB18_TDP shuffle_enable B make_transp endmatch - -# [[CITE]] 7 Series FPGAs Memory Resources User Guide (UG473), -# v1.14 ed., p 29-30, July, 2019. - diff --git a/tests/arch/xilinx/memory_params.ys b/tests/arch/xilinx/memory_params.ys index 657629e0f..c1b0ca489 100644 --- a/tests/arch/xilinx/memory_params.ys +++ b/tests/arch/xilinx/memory_params.ys @@ -37,10 +37,10 @@ cd sync_ram_sdp select -assert-count 0 t:RAMB18E1 select -assert-count 4 t:RAM128X1D -# More than 18K bits and addr <= 36: -> RAMB36E1 +# More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1 design -reset read_verilog ../common/memory_params.v -chparam -set ADDRESS_WIDTH 15 -set DATA_WIDTH 1 sync_ram_sdp +chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp synth_xilinx -top sync_ram_sdp cd sync_ram_sdp select -assert-count 1 t:RAMB36E1 From 1c9634558747bf5b92a309b6af013a54034c35d3 Mon Sep 17 00:00:00 2001 From: Diego H Date: Fri, 13 Dec 2019 09:33:18 -0600 Subject: [PATCH 5/5] Renaming BRAM memory tests for the sake of uniformity --- .../common/{memory_params.v => blockram_params.v} | 0 .../xilinx/{memory_params.ys => blockram_params.ys} | 12 ++++++------ 2 files changed, 6 insertions(+), 6 deletions(-) rename tests/arch/common/{memory_params.v => blockram_params.v} (100%) rename tests/arch/xilinx/{memory_params.ys => blockram_params.ys} (84%) diff --git a/tests/arch/common/memory_params.v b/tests/arch/common/blockram_params.v similarity index 100% rename from tests/arch/common/memory_params.v rename to tests/arch/common/blockram_params.v diff --git a/tests/arch/xilinx/memory_params.ys b/tests/arch/xilinx/blockram_params.ys similarity index 84% rename from tests/arch/xilinx/memory_params.ys rename to tests/arch/xilinx/blockram_params.ys index c1b0ca489..27a94834e 100644 --- a/tests/arch/xilinx/memory_params.ys +++ b/tests/arch/xilinx/blockram_params.ys @@ -1,28 +1,28 @@ ## TODO: Not running equivalence checking because BRAM models does not exists ## currently. Checking instance counts instead. # Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1 -read_verilog ../common/memory_params.v +read_verilog ../common/blockram_params.v chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp synth_xilinx -top sync_ram_sdp cd sync_ram_sdp select -assert-count 1 t:RAMB18E1 design -reset -read_verilog ../common/memory_params.v +read_verilog ../common/blockram_params.v chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp synth_xilinx -top sync_ram_sdp cd sync_ram_sdp select -assert-count 1 t:RAMB18E1 design -reset -read_verilog ../common/memory_params.v +read_verilog ../common/blockram_params.v chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp synth_xilinx -top sync_ram_sdp cd sync_ram_sdp select -assert-count 1 t:RAMB18E1 design -reset -read_verilog ../common/memory_params.v +read_verilog ../common/blockram_params.v chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp synth_xilinx -top sync_ram_sdp cd sync_ram_sdp @@ -30,7 +30,7 @@ select -assert-count 1 t:RAMB18E1 # Anything memory bits < 1024 -> LUTRAM design -reset -read_verilog ../common/memory_params.v +read_verilog ../common/blockram_params.v chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp synth_xilinx -top sync_ram_sdp cd sync_ram_sdp @@ -39,7 +39,7 @@ select -assert-count 4 t:RAM128X1D # More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1 design -reset -read_verilog ../common/memory_params.v +read_verilog ../common/blockram_params.v chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp synth_xilinx -top sync_ram_sdp cd sync_ram_sdp