mirror of https://github.com/YosysHQ/yosys.git
Also fix write_aiger for UB
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36e2eb06bb
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524af21317
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@ -70,35 +70,35 @@ struct AigerWriter
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int bit2aig(SigBit bit)
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int bit2aig(SigBit bit)
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{
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{
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if (aig_map.count(bit) == 0)
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auto it = aig_map.find(bit);
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{
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if (it != aig_map.end()) {
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aig_map[bit] = -1;
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log_assert(it->second >= 0);
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return it->second;
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if (initstate_bits.count(bit)) {
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log_assert(initstate_ff > 0);
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aig_map[bit] = initstate_ff;
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} else
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if (not_map.count(bit)) {
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int a = bit2aig(not_map.at(bit)) ^ 1;
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aig_map[bit] = a;
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} else
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if (and_map.count(bit)) {
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auto args = and_map.at(bit);
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int a0 = bit2aig(args.first);
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int a1 = bit2aig(args.second);
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aig_map[bit] = mkgate(a0, a1);
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} else
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if (alias_map.count(bit)) {
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int a = bit2aig(alias_map.at(bit));
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aig_map[bit] = a;
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}
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if (bit == State::Sx || bit == State::Sz)
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log_error("Design contains 'x' or 'z' bits. Use 'setundef' to replace those constants.\n");
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}
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}
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log_assert(aig_map.at(bit) >= 0);
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// NB: Cannot use iterator returned from aig_map.insert()
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return aig_map.at(bit);
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// since this function is called recursively
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int a = -1;
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if (not_map.count(bit)) {
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a = bit2aig(not_map.at(bit)) ^ 1;
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} else
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if (and_map.count(bit)) {
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auto args = and_map.at(bit);
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int a0 = bit2aig(args.first);
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int a1 = bit2aig(args.second);
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a = mkgate(a0, a1);
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} else
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if (alias_map.count(bit)) {
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a = bit2aig(alias_map.at(bit));
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}
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if (bit == State::Sx || bit == State::Sz)
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log_error("Design contains 'x' or 'z' bits. Use 'setundef' to replace those constants.\n");
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log_assert(a >= 0);
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aig_map[bit] = a;
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return a;
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}
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}
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AigerWriter(Module *module, bool zinit_mode, bool imode, bool omode, bool bmode) : module(module), zinit_mode(zinit_mode), sigmap(module)
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AigerWriter(Module *module, bool zinit_mode, bool imode, bool omode, bool bmode) : module(module), zinit_mode(zinit_mode), sigmap(module)
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