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Merge branch 'xc7mux' into xc7mux_wip

This commit is contained in:
Eddie Hung 2019-06-21 14:37:20 -07:00
parent f433a52374 e581a3e6f4
commit 523e7ee782
3 changed files with 15 additions and 7 deletions
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14
backends/aiger/xaiger.cc
View File

@ -86,14 +86,15 @@ struct XAigerWriter
int bit2aig(SigBit bit) int bit2aig(SigBit bit)
{ {
// NB: Cannot use iterator returned from aig_map.insert()
// since this function is called recursively
auto it = aig_map.find(bit); auto it = aig_map.find(bit);
if (it != aig_map.end()) { if (it != aig_map.end()) {
log_assert(it->second >= 0); log_assert(it->second >= 0);
return it->second; return it->second;
} }
// NB: Cannot use iterator returned from aig_map.insert()
// since this function is called recursively
int a = -1; int a = -1;
if (not_map.count(bit)) { if (not_map.count(bit)) {
a = bit2aig(not_map.at(bit)) ^ 1; a = bit2aig(not_map.at(bit)) ^ 1;
@ -109,7 +110,7 @@ struct XAigerWriter
} }
if (bit == State::Sx || bit == State::Sz) { if (bit == State::Sx || bit == State::Sz) {
log_debug("Bit '%s' contains 'x' or 'z' bits. Treating as 1'b0.\n", log_signal(bit)); log_debug("Design contains 'x' or 'z' bits. Treating as 1'b0.\n");
a = aig_map.at(State::S0); a = aig_map.at(State::S0);
} }
@ -428,12 +429,13 @@ struct XAigerWriter
module->connect(new_bit, bit); module->connect(new_bit, bit);
if (not_map.count(bit)) if (not_map.count(bit))
not_map[new_bit] = not_map.at(bit); not_map[new_bit] = not_map.at(bit);
else if (and_map.count(bit)) else if (and_map.count(bit)) {
and_map[new_bit] = and_map.at(bit); //and_map[new_bit] = and_map.at(bit); // Breaks gcc-4.8
and_map.insert(std::make_pair(new_bit, and_map.at(bit)));
}
else if (alias_map.count(bit)) else if (alias_map.count(bit))
alias_map[new_bit] = alias_map.at(bit); alias_map[new_bit] = alias_map.at(bit);
else else
//log_abort();
alias_map[new_bit] = bit; alias_map[new_bit] = bit;
output_bits.erase(bit); output_bits.erase(bit);
output_bits.insert(new_bit); output_bits.insert(new_bit);

7
frontends/aiger/aigerparse.cc
View File

@ -114,13 +114,20 @@ struct ConstEvalAig
RTLIL::Cell *cell = sig2driver.at(output); RTLIL::Cell *cell = sig2driver.at(output);
RTLIL::SigBit sig_a = cell->getPort("\\A"); RTLIL::SigBit sig_a = cell->getPort("\\A");
sig2deps[sig_a].reserve(sig2deps[sig_a].size() + sig2deps[output].size()); // Reserve so that any invalidation
// that may occur does so here, and
// not mid insertion (below)
sig2deps[sig_a].insert(sig2deps[output].begin(), sig2deps[output].end()); sig2deps[sig_a].insert(sig2deps[output].begin(), sig2deps[output].end());
if (!inputs.count(sig_a)) if (!inputs.count(sig_a))
compute_deps(sig_a, inputs); compute_deps(sig_a, inputs);
if (cell->type == "$_AND_") { if (cell->type == "$_AND_") {
RTLIL::SigSpec sig_b = cell->getPort("\\B"); RTLIL::SigSpec sig_b = cell->getPort("\\B");
sig2deps[sig_b].reserve(sig2deps[sig_b].size() + sig2deps[output].size()); // Reserve so that any invalidation
// that may occur does so here, and
// not mid insertion (below)
sig2deps[sig_b].insert(sig2deps[output].begin(), sig2deps[output].end()); sig2deps[sig_b].insert(sig2deps[output].begin(), sig2deps[output].end());
if (!inputs.count(sig_b)) if (!inputs.count(sig_b))
compute_deps(sig_b, inputs); compute_deps(sig_b, inputs);
} }

1
tests/tools/autotest.sh
View File

@ -226,7 +226,6 @@ do
if $warn_iverilog_git; then if $warn_iverilog_git; then
echo "Note: Make sure that 'iverilog' is an up-to-date git checkout of Icarus Verilog." echo "Note: Make sure that 'iverilog' is an up-to-date git checkout of Icarus Verilog."
fi fi
cat ${bn}.err
$keeprunning || exit 1 $keeprunning || exit 1
fi fi
done done