mirror of https://github.com/YosysHQ/yosys.git
Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux
This commit is contained in:
commit
5174082208
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@ -294,12 +294,8 @@ struct ShregmapWorker
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if (opts.init || sigbit_init.count(q_bit) == 0)
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{
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auto r = sigbit_chain_next.insert(std::make_pair(d_bit, cell));
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if (!r.second) {
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if (!r.second)
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sigbit_with_non_chain_users.insert(d_bit);
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Wire *wire = module->addWire(NEW_ID);
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module->connect(wire, d_bit);
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sigbit_chain_next.insert(std::make_pair(wire, cell));
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}
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sigbit_chain_prev[q_bit] = cell;
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continue;
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@ -319,14 +315,14 @@ struct ShregmapWorker
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{
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for (auto it : sigbit_chain_next)
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{
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Cell *c1, *c2 = it.second;
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if (opts.tech == nullptr && sigbit_with_non_chain_users.count(it.first))
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goto start_cell;
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if (sigbit_chain_prev.count(it.first) != 0)
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c1 = sigbit_chain_prev.at(it.first, nullptr);
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if (c1 != nullptr)
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{
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Cell *c1 = sigbit_chain_prev.at(it.first);
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Cell *c2 = it.second;
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if (c1->type != c2->type)
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goto start_cell;
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@ -336,6 +332,15 @@ struct ShregmapWorker
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IdString d_port = opts.ffcells.at(c1->type).first;
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IdString q_port = opts.ffcells.at(c1->type).second;
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// If the previous cell's D has other non chain users,
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// then it is possible that this previous cell could
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// be a start of the chain
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SigBit d_bit = sigmap(c1->getPort(d_port).as_bit());
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if (sigbit_with_non_chain_users.count(d_bit)) {
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c2 = c1;
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goto start_cell;
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}
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auto c1_conn = c1->connections();
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auto c2_conn = c1->connections();
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@ -352,7 +357,7 @@ struct ShregmapWorker
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}
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start_cell:
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chain_start_cells.insert(it.second);
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chain_start_cells.insert(c2);
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}
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}
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