riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

write_aiger: Fix non-$_FF_ FFs 

This broke while switching sby's formal flows to always use $_FF_'s.
This commit is contained in:
Jannis Harder 2022-08-18 13:56:22 +02:00
parent 1c36f4cc2c
commit 5142fb3b5c
2 changed files with 8 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
backends/aiger/aiger.cc
View File

@ -202,7 +202,7 @@ struct AigerWriter
ff_map[Q] = D; ff_map[Q] = D;
if (cell->type != ID($_FF_)) { if (cell->type != ID($_FF_)) {
auto sig_clk = sigmap(cell->getPort(ID::CLK).as_bit()); auto sig_clk = sigmap(cell->getPort(ID::C).as_bit());
ywmap_clocks[sig_clk] |= cell->type == ID($_DFF_N_) ? 2 : 1; ywmap_clocks[sig_clk] |= cell->type == ID($_DFF_N_) ? 2 : 1;
} }
continue; continue;

7
tests/various/aiger_dff.ys Normal file
View File

@ -0,0 +1,7 @@
read_verilog -icells <<EOT
module top(input clk, d, output q);
\$_DFF_N_ dffn(.C(clk), .D(d), .Q(q));
endmodule
EOT
write_aiger -zinit -ywmap aiger_dff.out /dev/null
!grep -qF negedge aiger_dff.out