From 3fc474aa73cb447f22e9ca35687b054102f4be32 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 9 Apr 2019 10:06:44 -0700 Subject: [PATCH 001/213] Add support for synth_xilinx -abc9 and ignore abc9 -dress opt --- passes/techmap/abc9.cc | 5 +++++ techlibs/xilinx/synth_xilinx.cc | 10 +++++++++- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index da3d36354..6e2e349ee 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -1237,6 +1237,11 @@ struct Abc9Pass : public Pass { map_mux16 = true; continue; } + if (arg == "-dress") { + // TODO + abc_dress = true; + continue; + } if (arg == "-g" && argidx+1 < args.size()) { for (auto g : split_tokens(args[++argidx], ",")) { vector gate_list; diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 805ae8e6e..090bcce85 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -80,6 +80,9 @@ struct SynthXilinxPass : public Pass log(" -retime\n"); log(" run 'abc' with -dff option\n"); log("\n"); + log(" -abc9\n"); + log(" use abc9 instead of abc\n"); + log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); log("\n"); @@ -142,6 +145,7 @@ struct SynthXilinxPass : public Pass std::string edif_file; std::string blif_file; std::string run_from, run_to; + std::string abc = "abc"; bool flatten = false; bool retime = false; bool vpr = false; @@ -191,6 +195,10 @@ struct SynthXilinxPass : public Pass nodram = true; continue; } + if (args[argidx] == "-abc9") { + abc = "abc9"; + continue; + } break; } extra_args(args, argidx, design); @@ -267,7 +275,7 @@ struct SynthXilinxPass : public Pass if (check_label(active, run_from, run_to, "map_luts")) { - Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); + Pass::call(design, abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); Pass::call(design, "clean"); Pass::call(design, "techmap -map +/xilinx/lut_map.v"); } From 3b6f85b0a6fb08b44dfa7417fce1aeefe9f20e3e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 9 Apr 2019 10:09:43 -0700 Subject: [PATCH 002/213] Comment out --- passes/techmap/abc9.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 6e2e349ee..ec4a28d08 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -1239,7 +1239,7 @@ struct Abc9Pass : public Pass { } if (arg == "-dress") { // TODO - abc_dress = true; + //abc_dress = true; continue; } if (arg == "-g" && argidx+1 < args.size()) { From bd523abef5babcc16fbdd67dbf868bd601acaced Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 9 Apr 2019 10:32:58 -0700 Subject: [PATCH 003/213] Add 'setundef -zero' call prior to aigmap in abc9 --- passes/techmap/abc9.cc | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index ec4a28d08..b0326372e 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -403,6 +403,10 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri RTLIL::Selection& sel = design->selection_stack.back(); sel.select(module); + // Adopt same behaviour as abc + // TODO: How to specify don't-care to abc9? + Pass::call(design, "setundef -zero"); + Pass::call(design, "aigmap"); handle_loops(design); From 7e304c362bc342abaed46f1906cad8b118ba45e5 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 9 Apr 2019 10:58:06 -0700 Subject: [PATCH 004/213] Add "-box" option to abc9 --- passes/techmap/abc9.cc | 29 ++++++++++++++++++++++------- 1 file changed, 22 insertions(+), 7 deletions(-) diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index b0326372e..765dc7fb8 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -272,7 +272,7 @@ failed: void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file, std::string liberty_file, std::string constr_file, bool cleanup, vector lut_costs, bool dff_mode, std::string clk_str, bool keepff, std::string delay_target, std::string sop_inputs, std::string sop_products, std::string lutin_shared, bool fast_mode, - const std::vector &cells, bool show_tempdir, bool sop_mode) + const std::vector &cells, bool show_tempdir, bool sop_mode, std::string box_file) { module = current_module; map_autoidx = autoidx++; @@ -329,8 +329,11 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri if (!constr_file.empty()) abc_script += stringf("read_constr -v %s; ", constr_file.c_str()); } else - if (!lut_costs.empty()) + if (!lut_costs.empty()) { abc_script += stringf("read_lut %s/lutdefs.txt; ", tempdir_name.c_str()); + if (!box_file.empty()) + abc_script += stringf("read_box -v %s; ", box_file.c_str()); + } else abc_script += stringf("read_library %s/stdcells.genlib; ", tempdir_name.c_str()); @@ -1004,7 +1007,7 @@ struct Abc9Pass : public Pass { log(" file format).\n"); log("\n"); log(" -constr \n"); - log(" pass this file with timing constraints to ABC. use with -liberty.\n"); + log(" pass this file with timing constraints to ABC. Use with -liberty.\n"); log("\n"); log(" a constr file contains two lines:\n"); log(" set_driving_cell \n"); @@ -1094,6 +1097,9 @@ struct Abc9Pass : public Pass { log(" this attribute is a unique integer for each ABC process started. This\n"); log(" is useful for debugging the partitioning of clock domains.\n"); log("\n"); + log(" -box \n"); + log(" pass this file with box library to ABC. Use with -lut.\n"); + log("\n"); log("When neither -liberty nor -lut is used, the Yosys standard cell library is\n"); log("loaded into ABC before the ABC script is executed.\n"); log("\n"); @@ -1123,7 +1129,7 @@ struct Abc9Pass : public Pass { #else std::string exe_file = proc_self_dirname() + "yosys-abc"; #endif - std::string script_file, liberty_file, constr_file, clk_str; + std::string script_file, liberty_file, constr_file, clk_str, box_file; std::string delay_target, sop_inputs, sop_products, lutin_shared = "-S 1"; bool fast_mode = false, dff_mode = false, keepff = false, cleanup = true; bool show_tempdir = false, sop_mode = false; @@ -1169,8 +1175,8 @@ struct Abc9Pass : public Pass { continue; } if (arg == "-constr" && argidx+1 < args.size()) { - rewrite_filename(constr_file); constr_file = args[++argidx]; + rewrite_filename(constr_file); if (!constr_file.empty() && !is_absolute_path(constr_file)) constr_file = std::string(pwd) + "/" + constr_file; continue; @@ -1357,6 +1363,13 @@ struct Abc9Pass : public Pass { markgroups = true; continue; } + if (arg == "-box" && argidx+1 < args.size()) { + box_file = args[++argidx]; + rewrite_filename(box_file); + if (!box_file.empty() && !is_absolute_path(box_file)) + box_file = std::string(pwd) + "/" + box_file; + continue; + } break; } extra_args(args, argidx, design); @@ -1395,7 +1408,8 @@ struct Abc9Pass : public Pass { if (!dff_mode || !clk_str.empty()) { abc9_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, dff_mode, clk_str, keepff, - delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, mod->selected_cells(), show_tempdir, sop_mode); + delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, mod->selected_cells(), show_tempdir, sop_mode, + box_file); continue; } @@ -1540,7 +1554,8 @@ struct Abc9Pass : public Pass { en_polarity = std::get<2>(it.first); en_sig = assign_map(std::get<3>(it.first)); abc9_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, !clk_sig.empty(), "$", - keepff, delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, it.second, show_tempdir, sop_mode); + keepff, delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, it.second, show_tempdir, sop_mode, + box_file); assign_map.set(mod); } } From 2ae26b986cd550e4d3ce4dc5c4f7235144a6f83c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 9 Apr 2019 10:58:58 -0700 Subject: [PATCH 005/213] Add techlibs/xilinx/cells.box --- techlibs/xilinx/Makefile.inc | 1 + techlibs/xilinx/cells.box | 5 +++++ 2 files changed, 6 insertions(+) create mode 100644 techlibs/xilinx/cells.box diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index d68f03bb4..9937c0c9c 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -30,6 +30,7 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells.box)) $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh)) $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_32.vh)) diff --git a/techlibs/xilinx/cells.box b/techlibs/xilinx/cells.box new file mode 100644 index 000000000..31ad4a656 --- /dev/null +++ b/techlibs/xilinx/cells.box @@ -0,0 +1,5 @@ +MUXF7 1 0 2 1 +1 1 + +MUXF8 2 0 2 1 +1 1 From f2042fc7c43af9f43d42fdd2e8034963122ff5eb Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 9 Apr 2019 11:01:46 -0700 Subject: [PATCH 006/213] synth_xilinx with abc9 to use -box --- techlibs/xilinx/synth_xilinx.cc | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 090bcce85..eb37feb83 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -275,7 +275,10 @@ struct SynthXilinxPass : public Pass if (check_label(active, run_from, run_to, "map_luts")) { - Pass::call(design, abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); + if (abc == "abc9") + Pass::call(design, abc + " -luts 2:2,3,6:5,10,20 -box +/xilinx/cells.box" + string(retime ? " -dff" : "")); + else + Pass::call(design, abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); Pass::call(design, "clean"); Pass::call(design, "techmap -map +/xilinx/lut_map.v"); } From d536379c62d926967d5e7743b32990167f91e762 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 9 Apr 2019 14:31:31 -0700 Subject: [PATCH 007/213] Add "-lut " support to abc9 --- passes/techmap/abc9.cc | 44 +++++++++++++++++++++++++++++------------- 1 file changed, 31 insertions(+), 13 deletions(-) diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 765dc7fb8..e26920f20 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -272,7 +272,7 @@ failed: void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file, std::string liberty_file, std::string constr_file, bool cleanup, vector lut_costs, bool dff_mode, std::string clk_str, bool keepff, std::string delay_target, std::string sop_inputs, std::string sop_products, std::string lutin_shared, bool fast_mode, - const std::vector &cells, bool show_tempdir, bool sop_mode, std::string box_file) + const std::vector &cells, bool show_tempdir, bool sop_mode, std::string box_file, std::string lut_file) { module = current_module; map_autoidx = autoidx++; @@ -334,6 +334,12 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri if (!box_file.empty()) abc_script += stringf("read_box -v %s; ", box_file.c_str()); } + else + if (!lut_file.empty()) { + abc_script += stringf("read_lut %s; ", lut_file.c_str()); + if (!box_file.empty()) + abc_script += stringf("read_box -v %s; ", box_file.c_str()); + } else abc_script += stringf("read_library %s/stdcells.genlib; ", tempdir_name.c_str()); @@ -348,11 +354,11 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri abc_script += script_file[i]; } else abc_script += stringf("source %s", script_file.c_str()); - } else if (!lut_costs.empty()) { - bool all_luts_cost_same = true; - for (int this_cost : lut_costs) - if (this_cost != lut_costs.front()) - all_luts_cost_same = false; + } else if (!lut_costs.empty() || !lut_file.empty()) { + //bool all_luts_cost_same = true; + //for (int this_cost : lut_costs) + // if (this_cost != lut_costs.front()) + // all_luts_cost_same = false; abc_script += fast_mode ? ABC_FAST_COMMAND_LUT : ABC_COMMAND_LUT; //if (all_luts_cost_same && !fast_mode) // abc_script += "; lutpack {S}"; @@ -579,7 +585,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri RTLIL::Cell *cell; RTLIL::SigBit a_bit = c->getPort("\\A").as_bit(); RTLIL::SigBit y_bit = c->getPort("\\Y").as_bit(); - if (!lut_costs.empty()) { + if (!lut_costs.empty() || !lut_file.empty()) { // ABC can return NOT gates that drive POs if (a_bit.wire->port_input) { // If it's a NOT gate that comes from a primary input directly @@ -1044,6 +1050,9 @@ struct Abc9Pass : public Pass { log(" the area cost doubles with each additional input bit. the delay cost\n"); log(" is still constant for all lut widths.\n"); log("\n"); + log(" -lut \n"); + log(" pass this file with lut library to ABC.\n"); + log("\n"); log(" -luts ,,,:,..\n"); log(" generate netlist using luts. Use the specified costs for luts with 1,\n"); log(" 2, 3, .. inputs.\n"); @@ -1129,7 +1138,7 @@ struct Abc9Pass : public Pass { #else std::string exe_file = proc_self_dirname() + "yosys-abc"; #endif - std::string script_file, liberty_file, constr_file, clk_str, box_file; + std::string script_file, liberty_file, constr_file, clk_str, box_file, lut_file; std::string delay_target, sop_inputs, sop_products, lutin_shared = "-S 1"; bool fast_mode = false, dff_mode = false, keepff = false, cleanup = true; bool show_tempdir = false, sop_mode = false; @@ -1205,8 +1214,17 @@ struct Abc9Pass : public Pass { lut_mode = atoi(arg.substr(0, pos).c_str()); lut_mode2 = atoi(arg.substr(pos+1).c_str()); } else { - lut_mode = atoi(arg.c_str()); - lut_mode2 = lut_mode; + pos = arg.find_first_of('.'); + if (pos != string::npos) { + lut_file = arg; + rewrite_filename(lut_file); + if (!lut_file.empty() && !is_absolute_path(lut_file)) + lut_file = std::string(pwd) + "/" + lut_file; + } + else { + lut_mode = atoi(arg.c_str()); + lut_mode2 = lut_mode; + } } lut_costs.clear(); for (int i = 0; i < lut_mode; i++) @@ -1374,7 +1392,7 @@ struct Abc9Pass : public Pass { } extra_args(args, argidx, design); - if (!lut_costs.empty() && !liberty_file.empty()) + if ((!lut_costs.empty() || !lut_file.empty()) && !liberty_file.empty()) log_cmd_error("Got -lut and -liberty! This two options are exclusive.\n"); if (!constr_file.empty() && liberty_file.empty()) log_cmd_error("Got -constr but no -liberty!\n"); @@ -1409,7 +1427,7 @@ struct Abc9Pass : public Pass { if (!dff_mode || !clk_str.empty()) { abc9_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, dff_mode, clk_str, keepff, delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, mod->selected_cells(), show_tempdir, sop_mode, - box_file); + box_file, lut_file); continue; } @@ -1555,7 +1573,7 @@ struct Abc9Pass : public Pass { en_sig = assign_map(std::get<3>(it.first)); abc9_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, !clk_sig.empty(), "$", keepff, delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, it.second, show_tempdir, sop_mode, - box_file); + box_file, lut_file); assign_map.set(mod); } } From b9e19071b8596b8d06b99cbb653325c0c9dc330f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 9 Apr 2019 14:32:10 -0700 Subject: [PATCH 008/213] Add delays to cells.box --- techlibs/xilinx/cells.box | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/techlibs/xilinx/cells.box b/techlibs/xilinx/cells.box index 31ad4a656..c8092db6e 100644 --- a/techlibs/xilinx/cells.box +++ b/techlibs/xilinx/cells.box @@ -1,5 +1,13 @@ -MUXF7 1 0 2 1 -1 1 +# Max delays from https://pastebin.com/v2hrcksd +# from https://github.com/SymbiFlow/prjxray/pull/706#issuecomment-479380321 -MUXF8 2 0 2 1 -1 1 +# F7BMUX slower than F7AMUX +# Inputs: 0 1 S0 +# Outputs: OUT +F7BMUX 1 0 3 1 +217 223 296 + +# Inputs: 0 1 S0 +# Outputs: OUT +MUXF8 2 0 3 1 +104 94 273 From fd88ab5c834a45f4828a03fe7722b321e5f7c032 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 9 Apr 2019 14:32:39 -0700 Subject: [PATCH 009/213] synth_xilinx to call abc with -lut +/xilinx/cells.lut --- techlibs/xilinx/synth_xilinx.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index eb37feb83..e2a2dfeeb 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -276,9 +276,9 @@ struct SynthXilinxPass : public Pass if (check_label(active, run_from, run_to, "map_luts")) { if (abc == "abc9") - Pass::call(design, abc + " -luts 2:2,3,6:5,10,20 -box +/xilinx/cells.box" + string(retime ? " -dff" : "")); + Pass::call(design, abc + " -lut +/xilinx/cells.lut -box +/xilinx/cells.box" + string(retime ? " -dff" : "")); else - Pass::call(design, abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); + Pass::call(design, abc + " -lut +/xilinx/cells.lut" + string(retime ? " -dff" : "")); Pass::call(design, "clean"); Pass::call(design, "techmap -map +/xilinx/lut_map.v"); } From 3e368593eb22d16de60c44ea721ca146082d3472 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 9 Apr 2019 14:33:37 -0700 Subject: [PATCH 010/213] Add cells.lut to techlibs/xilinx/ --- techlibs/xilinx/Makefile.inc | 1 + techlibs/xilinx/cells.lut | 15 +++++++++++++++ 2 files changed, 16 insertions(+) create mode 100644 techlibs/xilinx/cells.lut diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index 9937c0c9c..432bb0770 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -31,6 +31,7 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells.box)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells.lut)) $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh)) $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_32.vh)) diff --git a/techlibs/xilinx/cells.lut b/techlibs/xilinx/cells.lut new file mode 100644 index 000000000..3f3b69a8e --- /dev/null +++ b/techlibs/xilinx/cells.lut @@ -0,0 +1,15 @@ +# Max delays from https://pastebin.com/v2hrcksd +# from https://github.com/SymbiFlow/prjxray/pull/706#issuecomment-479380321 + +# Since LUT delays are pushed onto the fabric as routing delays, +# assume each input costs +100ps + +# K area delay +1 11 224 +2 12 224 324 +3 13 224 324 424 +4 14 224 324 424 524 +5 15 224 324 424 524 624 +6 20 224 324 424 524 624 724 +7 40 224 324 424 524 624 724 1020 +8 80 224 324 424 524 624 724 1020 1293 From 4dac9818bde02222f951c25ada5f3fd651ea4e36 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 10 Apr 2019 08:49:39 -0700 Subject: [PATCH 011/213] Update LUT delays --- techlibs/xilinx/cells.lut | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/techlibs/xilinx/cells.lut b/techlibs/xilinx/cells.lut index 3f3b69a8e..a1d9b9c42 100644 --- a/techlibs/xilinx/cells.lut +++ b/techlibs/xilinx/cells.lut @@ -1,15 +1,12 @@ # Max delays from https://pastebin.com/v2hrcksd # from https://github.com/SymbiFlow/prjxray/pull/706#issuecomment-479380321 -# Since LUT delays are pushed onto the fabric as routing delays, -# assume each input costs +100ps - # K area delay -1 11 224 -2 12 224 324 -3 13 224 324 424 -4 14 224 324 424 524 -5 15 224 324 424 524 624 -6 20 224 324 424 524 624 724 -7 40 224 324 424 524 624 724 1020 -8 80 224 324 424 524 624 724 1020 1293 +1 11 624 +2 12 624 +3 13 624 +4 14 624 +5 15 624 +6 20 724 +7 40 1020 +8 80 1293 From e0b46eb4cbadafa5f03a5337f761d0ede2b993fa Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 10 Apr 2019 08:49:55 -0700 Subject: [PATCH 012/213] WIP for $shiftx to wide mux --- techlibs/xilinx/cells_map.v | 64 ++++++++++++++++++++++++++++++++++++- 1 file changed, 63 insertions(+), 1 deletion(-) diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index d5801c0fc..4f5c7ff18 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -17,4 +17,66 @@ * */ -// Empty for now +module \$shiftx (A, B, Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 1; + parameter B_WIDTH = 1; + parameter Y_WIDTH = 1; + + input [A_WIDTH-1:0] A; + input [B_WIDTH-1:0] B; + output [Y_WIDTH-1:0] Y; + + generate + genvar i; + if (B_WIDTH < 3) begin + reg _TECHMAP_FAIL_; + assign _TECHMAP_FAIL_ = 1; + end + else if (B_WIDTH == 3) begin + localparam a_width0 = Y_WIDTH * (2 ** (B_WIDTH-1)); + localparam a_widthN = A_WIDTH - a_width0; + wire [Y_WIDTH-1:0] T0, T1; + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[a_width0-1:0]), .B(B[B_WIDTH-2:0]), .Y(T0)); + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1)); + //MUXF7 fpga_mux[Y_WIDTH-1:0] (.I0(T0), .I1(T1), .S(B[B_WIDTH-1]), .O(Y)); + for (i = 0; i < Y_WIDTH; i++) + MUXF7 fpga_mux (.I0(T0[i]), .I1(T1[i]), .S(B[B_WIDTH-1]), .O(Y[i])); + end + else if (B_WIDTH == 4) begin + localparam a_width0 = Y_WIDTH * (2 ** (B_WIDTH-2)); + localparam num_mux8 = A_WIDTH / a_width0; + localparam a_widthN = A_WIDTH - num_mux8*a_width0; + wire [Y_WIDTH*B_WIDTH-1:0] T; + wire [Y_WIDTH-1:0] T0, T1; + for (i = 0; i < B_WIDTH; i++) + if (i < num_mux8) + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(B_WIDTH-2), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[(i+1)*a_width0-1:i*a_width0]), .B(B[B_WIDTH-3:0]), .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH])); + else if (i == num_mux8 && A_WIDTH > i*a_width0) + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH])); + else + assign T[(i+1)*Y_WIDTH-1:i*Y_WIDTH] = {Y_WIDTH{1'bx}}; + for (i = 0; i < Y_WIDTH; i++) begin + MUXF7 fpga_mux_0 (.I0(T[i*B_WIDTH+0]), .I1(T[i*B_WIDTH+1]), .S(B[B_WIDTH-2]), .O(T0[i])); + MUXF7 fpga_mux_1 (.I0(T[i*B_WIDTH+2]), .I1(T[i*B_WIDTH+3]), .S(B[B_WIDTH-2]), .O(T1[i])); + MUXF8 fpga_mux_2 (.I0(T0[i]), .I1(T1[i]), .S(B[B_WIDTH-1]), .O(Y[i])); + end + end + else begin + localparam a_width0 = Y_WIDTH * (2 ** 4); + localparam num_mux16 = A_WIDTH / a_width0; + localparam a_widthN = A_WIDTH - num_mux16*a_width0; + wire [Y_WIDTH*(2**(B_WIDTH-4))-1:0] T; + for (i = 0; i < 2 ** (B_WIDTH-4); i++) + if (i < num_mux16) + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[(i+1)*a_width0-1:i*a_width0]), .B(B[4-1:0]), .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH])); + else if (i == num_mux16 && a_widthN > 0) begin + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH])); + end + else + assign T[(i+1)*Y_WIDTH-1:i*Y_WIDTH] = {Y_WIDTH{1'bx}}; + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(Y_WIDTH*(2**(B_WIDTH-4))), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y)); + end + endgenerate +endmodule From 526aef9c2a9d61721add1c5ef1f85d439bfbb61e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 10 Apr 2019 08:50:31 -0700 Subject: [PATCH 013/213] Move map_cells to before map_luts --- techlibs/xilinx/synth_xilinx.cc | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index e2a2dfeeb..6d3999ae0 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -264,25 +264,15 @@ struct SynthXilinxPass : public Pass Pass::call(design, "opt -full"); if (vpr) { - Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v -D _EXPLICIT_CARRY"); + Pass::call(design, "techmap -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v -D _EXPLICIT_CARRY"); } else { - Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v"); + Pass::call(design, "techmap -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v"); } Pass::call(design, "hierarchy -check"); Pass::call(design, "opt -fast"); } - if (check_label(active, run_from, run_to, "map_luts")) - { - if (abc == "abc9") - Pass::call(design, abc + " -lut +/xilinx/cells.lut -box +/xilinx/cells.box" + string(retime ? " -dff" : "")); - else - Pass::call(design, abc + " -lut +/xilinx/cells.lut" + string(retime ? " -dff" : "")); - Pass::call(design, "clean"); - Pass::call(design, "techmap -map +/xilinx/lut_map.v"); - } - if (check_label(active, run_from, run_to, "map_cells")) { Pass::call(design, "techmap -map +/xilinx/cells_map.v"); @@ -291,6 +281,17 @@ struct SynthXilinxPass : public Pass Pass::call(design, "clean"); } + if (check_label(active, run_from, run_to, "map_luts")) + { + Pass::call(design, "techmap -map +/techmap.v"); + if (abc == "abc9") + Pass::call(design, abc + " -lut +/xilinx/cells.lut -box +/xilinx/cells.box" + string(retime ? " -dff" : "")); + else + Pass::call(design, abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); + Pass::call(design, "clean"); + Pass::call(design, "techmap -map +/xilinx/lut_map.v"); + } + if (check_label(active, run_from, run_to, "check")) { Pass::call(design, "hierarchy -check"); From 1ec949d5edfb6b13b8bf412763ae272a47fec894 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 10 Apr 2019 09:02:42 -0700 Subject: [PATCH 014/213] Tidy up --- techlibs/xilinx/cells_map.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 4f5c7ff18..ff33cf8ff 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -53,7 +53,7 @@ module \$shiftx (A, B, Y); for (i = 0; i < B_WIDTH; i++) if (i < num_mux8) \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(B_WIDTH-2), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[(i+1)*a_width0-1:i*a_width0]), .B(B[B_WIDTH-3:0]), .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH])); - else if (i == num_mux8 && A_WIDTH > i*a_width0) + else if (i == num_mux8 && a_widthN > 0) \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH])); else assign T[(i+1)*Y_WIDTH-1:i*Y_WIDTH] = {Y_WIDTH{1'bx}}; From 17a02df05cb04bf9c597564b130e556f186154f3 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 10 Apr 2019 12:36:06 -0700 Subject: [PATCH 015/213] ff_map.v after abc --- techlibs/xilinx/synth_xilinx.cc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 6d3999ae0..9178182fb 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -264,9 +264,9 @@ struct SynthXilinxPass : public Pass Pass::call(design, "opt -full"); if (vpr) { - Pass::call(design, "techmap -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v -D _EXPLICIT_CARRY"); + Pass::call(design, "techmap -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY"); } else { - Pass::call(design, "techmap -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v"); + Pass::call(design, "techmap -map +/xilinx/arith_map.v"); } Pass::call(design, "hierarchy -check"); @@ -276,8 +276,6 @@ struct SynthXilinxPass : public Pass if (check_label(active, run_from, run_to, "map_cells")) { Pass::call(design, "techmap -map +/xilinx/cells_map.v"); - Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " - "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT"); Pass::call(design, "clean"); } @@ -289,7 +287,9 @@ struct SynthXilinxPass : public Pass else Pass::call(design, abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); Pass::call(design, "clean"); - Pass::call(design, "techmap -map +/xilinx/lut_map.v"); + Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v"); + Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " + "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT"); } if (check_label(active, run_from, run_to, "check")) From 32561332b21b7b072fa6619f0bbb29a69cb30f33 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 10 Apr 2019 14:48:58 -0700 Subject: [PATCH 016/213] Update doc for synth_xilinx --- techlibs/xilinx/synth_xilinx.cc | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 9178182fb..10902a560 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -113,19 +113,20 @@ struct SynthXilinxPass : public Pass log(" dffsr2dff\n"); log(" dff2dffe\n"); log(" opt -full\n"); - log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v\n"); + log(" techmap -map +/xilinx/arith_map.v\n"); log(" opt -fast\n"); log("\n"); - log(" map_luts:\n"); - log(" abc -luts 2:2,3,6:5,10,20 [-dff] (without '-vpr' only!)\n"); - log(" abc -lut 5 [-dff] (with '-vpr' only!)\n"); - log(" clean\n"); - log("\n"); log(" map_cells:\n"); log(" techmap -map +/xilinx/cells_map.v\n"); + log(" clean\n"); + log("\n"); + log(" map_luts:\n"); + log(" techmap -map +/techmap.v\n"); + log(" abc -luts 2:2,3,6:5,10,20 [-dff]\n"); + log(" clean\n"); + log(" techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v\n"); log(" dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT \\\n"); log(" -ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT\n"); - log(" clean\n"); log("\n"); log(" check:\n"); log(" hierarchy -check\n"); From 3f5dab0d09f881d78fca73c54c20118c52b2e563 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 10 Apr 2019 14:51:10 -0700 Subject: [PATCH 017/213] Fix for when B_SIGNED = 1 --- techlibs/xilinx/cells_map.v | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index ff33cf8ff..758d2ade3 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -28,12 +28,19 @@ module \$shiftx (A, B, Y); input [B_WIDTH-1:0] B; output [Y_WIDTH-1:0] Y; + parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0; + parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0; + generate genvar i; if (B_WIDTH < 3) begin - reg _TECHMAP_FAIL_; + wire _TECHMAP_FAIL_; assign _TECHMAP_FAIL_ = 1; end + // Optimisation to remove B_SIGNED if sign bit of B is constant-0 + else if (B_SIGNED && _TECHMAP_CONSTMSK_B_[B_WIDTH-1] && _TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0) begin + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B[B_WIDTH-2:0]), .Y(Y)); + end else if (B_WIDTH == 3) begin localparam a_width0 = Y_WIDTH * (2 ** (B_WIDTH-1)); localparam a_widthN = A_WIDTH - a_width0; From 3d577586fde783829aae213fac4d1480ce1b8c53 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 10 Apr 2019 16:15:23 -0700 Subject: [PATCH 018/213] Try splitting $shiftx with Y_WIDTH > 1 into Y_WIDTH = 1 --- techlibs/xilinx/cells_map.v | 89 ++++++++++++++++++++----------------- 1 file changed, 48 insertions(+), 41 deletions(-) diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 758d2ade3..253678028 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -32,58 +32,65 @@ module \$shiftx (A, B, Y); parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0; generate - genvar i; - if (B_WIDTH < 3) begin - wire _TECHMAP_FAIL_; - assign _TECHMAP_FAIL_ = 1; + genvar i, j; + if (B_SIGNED) begin + if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && _TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0) + // Optimisation to remove B_SIGNED if sign bit of B is constant-0 + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B[B_WIDTH-2:0]), .Y(Y)); + else + wire _TECHMAP_FAIL_ = 1; end - // Optimisation to remove B_SIGNED if sign bit of B is constant-0 - else if (B_SIGNED && _TECHMAP_CONSTMSK_B_[B_WIDTH-1] && _TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0) begin - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B[B_WIDTH-2:0]), .Y(Y)); - end - else if (B_WIDTH == 3) begin - localparam a_width0 = Y_WIDTH * (2 ** (B_WIDTH-1)); - localparam a_widthN = A_WIDTH - a_width0; - wire [Y_WIDTH-1:0] T0, T1; - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[a_width0-1:0]), .B(B[B_WIDTH-2:0]), .Y(T0)); - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1)); - //MUXF7 fpga_mux[Y_WIDTH-1:0] (.I0(T0), .I1(T1), .S(B[B_WIDTH-1]), .O(Y)); - for (i = 0; i < Y_WIDTH; i++) - MUXF7 fpga_mux (.I0(T0[i]), .I1(T1[i]), .S(B[B_WIDTH-1]), .O(Y[i])); - end - else if (B_WIDTH == 4) begin - localparam a_width0 = Y_WIDTH * (2 ** (B_WIDTH-2)); - localparam num_mux8 = A_WIDTH / a_width0; - localparam a_widthN = A_WIDTH - num_mux8*a_width0; - wire [Y_WIDTH*B_WIDTH-1:0] T; - wire [Y_WIDTH-1:0] T0, T1; - for (i = 0; i < B_WIDTH; i++) - if (i < num_mux8) - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(B_WIDTH-2), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[(i+1)*a_width0-1:i*a_width0]), .B(B[B_WIDTH-3:0]), .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH])); - else if (i == num_mux8 && a_widthN > 0) - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH])); - else - assign T[(i+1)*Y_WIDTH-1:i*Y_WIDTH] = {Y_WIDTH{1'bx}}; + else if (Y_WIDTH > 1) begin for (i = 0; i < Y_WIDTH; i++) begin - MUXF7 fpga_mux_0 (.I0(T[i*B_WIDTH+0]), .I1(T[i*B_WIDTH+1]), .S(B[B_WIDTH-2]), .O(T0[i])); - MUXF7 fpga_mux_1 (.I0(T[i*B_WIDTH+2]), .I1(T[i*B_WIDTH+3]), .S(B[B_WIDTH-2]), .O(T1[i])); - MUXF8 fpga_mux_2 (.I0(T0[i]), .I1(T1[i]), .S(B[B_WIDTH-1]), .O(Y[i])); + wire [A_WIDTH/Y_WIDTH-1:0] A_i; + for (j = 0; j < A_WIDTH/Y_WIDTH; j++) + assign A_i[j] = A[i*Y_WIDTH+j]; + wire [$clog2(A_WIDTH/Y_WIDTH)-1:0] B_i = B/Y_WIDTH; + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH/Y_WIDTH), .B_WIDTH($clog2(A_WIDTH/Y_WIDTH)), .Y_WIDTH(1)) bitblast (.A(A_i), .B(B_i), .Y(Y[i])); end end + else if (B_WIDTH < 3) begin + wire _TECHMAP_FAIL_ = 1; + end + else if (B_WIDTH == 3) begin + localparam a_width0 = 2 ** 2; + localparam a_widthN = A_WIDTH - a_width0; + wire T0, T1; + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[a_width0-1:0]), .B(B[B_WIDTH-2:0]), .Y(T0)); + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1)); + MUXF7 fpga_mux (.I0(T0[i]), .I1(T1[i]), .S(B[B_WIDTH-1]), .O(Y[i])); + end + else if (B_WIDTH == 4) begin + localparam a_width0 = 2 ** 3; + localparam num_mux8 = A_WIDTH / a_width0; + localparam a_widthN = A_WIDTH - num_mux8*a_width0; + wire [B_WIDTH-1:0] T; + wire T0, T1; + for (i = 0; i < B_WIDTH; i++) + if (i < num_mux8) + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(B_WIDTH-2), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[(i+1)*a_width0-1:i*a_width0]), .B(B[B_WIDTH-3:0]), .Y(T[i])); + else if (i == num_mux8 && a_widthN > 0) + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i])); + else + assign T[i] = 1'bx; + MUXF7 fpga_mux_0 (.I0(T[0]), .I1(T[1]), .S(B[B_WIDTH-2]), .O(T0)); + MUXF7 fpga_mux_1 (.I0(T[2]), .I1(T[3]), .S(B[B_WIDTH-2]), .O(T1)); + MUXF8 fpga_mux_2 (.I0(T0), .I1(T1), .S(B[B_WIDTH-1]), .O(Y)); + end else begin - localparam a_width0 = Y_WIDTH * (2 ** 4); + localparam a_width0 = 2 ** 4; localparam num_mux16 = A_WIDTH / a_width0; localparam a_widthN = A_WIDTH - num_mux16*a_width0; - wire [Y_WIDTH*(2**(B_WIDTH-4))-1:0] T; + wire [(2**(B_WIDTH-4))-1:0] T; for (i = 0; i < 2 ** (B_WIDTH-4); i++) - if (i < num_mux16) - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[(i+1)*a_width0-1:i*a_width0]), .B(B[4-1:0]), .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH])); + if (i < num_mux16) + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[(i+1)*a_width0-1:i*a_width0]), .B(B[4-1:0]), .Y(T[i])); else if (i == num_mux16 && a_widthN > 0) begin - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH])); + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i])); end else - assign T[(i+1)*Y_WIDTH-1:i*Y_WIDTH] = {Y_WIDTH{1'bx}}; - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(Y_WIDTH*(2**(B_WIDTH-4))), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y)); + assign T[i] = 1'bx; + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(2**(B_WIDTH-4)), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y)); end endgenerate endmodule From cd7b2de27f4ffd097af7662a0390a5c86e5532a3 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 10 Apr 2019 18:05:09 -0700 Subject: [PATCH 019/213] WIP for cells_map.v -- maybe working? --- techlibs/xilinx/cells_map.v | 59 +++++++++++++++++-------------------- 1 file changed, 27 insertions(+), 32 deletions(-) diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 253678028..93d60f60b 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -31,6 +31,7 @@ module \$shiftx (A, B, Y); parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0; parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0; + localparam NUM = A_WIDTH/Y_WIDTH; generate genvar i, j; if (B_SIGNED) begin @@ -40,57 +41,51 @@ module \$shiftx (A, B, Y); else wire _TECHMAP_FAIL_ = 1; end - else if (Y_WIDTH > 1) begin - for (i = 0; i < Y_WIDTH; i++) begin - wire [A_WIDTH/Y_WIDTH-1:0] A_i; - for (j = 0; j < A_WIDTH/Y_WIDTH; j++) - assign A_i[j] = A[i*Y_WIDTH+j]; - wire [$clog2(A_WIDTH/Y_WIDTH)-1:0] B_i = B/Y_WIDTH; - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH/Y_WIDTH), .B_WIDTH($clog2(A_WIDTH/Y_WIDTH)), .Y_WIDTH(1)) bitblast (.A(A_i), .B(B_i), .Y(Y[i])); - end - end - else if (B_WIDTH < 3) begin + else if (NUM <= 4) begin wire _TECHMAP_FAIL_ = 1; end - else if (B_WIDTH == 3) begin - localparam a_width0 = 2 ** 2; + else if (NUM <= 8) begin + localparam a_width0 = Y_WIDTH * 4; localparam a_widthN = A_WIDTH - a_width0; - wire T0, T1; + wire [Y_WIDTH-1:0] T0, T1; \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[a_width0-1:0]), .B(B[B_WIDTH-2:0]), .Y(T0)); \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1)); - MUXF7 fpga_mux (.I0(T0[i]), .I1(T1[i]), .S(B[B_WIDTH-1]), .O(Y[i])); + for (i = 0; i < Y_WIDTH; i++) + MUXF7 fpga_mux (.I0(T0[i]), .I1(T1[i]), .S(B[B_WIDTH-1]), .O(Y[i])); end - else if (B_WIDTH == 4) begin - localparam a_width0 = 2 ** 3; + else if (NUM <= 16) begin + localparam a_width0 = Y_WIDTH * 4; localparam num_mux8 = A_WIDTH / a_width0; localparam a_widthN = A_WIDTH - num_mux8*a_width0; - wire [B_WIDTH-1:0] T; - wire T0, T1; - for (i = 0; i < B_WIDTH; i++) + wire [Y_WIDTH*4-1:0] T; + wire [Y_WIDTH-1:0] T0, T1; + for (i = 0; i < 4; i++) if (i < num_mux8) - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(B_WIDTH-2), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[(i+1)*a_width0-1:i*a_width0]), .B(B[B_WIDTH-3:0]), .Y(T[i])); + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(B_WIDTH-2), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[(i+1)*a_width0-1:i*a_width0]), .B(B[B_WIDTH-3:0]), .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH])); else if (i == num_mux8 && a_widthN > 0) - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i])); + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH(B_WIDTH-2), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[B_WIDTH-3:0]), .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH])); else - assign T[i] = 1'bx; - MUXF7 fpga_mux_0 (.I0(T[0]), .I1(T[1]), .S(B[B_WIDTH-2]), .O(T0)); - MUXF7 fpga_mux_1 (.I0(T[2]), .I1(T[3]), .S(B[B_WIDTH-2]), .O(T1)); - MUXF8 fpga_mux_2 (.I0(T0), .I1(T1), .S(B[B_WIDTH-1]), .O(Y)); + assign T[(i+1)*Y_WIDTH-1:i*Y_WIDTH] = {Y_WIDTH{1'bx}}; + for (i = 0; i < Y_WIDTH; i++) begin + MUXF7 fpga_mux_0 (.I0(T[0*Y_WIDTH+i]), .I1(T[1*Y_WIDTH+i]), .S(B[B_WIDTH-2]), .O(T0[i])); + MUXF7 fpga_mux_1 (.I0(T[2*Y_WIDTH+i]), .I1(T[3*Y_WIDTH+i]), .S(B[B_WIDTH-2]), .O(T1[i])); + MUXF8 fpga_mux_2 (.I0(T0[i]), .I1(T1[i]), .S(B[B_WIDTH-1]), .O(Y[i])); + end end else begin - localparam a_width0 = 2 ** 4; + localparam a_width0 = Y_WIDTH * 16; localparam num_mux16 = A_WIDTH / a_width0; localparam a_widthN = A_WIDTH - num_mux16*a_width0; - wire [(2**(B_WIDTH-4))-1:0] T; - for (i = 0; i < 2 ** (B_WIDTH-4); i++) + wire [Y_WIDTH * (2 ** ($clog2(NUM)-4))-1:0] T; + for (i = 0; i < 2 ** ($clog2(NUM)-4); i++) if (i < num_mux16) - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[(i+1)*a_width0-1:i*a_width0]), .B(B[4-1:0]), .Y(T[i])); + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH($clog2(a_width0)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[(i+1)*a_width0-1:i*a_width0]), .B(B[$clog2(a_width0)-1:0]), .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH])); else if (i == num_mux16 && a_widthN > 0) begin - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i])); + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_width0)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_width0)-1:0]), .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH])); end else - assign T[i] = 1'bx; - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(2**(B_WIDTH-4)), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y)); + assign T[(i+1)*Y_WIDTH-1:i*Y_WIDTH] = {Y_WIDTH{1'bx}}; + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(Y_WIDTH * (2 ** ($clog2(NUM)-4))), .B_WIDTH(B_WIDTH-$clog2(a_width0)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(T), .B(B[B_WIDTH-1:$clog2(a_width0)]), .Y(Y)); end endgenerate endmodule From 87b8d29a900eef6ec84c87ea7cd87f9a0b744fac Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 11 Apr 2019 09:13:39 -0700 Subject: [PATCH 020/213] Juggle opt calls in synth_xilinx --- techlibs/xilinx/cells_map.v | 77 ++++++++++++++++++--------------- techlibs/xilinx/synth_xilinx.cc | 6 +-- 2 files changed, 44 insertions(+), 39 deletions(-) diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 93d60f60b..253678028 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -31,7 +31,6 @@ module \$shiftx (A, B, Y); parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0; parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0; - localparam NUM = A_WIDTH/Y_WIDTH; generate genvar i, j; if (B_SIGNED) begin @@ -41,51 +40,57 @@ module \$shiftx (A, B, Y); else wire _TECHMAP_FAIL_ = 1; end - else if (NUM <= 4) begin - wire _TECHMAP_FAIL_ = 1; - end - else if (NUM <= 8) begin - localparam a_width0 = Y_WIDTH * 4; - localparam a_widthN = A_WIDTH - a_width0; - wire [Y_WIDTH-1:0] T0, T1; - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[a_width0-1:0]), .B(B[B_WIDTH-2:0]), .Y(T0)); - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1)); - for (i = 0; i < Y_WIDTH; i++) - MUXF7 fpga_mux (.I0(T0[i]), .I1(T1[i]), .S(B[B_WIDTH-1]), .O(Y[i])); - end - else if (NUM <= 16) begin - localparam a_width0 = Y_WIDTH * 4; - localparam num_mux8 = A_WIDTH / a_width0; - localparam a_widthN = A_WIDTH - num_mux8*a_width0; - wire [Y_WIDTH*4-1:0] T; - wire [Y_WIDTH-1:0] T0, T1; - for (i = 0; i < 4; i++) - if (i < num_mux8) - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(B_WIDTH-2), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[(i+1)*a_width0-1:i*a_width0]), .B(B[B_WIDTH-3:0]), .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH])); - else if (i == num_mux8 && a_widthN > 0) - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH(B_WIDTH-2), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[B_WIDTH-3:0]), .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH])); - else - assign T[(i+1)*Y_WIDTH-1:i*Y_WIDTH] = {Y_WIDTH{1'bx}}; + else if (Y_WIDTH > 1) begin for (i = 0; i < Y_WIDTH; i++) begin - MUXF7 fpga_mux_0 (.I0(T[0*Y_WIDTH+i]), .I1(T[1*Y_WIDTH+i]), .S(B[B_WIDTH-2]), .O(T0[i])); - MUXF7 fpga_mux_1 (.I0(T[2*Y_WIDTH+i]), .I1(T[3*Y_WIDTH+i]), .S(B[B_WIDTH-2]), .O(T1[i])); - MUXF8 fpga_mux_2 (.I0(T0[i]), .I1(T1[i]), .S(B[B_WIDTH-1]), .O(Y[i])); + wire [A_WIDTH/Y_WIDTH-1:0] A_i; + for (j = 0; j < A_WIDTH/Y_WIDTH; j++) + assign A_i[j] = A[i*Y_WIDTH+j]; + wire [$clog2(A_WIDTH/Y_WIDTH)-1:0] B_i = B/Y_WIDTH; + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH/Y_WIDTH), .B_WIDTH($clog2(A_WIDTH/Y_WIDTH)), .Y_WIDTH(1)) bitblast (.A(A_i), .B(B_i), .Y(Y[i])); end end + else if (B_WIDTH < 3) begin + wire _TECHMAP_FAIL_ = 1; + end + else if (B_WIDTH == 3) begin + localparam a_width0 = 2 ** 2; + localparam a_widthN = A_WIDTH - a_width0; + wire T0, T1; + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[a_width0-1:0]), .B(B[B_WIDTH-2:0]), .Y(T0)); + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1)); + MUXF7 fpga_mux (.I0(T0[i]), .I1(T1[i]), .S(B[B_WIDTH-1]), .O(Y[i])); + end + else if (B_WIDTH == 4) begin + localparam a_width0 = 2 ** 3; + localparam num_mux8 = A_WIDTH / a_width0; + localparam a_widthN = A_WIDTH - num_mux8*a_width0; + wire [B_WIDTH-1:0] T; + wire T0, T1; + for (i = 0; i < B_WIDTH; i++) + if (i < num_mux8) + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(B_WIDTH-2), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[(i+1)*a_width0-1:i*a_width0]), .B(B[B_WIDTH-3:0]), .Y(T[i])); + else if (i == num_mux8 && a_widthN > 0) + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i])); + else + assign T[i] = 1'bx; + MUXF7 fpga_mux_0 (.I0(T[0]), .I1(T[1]), .S(B[B_WIDTH-2]), .O(T0)); + MUXF7 fpga_mux_1 (.I0(T[2]), .I1(T[3]), .S(B[B_WIDTH-2]), .O(T1)); + MUXF8 fpga_mux_2 (.I0(T0), .I1(T1), .S(B[B_WIDTH-1]), .O(Y)); + end else begin - localparam a_width0 = Y_WIDTH * 16; + localparam a_width0 = 2 ** 4; localparam num_mux16 = A_WIDTH / a_width0; localparam a_widthN = A_WIDTH - num_mux16*a_width0; - wire [Y_WIDTH * (2 ** ($clog2(NUM)-4))-1:0] T; - for (i = 0; i < 2 ** ($clog2(NUM)-4); i++) + wire [(2**(B_WIDTH-4))-1:0] T; + for (i = 0; i < 2 ** (B_WIDTH-4); i++) if (i < num_mux16) - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH($clog2(a_width0)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[(i+1)*a_width0-1:i*a_width0]), .B(B[$clog2(a_width0)-1:0]), .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH])); + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[(i+1)*a_width0-1:i*a_width0]), .B(B[4-1:0]), .Y(T[i])); else if (i == num_mux16 && a_widthN > 0) begin - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_width0)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_width0)-1:0]), .Y(T[(i+1)*Y_WIDTH-1:i*Y_WIDTH])); + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i])); end else - assign T[(i+1)*Y_WIDTH-1:i*Y_WIDTH] = {Y_WIDTH{1'bx}}; - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(Y_WIDTH * (2 ** ($clog2(NUM)-4))), .B_WIDTH(B_WIDTH-$clog2(a_width0)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(T), .B(B[B_WIDTH-1:$clog2(a_width0)]), .Y(Y)); + assign T[i] = 1'bx; + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(2**(B_WIDTH-4)), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y)); end endgenerate endmodule diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 10902a560..0058f626f 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -118,7 +118,7 @@ struct SynthXilinxPass : public Pass log("\n"); log(" map_cells:\n"); log(" techmap -map +/xilinx/cells_map.v\n"); - log(" clean\n"); + log(" opt -fast\n"); log("\n"); log(" map_luts:\n"); log(" techmap -map +/techmap.v\n"); @@ -258,11 +258,10 @@ struct SynthXilinxPass : public Pass if (check_label(active, run_from, run_to, "fine")) { - Pass::call(design, "opt -fast -full"); + Pass::call(design, "opt -fast"); Pass::call(design, "memory_map"); Pass::call(design, "dffsr2dff"); Pass::call(design, "dff2dffe"); - Pass::call(design, "opt -full"); if (vpr) { Pass::call(design, "techmap -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY"); @@ -282,6 +281,7 @@ struct SynthXilinxPass : public Pass if (check_label(active, run_from, run_to, "map_luts")) { + Pass::call(design, "opt -full"); Pass::call(design, "techmap -map +/techmap.v"); if (abc == "abc9") Pass::call(design, abc + " -lut +/xilinx/cells.lut -box +/xilinx/cells.box" + string(retime ? " -dff" : "")); From bca37796578ee3a259a8327d881d5ac1264c3ac9 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 11 Apr 2019 09:25:19 -0700 Subject: [PATCH 021/213] Fix typo --- techlibs/xilinx/cells_map.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 253678028..8bf0a28b5 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -58,7 +58,7 @@ module \$shiftx (A, B, Y); wire T0, T1; \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[a_width0-1:0]), .B(B[B_WIDTH-2:0]), .Y(T0)); \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1)); - MUXF7 fpga_mux (.I0(T0[i]), .I1(T1[i]), .S(B[B_WIDTH-1]), .O(Y[i])); + MUXF7 fpga_mux (.I0(T0), .I1(T1), .S(B[B_WIDTH-1]), .O(Y)); end else if (B_WIDTH == 4) begin localparam a_width0 = 2 ** 3; From 0ec85640993e0eeb089334efbcd486a254d32786 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 11 Apr 2019 10:04:58 -0700 Subject: [PATCH 022/213] Fix cells_map.v --- techlibs/xilinx/cells_map.v | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 8bf0a28b5..f1ea8f6df 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -41,12 +41,12 @@ module \$shiftx (A, B, Y); wire _TECHMAP_FAIL_ = 1; end else if (Y_WIDTH > 1) begin + wire [$clog2(A_WIDTH/Y_WIDTH)-1:0] B_bitty = B/Y_WIDTH; for (i = 0; i < Y_WIDTH; i++) begin wire [A_WIDTH/Y_WIDTH-1:0] A_i; for (j = 0; j < A_WIDTH/Y_WIDTH; j++) - assign A_i[j] = A[i*Y_WIDTH+j]; - wire [$clog2(A_WIDTH/Y_WIDTH)-1:0] B_i = B/Y_WIDTH; - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH/Y_WIDTH), .B_WIDTH($clog2(A_WIDTH/Y_WIDTH)), .Y_WIDTH(1)) bitblast (.A(A_i), .B(B_i), .Y(Y[i])); + assign A_i[j] = A[j*Y_WIDTH+i]; + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH/Y_WIDTH), .B_WIDTH($clog2(A_WIDTH/Y_WIDTH)), .Y_WIDTH(1)) bitblast (.A(A_i), .B(B_bitty), .Y(Y[i])); end end else if (B_WIDTH < 3) begin @@ -68,9 +68,9 @@ module \$shiftx (A, B, Y); wire T0, T1; for (i = 0; i < B_WIDTH; i++) if (i < num_mux8) - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(B_WIDTH-2), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[(i+1)*a_width0-1:i*a_width0]), .B(B[B_WIDTH-3:0]), .Y(T[i])); + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(B_WIDTH-2), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[i*a_width0+:a_width0]), .B(B[B_WIDTH-3:0]), .Y(T[i])); else if (i == num_mux8 && a_widthN > 0) - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i])); + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i])); else assign T[i] = 1'bx; MUXF7 fpga_mux_0 (.I0(T[0]), .I1(T[1]), .S(B[B_WIDTH-2]), .O(T0)); @@ -84,9 +84,9 @@ module \$shiftx (A, B, Y); wire [(2**(B_WIDTH-4))-1:0] T; for (i = 0; i < 2 ** (B_WIDTH-4); i++) if (i < num_mux16) - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[(i+1)*a_width0-1:i*a_width0]), .B(B[4-1:0]), .Y(T[i])); + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]), .Y(T[i])); else if (i == num_mux16 && a_widthN > 0) begin - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i])); + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i])); end else assign T[i] = 1'bx; From 8658b56a08737cef6040015b192c11da3e6b4eb4 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 11 Apr 2019 10:08:05 -0700 Subject: [PATCH 023/213] More fine tuning --- techlibs/xilinx/cells_map.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index f1ea8f6df..071014d47 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -56,7 +56,7 @@ module \$shiftx (A, B, Y); localparam a_width0 = 2 ** 2; localparam a_widthN = A_WIDTH - a_width0; wire T0, T1; - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[a_width0-1:0]), .B(B[B_WIDTH-2:0]), .Y(T0)); + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[a_width0-1:0]), .B(B[2-1:0]), .Y(T0)); \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1)); MUXF7 fpga_mux (.I0(T0), .I1(T1), .S(B[B_WIDTH-1]), .O(Y)); end @@ -68,7 +68,7 @@ module \$shiftx (A, B, Y); wire T0, T1; for (i = 0; i < B_WIDTH; i++) if (i < num_mux8) - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(B_WIDTH-2), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[i*a_width0+:a_width0]), .B(B[B_WIDTH-3:0]), .Y(T[i])); + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(3), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[i*a_width0+:a_width0]), .B(B[3-1:0]), .Y(T[i])); else if (i == num_mux8 && a_widthN > 0) \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i])); else From 233edf00fec32c8acd7ed442323e0cd515f0e681 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 11 Apr 2019 10:48:14 -0700 Subject: [PATCH 024/213] Fix cells_map.v some more --- techlibs/xilinx/cells_map.v | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 071014d47..2981f89f6 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -61,21 +61,21 @@ module \$shiftx (A, B, Y); MUXF7 fpga_mux (.I0(T0), .I1(T1), .S(B[B_WIDTH-1]), .O(Y)); end else if (B_WIDTH == 4) begin - localparam a_width0 = 2 ** 3; + localparam a_width0 = 2 ** 2; localparam num_mux8 = A_WIDTH / a_width0; localparam a_widthN = A_WIDTH - num_mux8*a_width0; - wire [B_WIDTH-1:0] T; + wire [4-1:0] T; wire T0, T1; - for (i = 0; i < B_WIDTH; i++) + for (i = 0; i < 4; i++) if (i < num_mux8) - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(3), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[i*a_width0+:a_width0]), .B(B[3-1:0]), .Y(T[i])); + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[i*a_width0+:a_width0]), .B(B[2-1:0]), .Y(T[i])); else if (i == num_mux8 && a_widthN > 0) \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i])); else assign T[i] = 1'bx; - MUXF7 fpga_mux_0 (.I0(T[0]), .I1(T[1]), .S(B[B_WIDTH-2]), .O(T0)); - MUXF7 fpga_mux_1 (.I0(T[2]), .I1(T[3]), .S(B[B_WIDTH-2]), .O(T1)); - MUXF8 fpga_mux_2 (.I0(T0), .I1(T1), .S(B[B_WIDTH-1]), .O(Y)); + MUXF7 fpga_mux_0 (.I0(T[0]), .I1(T[1]), .S(B[2]), .O(T0)); + MUXF7 fpga_mux_1 (.I0(T[2]), .I1(T[3]), .S(B[2]), .O(T1)); + MUXF8 fpga_mux_2 (.I0(T0), .I1(T1), .S(B[3]), .O(Y)); end else begin localparam a_width0 = 2 ** 4; From ca8ef92a82897b71c3dbc13ab5ff0cbd28339689 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 12 Apr 2019 10:36:05 -0700 Subject: [PATCH 025/213] PI before CI --- backends/aiger/xaiger.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index bad9322bb..b0770ec96 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -295,12 +295,12 @@ struct XAigerWriter aig_map[State::S0] = 0; aig_map[State::S1] = 1; - for (auto bit : ci_bits) { + for (auto bit : input_bits) { aig_m++, aig_i++; aig_map[bit] = 2*aig_m; } - for (auto bit : input_bits) { + for (auto bit : ci_bits) { aig_m++, aig_i++; aig_map[bit] = 2*aig_m; } From 8fbbd9b129697152c93c35831c1d50982702a3ec Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 15 Apr 2019 22:25:09 -0700 Subject: [PATCH 026/213] Add abc_box_id attribute to MUXF7/F8 cells --- techlibs/xilinx/cells_sim.v | 2 ++ 1 file changed, 2 insertions(+) diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 0c8f282a4..05dd9229f 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -159,10 +159,12 @@ module MUXCY(output O, input CI, DI, S); assign O = S ? CI : DI; endmodule +(* abc_box_id = 1 *) module MUXF7(output O, input I0, I1, S); assign O = S ? I1 : I0; endmodule +(* abc_box_id = 2 *) module MUXF8(output O, input I0, I1, S); assign O = S ? I1 : I0; endmodule From e084240a813b618cea6b5a80d41e2d4516388e44 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 15 Apr 2019 22:25:37 -0700 Subject: [PATCH 027/213] Check abc_box_id attr --- backends/aiger/xaiger.cc | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index d3384e136..eb31bfcef 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -212,6 +212,8 @@ struct XAigerWriter continue; } + bool abc_box = module->design->module(cell->type)->attributes.count("\\abc_box_id"); + for (const auto &c : cell->connections()) { /*if (c.second.is_fully_const()) continue;*/ for (auto b : c.second.bits()) { @@ -224,20 +226,33 @@ struct XAigerWriter if (I != b) alias_map[b] = I; /*if (!output_bits.count(b))*/ + if (abc_box) co_bits.emplace_back(b, 0); + else { + output_bits.insert(b); + if (!b.wire->port_input) + unused_bits.erase(b); + } } } if (is_output) { SigBit O = sigmap(b); /*if (!input_bits.count(O))*/ + if (abc_box) ci_bits.emplace_back(O, 0); + else { + input_bits.insert(O); + if (!O.wire->port_output) + undriven_bits.erase(O); + } } } if (!type_map.count(cell->type)) type_map[cell->type] = type_map.size()+1; } - box_list.emplace_back(cell); + if (abc_box) + box_list.emplace_back(cell); //log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell)); } From 18108e024ae7d3b246aa83e8a9e7ac5327837d0a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 15 Apr 2019 22:27:36 -0700 Subject: [PATCH 028/213] Use abc_box_id --- backends/aiger/xaiger.cc | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index eb31bfcef..841adf8f6 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -571,7 +571,6 @@ struct XAigerWriter write_h_buffer(input_bits.size()); write_h_buffer(num_outputs); write_h_buffer(box_list.size()); - int box_id = 0; for (auto cell : box_list) { int box_inputs = 0, box_outputs = 0; for (const auto &c : cell->connections()) { @@ -582,7 +581,7 @@ struct XAigerWriter } write_h_buffer(box_inputs); write_h_buffer(box_outputs); - write_h_buffer(box_id++); + write_h_buffer(module->design->module(cell->type)->attributes.at("\\abc_box_id").as_int()); write_h_buffer(0 /* OldBoxNum */); } std::string h_buffer_str = h_buffer.str(); From 8c6cf07acff290ab2132c1a7d262bf195fa85b8b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 16 Apr 2019 11:14:59 -0700 Subject: [PATCH 029/213] Revert "Add abc_box_id attribute to MUXF7/F8 cells" This reverts commit 8fbbd9b129697152c93c35831c1d50982702a3ec. --- techlibs/xilinx/cells_sim.v | 2 -- 1 file changed, 2 deletions(-) diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 05dd9229f..0c8f282a4 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -159,12 +159,10 @@ module MUXCY(output O, input CI, DI, S); assign O = S ? CI : DI; endmodule -(* abc_box_id = 1 *) module MUXF7(output O, input I0, I1, S); assign O = S ? I1 : I0; endmodule -(* abc_box_id = 2 *) module MUXF8(output O, input I0, I1, S); assign O = S ? I1 : I0; endmodule From a2b106135b29d1d44255f1b3b6c4173c6e1f3624 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 16 Apr 2019 11:19:42 -0700 Subject: [PATCH 030/213] Do not call abc on modules with abc_box_id attr --- passes/techmap/abc9.cc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index caaff9256..fbf3a47ee 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -1405,6 +1405,9 @@ struct Abc9Pass : public Pass { continue; } + if (mod->attributes.count("\\abc_box_id")) + continue; + assign_map.set(mod); signal_init.clear(); From b89bb744529fc8a5e4cd38522f86a797117f2abc Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 16 Apr 2019 11:19:54 -0700 Subject: [PATCH 031/213] For 'stat' do not count modules with abc_box_id --- passes/cmds/stat.cc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc index 54f4ea817..3909c4c8c 100644 --- a/passes/cmds/stat.cc +++ b/passes/cmds/stat.cc @@ -269,6 +269,9 @@ struct StatPass : public Pass { if (mod->get_bool_attribute("\\top")) top_mod = mod; + if (mod->attributes.count("\\abc_box_id")) + continue; + statdata_t data(design, mod, width_mode, cell_area); mod_stat[mod->name] = data; From 3ac4977b70a373cdabaa72e5f08050f49a3d4046 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 16 Apr 2019 11:21:03 -0700 Subject: [PATCH 032/213] Add +/xilinx/cells_box.v containing models for ABC boxes --- techlibs/xilinx/Makefile.inc | 1 + techlibs/xilinx/cells_box.v | 10 ++++++++++ 2 files changed, 11 insertions(+) create mode 100644 techlibs/xilinx/cells_box.v diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index 432bb0770..43be55d51 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -31,6 +31,7 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells.box)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_box.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells.lut)) $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh)) diff --git a/techlibs/xilinx/cells_box.v b/techlibs/xilinx/cells_box.v new file mode 100644 index 000000000..7805e6306 --- /dev/null +++ b/techlibs/xilinx/cells_box.v @@ -0,0 +1,10 @@ +(* abc_box_id = 1 *) +module MUXF7(output O, input I0, I1, S); + assign O = S ? I1 : I0; +endmodule + +(* abc_box_id = 2 *) +module MUXF8(output O, input I0, I1, S); + assign O = S ? I1 : I0; +endmodule + From d259e6dc14dadf9101116c622569f5b961adde69 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 16 Apr 2019 11:21:46 -0700 Subject: [PATCH 033/213] synth_xilinx: before abc read +/xilinx/cells_box.v --- techlibs/xilinx/synth_xilinx.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 0058f626f..c10e42532 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -283,6 +283,7 @@ struct SynthXilinxPass : public Pass { Pass::call(design, "opt -full"); Pass::call(design, "techmap -map +/techmap.v"); + Pass::call(design, "read_verilog +/xilinx/cells_box.v"); if (abc == "abc9") Pass::call(design, abc + " -lut +/xilinx/cells.lut -box +/xilinx/cells.box" + string(retime ? " -dff" : "")); else From 51896953626ddf7cffdbddfe64e8d85264d968a8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 16 Apr 2019 12:41:56 -0700 Subject: [PATCH 034/213] read_verilog cells_box.v before techmap --- techlibs/xilinx/synth_xilinx.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index c10e42532..d5e9b80c8 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -282,8 +282,8 @@ struct SynthXilinxPass : public Pass if (check_label(active, run_from, run_to, "map_luts")) { Pass::call(design, "opt -full"); - Pass::call(design, "techmap -map +/techmap.v"); Pass::call(design, "read_verilog +/xilinx/cells_box.v"); + Pass::call(design, "techmap -map +/techmap.v"); if (abc == "abc9") Pass::call(design, abc + " -lut +/xilinx/cells.lut -box +/xilinx/cells.box" + string(retime ? " -dff" : "")); else From 53b19ab1f5631bcfc6c3def14f5d44ecc05c1cbc Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 16 Apr 2019 12:43:14 -0700 Subject: [PATCH 035/213] Make cells.box whiteboxes not blackboxes --- techlibs/xilinx/cells.box | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/techlibs/xilinx/cells.box b/techlibs/xilinx/cells.box index c8092db6e..c236d3c90 100644 --- a/techlibs/xilinx/cells.box +++ b/techlibs/xilinx/cells.box @@ -4,10 +4,10 @@ # F7BMUX slower than F7AMUX # Inputs: 0 1 S0 # Outputs: OUT -F7BMUX 1 0 3 1 +F7BMUX 1 1 3 1 217 223 296 # Inputs: 0 1 S0 # Outputs: OUT -MUXF8 2 0 3 1 +MUXF8 2 1 3 1 104 94 273 From 98c297fabfb960beadedaccf7cc9f765f20e044b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 16 Apr 2019 12:44:10 -0700 Subject: [PATCH 036/213] ABC to read_box before reading netlist --- passes/techmap/abc9.cc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index fbf3a47ee..f5f7add9a 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -322,7 +322,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri log_header(design, "Extracting gate netlist of module `%s' to `%s/input.xaig'..\n", module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, show_tempdir).c_str()); - std::string abc_script = stringf("&read %s/input.xaig; &ps ", tempdir_name.c_str()); + std::string abc_script; if (!liberty_file.empty()) { abc_script += stringf("read_lib -w %s; ", liberty_file.c_str()); @@ -343,6 +343,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri else abc_script += stringf("read_library %s/stdcells.genlib; ", tempdir_name.c_str()); + abc_script += stringf("&read %s/input.xaig; &ps ", tempdir_name.c_str()); + if (!script_file.empty()) { if (script_file[0] == '+') { for (size_t i = 1; i < script_file.size(); i++) From f22aa4422dfa6165386b9d2e1e55dafe9b9e5cea Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 16 Apr 2019 12:57:27 -0700 Subject: [PATCH 037/213] WIP for box support --- backends/aiger/xaiger.cc | 129 ++++++++++++++++++++++++++++----------- 1 file changed, 93 insertions(+), 36 deletions(-) diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 841adf8f6..f7c757754 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -212,7 +212,8 @@ struct XAigerWriter continue; } - bool abc_box = module->design->module(cell->type)->attributes.count("\\abc_box_id"); + RTLIL::Module* box_module = module->design->module(cell->type); + bool abc_box = box_module && box_module->attributes.count("\\abc_box_id"); for (const auto &c : cell->connections()) { /*if (c.second.is_fully_const()) continue;*/ @@ -552,48 +553,104 @@ struct XAigerWriter f << "c"; - std::stringstream h_buffer; - auto write_h_buffer = [&h_buffer](int i32) { + if (!box_list.empty()) { + std::stringstream h_buffer; + auto write_h_buffer = [&h_buffer](int i32) { + // TODO: Don't assume we're on little endian +#ifdef _WIN32 + int i32_be = _byteswap_ulong(i32); +#else + int i32_be = __builtin_bswap32(i32); +#endif + h_buffer.write(reinterpret_cast(&i32_be), sizeof(i32_be)); + }; + int num_outputs = output_bits.size(); + if (omode && num_outputs == 0) + num_outputs = 1; + write_h_buffer(1); + write_h_buffer(input_bits.size() + ci_bits.size()); + write_h_buffer(num_outputs + co_bits.size()); + write_h_buffer(input_bits.size()); + write_h_buffer(num_outputs); + write_h_buffer(box_list.size()); + + RTLIL::Module *holes_module = nullptr; + holes_module = module->design->addModule("\\__holes__"); + + for (auto cell : box_list) { + int box_inputs = 0, box_outputs = 0; + int box_id = module->design->module(cell->type)->attributes.at("\\abc_box_id").as_int(); + Cell *holes_cell = nullptr; + if (holes_module && !holes_module->cell(stringf("\\u%d", box_id))) + holes_cell = holes_module->addCell(stringf("\\u%d", box_id), cell->type); + RTLIL::Wire *holes_wire; + int num_inputs = 0; + for (const auto &c : cell->connections()) { + if (cell->input(c.first)) { + box_inputs += c.second.size(); + if (holes_cell) { + holes_wire = holes_module->wire(stringf("\\i%d", num_inputs++)); + if (!holes_wire) { + holes_wire = holes_module->addWire(stringf("\\i%d", num_inputs)); + holes_wire->port_input = true; + } + holes_cell->setPort(c.first, holes_wire); + } + } + if (cell->output(c.first)) { + box_outputs += c.second.size(); + if (holes_cell) { + holes_wire = holes_module->addWire(stringf("\\%s.%s", cell->type.c_str(), c.first.c_str())); + holes_wire->port_output = true; + holes_cell->setPort(c.first, holes_wire); + } + } + } + write_h_buffer(box_inputs); + write_h_buffer(box_outputs); + write_h_buffer(box_id); + write_h_buffer(0 /* OldBoxNum */); + } + + f << "h"; + std::string buffer_str = h_buffer.str(); // TODO: Don't assume we're on little endian #ifdef _WIN32 - int i32_be = _byteswap_ulong(i32); + int buffer_size_be = _byteswap_ulong(buffer_str.size()); #else - int i32_be = __builtin_bswap32(i32); + int buffer_size_be = __builtin_bswap32(buffer_str.size()); #endif - h_buffer.write(reinterpret_cast(&i32_be), sizeof(i32_be)); - }; - int num_outputs = output_bits.size(); - if (omode && num_outputs == 0) - num_outputs = 1; - write_h_buffer(1); - write_h_buffer(input_bits.size() + ci_bits.size()); - write_h_buffer(num_outputs + co_bits.size()); - write_h_buffer(input_bits.size()); - write_h_buffer(num_outputs); - write_h_buffer(box_list.size()); - for (auto cell : box_list) { - int box_inputs = 0, box_outputs = 0; - for (const auto &c : cell->connections()) { - if (cell->input(c.first)) - box_inputs += c.second.size(); - if (cell->output(c.first)) - box_outputs += c.second.size(); - } - write_h_buffer(box_inputs); - write_h_buffer(box_outputs); - write_h_buffer(module->design->module(cell->type)->attributes.at("\\abc_box_id").as_int()); - write_h_buffer(0 /* OldBoxNum */); - } - std::string h_buffer_str = h_buffer.str(); - // TODO: Don't assume we're on little endian + f.write(reinterpret_cast(&buffer_size_be), sizeof(buffer_size_be)); + f.write(buffer_str.data(), buffer_str.size()); + + if (holes_module) { + holes_module->fixup_ports(); + + holes_module->design->selection_stack.emplace_back(false); + RTLIL::Selection& sel = holes_module->design->selection_stack.back(); + sel.select(holes_module); + + Pass::call(holes_module->design, "flatten; aigmap; write_verilog -noexpr -norename holes.v"); + + holes_module->design->selection_stack.pop_back(); + + std::stringstream a_buffer; + XAigerWriter writer(holes_module, false /*zinit_mode*/, false /*imode*/, false /*omode*/, false /*bmode*/); + writer.write_aiger(a_buffer, false /*ascii_mode*/, false /*miter_mode*/, false /*symbols_mode*/, false /*omode*/); + + f << "a"; + std::string buffer_str = a_buffer.str(); + // TODO: Don't assume we're on little endian #ifdef _WIN32 - int h_buffer_size_be = _byteswap_ulong(h_buffer_str.size()); + int buffer_size_be = _byteswap_ulong(buffer_str.size()); #else - int h_buffer_size_be = __builtin_bswap32(h_buffer_str.size()); + int buffer_size_be = __builtin_bswap32(buffer_str.size()); #endif - f << "h"; - f.write(reinterpret_cast(&h_buffer_size_be), sizeof(h_buffer_size_be)); - f.write(h_buffer_str.data(), h_buffer_str.size()); + f.write(reinterpret_cast(&buffer_size_be), sizeof(buffer_size_be)); + f.write(buffer_str.data(), buffer_str.size()); + holes_module->design->remove(holes_module); + } + } f << stringf("Generated by %s\n", yosys_version_str); } From fed1f0ba637941cc0c2c4cc75c08ba7e3994c1a0 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 16 Apr 2019 12:59:48 -0700 Subject: [PATCH 038/213] NULL check before use --- backends/aiger/xaiger.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index f7c757754..875a2ec03 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -231,7 +231,7 @@ struct XAigerWriter co_bits.emplace_back(b, 0); else { output_bits.insert(b); - if (!b.wire->port_input) + if (b.wire && !b.wire->port_input) unused_bits.erase(b); } } From aece97024de574fd765e18e31f685e9ffb0a13c6 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 16 Apr 2019 13:16:20 -0700 Subject: [PATCH 039/213] Fix spacing --- backends/aiger/xaiger.cc | 2 +- techlibs/xilinx/cells.lut | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 875a2ec03..bd7347a19 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -576,7 +576,7 @@ struct XAigerWriter RTLIL::Module *holes_module = nullptr; holes_module = module->design->addModule("\\__holes__"); - + for (auto cell : box_list) { int box_inputs = 0, box_outputs = 0; int box_id = module->design->module(cell->type)->attributes.at("\\abc_box_id").as_int(); diff --git a/techlibs/xilinx/cells.lut b/techlibs/xilinx/cells.lut index a1d9b9c42..c6bc7b1f7 100644 --- a/techlibs/xilinx/cells.lut +++ b/techlibs/xilinx/cells.lut @@ -1,4 +1,4 @@ -# Max delays from https://pastebin.com/v2hrcksd +# Max delays from https://pastebin.com/v2hrcksd # from https://github.com/SymbiFlow/prjxray/pull/706#issuecomment-479380321 # K area delay From 61ca83e099ce9b08b0dcbfaac65a2e2870d58413 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 16 Apr 2019 13:24:54 -0700 Subject: [PATCH 040/213] Remove write_verilog call --- backends/aiger/xaiger.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index bd7347a19..99ca4f8d5 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -630,7 +630,7 @@ struct XAigerWriter RTLIL::Selection& sel = holes_module->design->selection_stack.back(); sel.select(holes_module); - Pass::call(holes_module->design, "flatten; aigmap; write_verilog -noexpr -norename holes.v"); + Pass::call(holes_module->design, "flatten; aigmap"); holes_module->design->selection_stack.pop_back(); From 43cd047fb9d73c43f8fe2c35c457cfa8fc3523ec Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 16 Apr 2019 13:44:15 -0700 Subject: [PATCH 041/213] Do not put constants into output_bits --- backends/aiger/xaiger.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 99ca4f8d5..7c7697874 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -229,9 +229,9 @@ struct XAigerWriter /*if (!output_bits.count(b))*/ if (abc_box) co_bits.emplace_back(b, 0); - else { + else if (b.wire) { output_bits.insert(b); - if (b.wire && !b.wire->port_input) + if (!b.wire->port_input) unused_bits.erase(b); } } From ece5c3ab38023abc251828b9379ea4eca9573abc Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 16 Apr 2019 14:53:01 -0700 Subject: [PATCH 042/213] Fix wire numbering --- backends/aiger/xaiger.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 7c7697874..66ab3878e 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -589,11 +589,12 @@ struct XAigerWriter if (cell->input(c.first)) { box_inputs += c.second.size(); if (holes_cell) { - holes_wire = holes_module->wire(stringf("\\i%d", num_inputs++)); + holes_wire = holes_module->wire(stringf("\\i%d", num_inputs)); if (!holes_wire) { holes_wire = holes_module->addWire(stringf("\\i%d", num_inputs)); holes_wire->port_input = true; } + ++num_inputs; holes_cell->setPort(c.first, holes_wire); } } From cbb85e40e87fbfb1602bb934ed76a97efb9e55c6 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 16 Apr 2019 14:53:28 -0700 Subject: [PATCH 043/213] Add MUXCY and XORCY to cells_box.v --- techlibs/xilinx/cells.box | 6 ++++++ techlibs/xilinx/cells_box.v | 9 +++++++++ 2 files changed, 15 insertions(+) diff --git a/techlibs/xilinx/cells.box b/techlibs/xilinx/cells.box index c236d3c90..5ad284f47 100644 --- a/techlibs/xilinx/cells.box +++ b/techlibs/xilinx/cells.box @@ -11,3 +11,9 @@ F7BMUX 1 1 3 1 # Outputs: OUT MUXF8 2 1 3 1 104 94 273 + +MUXCY 3 1 3 1 +1 1 1 + +XORCY 4 1 2 1 +1 1 diff --git a/techlibs/xilinx/cells_box.v b/techlibs/xilinx/cells_box.v index 7805e6306..ef6f81d27 100644 --- a/techlibs/xilinx/cells_box.v +++ b/techlibs/xilinx/cells_box.v @@ -8,3 +8,12 @@ module MUXF8(output O, input I0, I1, S); assign O = S ? I1 : I0; endmodule +(* abc_box_id = 3 *) +module MUXCY(output O, input CI, DI, S); + assign O = S ? CI : DI; +endmodule + +(* abc_box_id = 4 *) +module XORCY(output O, input CI, LI); + assign O = CI ^ LI; +endmodule From 79fb291dbedbb6cf582925329e8140cbc7e502a9 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 22 Apr 2019 12:14:37 -0700 Subject: [PATCH 044/213] Cleanup, call pmux2shiftx even without -nosrl --- techlibs/xilinx/Makefile.inc | 5 ++--- techlibs/xilinx/{cells.box => abc.box} | 8 ++++---- techlibs/xilinx/{cells.lut => abc.lut} | 0 techlibs/xilinx/cells_box.v | 19 ----------------- techlibs/xilinx/cells_sim.v | 28 +++++++++++++++----------- techlibs/xilinx/synth_xilinx.cc | 15 +++++++------- 6 files changed, 30 insertions(+), 45 deletions(-) rename techlibs/xilinx/{cells.box => abc.box} (79%) rename techlibs/xilinx/{cells.lut => abc.lut} (100%) delete mode 100644 techlibs/xilinx/cells_box.v diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index 43be55d51..296edace9 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -30,9 +30,8 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells.box)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_box.v)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells.lut)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc.box)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc.lut)) $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh)) $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_32.vh)) diff --git a/techlibs/xilinx/cells.box b/techlibs/xilinx/abc.box similarity index 79% rename from techlibs/xilinx/cells.box rename to techlibs/xilinx/abc.box index 5ad284f47..d572817df 100644 --- a/techlibs/xilinx/cells.box +++ b/techlibs/xilinx/abc.box @@ -2,13 +2,13 @@ # from https://github.com/SymbiFlow/prjxray/pull/706#issuecomment-479380321 # F7BMUX slower than F7AMUX -# Inputs: 0 1 S0 -# Outputs: OUT +# Inputs: I0 I1 S0 +# Outputs: O F7BMUX 1 1 3 1 217 223 296 -# Inputs: 0 1 S0 -# Outputs: OUT +# Inputs: I0 I1 S0 +# Outputs: O MUXF8 2 1 3 1 104 94 273 diff --git a/techlibs/xilinx/cells.lut b/techlibs/xilinx/abc.lut similarity index 100% rename from techlibs/xilinx/cells.lut rename to techlibs/xilinx/abc.lut diff --git a/techlibs/xilinx/cells_box.v b/techlibs/xilinx/cells_box.v deleted file mode 100644 index ef6f81d27..000000000 --- a/techlibs/xilinx/cells_box.v +++ /dev/null @@ -1,19 +0,0 @@ -(* abc_box_id = 1 *) -module MUXF7(output O, input I0, I1, S); - assign O = S ? I1 : I0; -endmodule - -(* abc_box_id = 2 *) -module MUXF8(output O, input I0, I1, S); - assign O = S ? I1 : I0; -endmodule - -(* abc_box_id = 3 *) -module MUXCY(output O, input CI, DI, S); - assign O = S ? CI : DI; -endmodule - -(* abc_box_id = 4 *) -module XORCY(output O, input CI, LI); - assign O = CI ^ LI; -endmodule diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 3a4540b83..8b231480f 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -155,18 +155,22 @@ module LUT6_2(output O6, output O5, input I0, I1, I2, I3, I4, I5); assign O5 = I0 ? s5_1[1] : s5_1[0]; endmodule +(* abc_box_id = 3, lib_whitebox *) module MUXCY(output O, input CI, DI, S); assign O = S ? CI : DI; endmodule +(* abc_box_id = 1, lib_whitebox *) module MUXF7(output O, input I0, I1, S); assign O = S ? I1 : I0; endmodule +(* abc_box_id = 2, lib_whitebox *) module MUXF8(output O, input I0, I1, S); assign O = S ? I1 : I0; endmodule +(* abc_box_id = 4, lib_whitebox *) module XORCY(output O, input CI, LI); assign O = CI ^ LI; endmodule @@ -202,7 +206,7 @@ endmodule `endif -module FDRE (output reg Q, input C, CE, D, R); +module FDRE ((* abc_flop_q *) output reg Q, input C, CE, input D, R); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; @@ -214,7 +218,7 @@ module FDRE (output reg Q, input C, CE, D, R); endcase endgenerate endmodule -module FDSE (output reg Q, input C, CE, D, S); +module FDSE ((* abc_flop_q *) output reg Q, input C, CE, D, S); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; @@ -226,7 +230,7 @@ module FDSE (output reg Q, input C, CE, D, S); endcase endgenerate endmodule -module FDCE (output reg Q, input C, CE, D, CLR); +module FDCE ((* abc_flop_q *) output reg Q, input C, CE, D, CLR); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; @@ -240,7 +244,7 @@ module FDCE (output reg Q, input C, CE, D, CLR); endcase endgenerate endmodule -module FDPE (output reg Q, input C, CE, D, PRE); +module FDPE ((* abc_flop_q *) output reg Q, input C, CE, D, PRE); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; @@ -254,32 +258,32 @@ module FDPE (output reg Q, input C, CE, D, PRE); endcase endgenerate endmodule -module FDRE_1 (output reg Q, input C, CE, D, R); +module FDRE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; initial Q <= INIT; always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D; endmodule -module FDSE_1 (output reg Q, input C, CE, D, S); +module FDSE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, S); parameter [0:0] INIT = 1'b1; initial Q <= INIT; always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D; endmodule -module FDCE_1 (output reg Q, input C, CE, D, CLR); +module FDCE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, CLR); parameter [0:0] INIT = 1'b0; initial Q <= INIT; always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D; endmodule -module FDPE_1 (output reg Q, input C, CE, D, PRE); +module FDPE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, PRE); parameter [0:0] INIT = 1'b1; initial Q <= INIT; always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; endmodule module RAM64X1D ( - output DPO, SPO, + (* abc_flop_q *) output DPO, SPO, input D, WCLK, WE, input A0, A1, A2, A3, A4, A5, input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5 @@ -296,7 +300,7 @@ module RAM64X1D ( endmodule module RAM128X1D ( - output DPO, SPO, + (* abc_flop_q *) output DPO, SPO, input D, WCLK, WE, input [6:0] A, DPRA ); @@ -310,7 +314,7 @@ module RAM128X1D ( endmodule module SRL16E ( - output Q, + (* abc_flop_q *) output Q, input A0, A1, A2, A3, CE, CLK, D ); parameter [15:0] INIT = 16'h0000; @@ -328,7 +332,7 @@ module SRL16E ( endmodule module SRLC32E ( - output Q, + (* abc_flop_q *) output Q, output Q31, input [4:0] A, input CE, CLK, D diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index fa87a3ad6..5de2803e9 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -119,8 +119,8 @@ struct SynthXilinxPass : public Pass log(" opt -fast\n"); log("\n"); log(" map_cells:\n"); + log(" pmux2shiftx\n"); log(" simplemap t:$dff t:$dffe (without '-nosrl' only)\n"); - log(" pmux2shiftx (without '-nosrl' only)\n"); log(" opt_expr -mux_undef (without '-nosrl' only)\n"); log(" shregmap -tech xilinx -minlen 3 (without '-nosrl' only)\n"); log(" techmap -map +/xilinx/cells_map.v\n"); @@ -288,14 +288,16 @@ struct SynthXilinxPass : public Pass if (check_label(active, run_from, run_to, "map_cells")) { + // shregmap -tech xilinx can cope with $shiftx and $mux + // cells for identifying variable-length shift registers, + // so attempt to convert $pmux-es to the former + // Also: wide multiplexers inference benefits from this too + Pass::call(design, "pmux2shiftx"); + if (!nosrl) { // shregmap operates on bit-level flops, not word-level, // so break those down here Pass::call(design, "simplemap t:$dff t:$dffe"); - // shregmap -tech xilinx can cope with $shiftx and $mux - // cells for identifiying variable-length shift registers, - // so attempt to convert $pmux-es to the former - Pass::call(design, "pmux2shiftx"); // pmux2shiftx can leave behind a $pmux with a single entry // -- need this to clean that up before shregmap Pass::call(design, "opt_expr -mux_undef"); @@ -311,9 +313,8 @@ struct SynthXilinxPass : public Pass { Pass::call(design, "opt -full"); Pass::call(design, "techmap -map +/techmap.v -D _NO_POS_SR -map +/xilinx/ff_map.v"); - Pass::call(design, "read_verilog +/xilinx/cells_box.v"); if (abc == "abc9") - Pass::call(design, abc + " -lut +/xilinx/cells.lut -box +/xilinx/cells.box" + string(retime ? " -dff" : "")); + Pass::call(design, abc + " -lut +/xilinx/abc.lut -box +/xilinx/abc.box" + string(retime ? " -dff" : "")); else Pass::call(design, abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : "")); Pass::call(design, "clean"); From 75b96b1afff6062c936624c8d7ac19970299cd34 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 22 Apr 2019 12:36:15 -0700 Subject: [PATCH 045/213] Add synth_xilinx -nomux option --- techlibs/xilinx/cells_map.v | 2 ++ techlibs/xilinx/synth_xilinx.cc | 20 ++++++++++++++++---- 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 3c4d8f4cd..e71d4bafb 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -142,6 +142,7 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o endgenerate endmodule +`ifndef NO_MUXFN module \$shiftx (A, B, Y); parameter A_SIGNED = 0; parameter B_SIGNED = 0; @@ -219,3 +220,4 @@ module \$shiftx (A, B, Y); end endgenerate endmodule +`endif // NO_MUXFN diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 5de2803e9..04b0dabca 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -72,6 +72,9 @@ struct SynthXilinxPass : public Pass log(" -nosrl\n"); log(" disable inference of shift registers\n"); log("\n"); + log(" -nomux\n"); + log(" disable inference of wide multiplexers\n"); + log("\n"); log(" -run :\n"); log(" only run the commands between the labels (see below). an empty\n"); log(" from label is synonymous to 'begin', and empty to label is\n"); @@ -119,7 +122,7 @@ struct SynthXilinxPass : public Pass log(" opt -fast\n"); log("\n"); log(" map_cells:\n"); - log(" pmux2shiftx\n"); + log(" pmux2shiftx (without '-nosrl' and '-nomux' only)\n"); log(" simplemap t:$dff t:$dffe (without '-nosrl' only)\n"); log(" opt_expr -mux_undef (without '-nosrl' only)\n"); log(" shregmap -tech xilinx -minlen 3 (without '-nosrl' only)\n"); @@ -161,6 +164,7 @@ struct SynthXilinxPass : public Pass bool nobram = false; bool nodram = false; bool nosrl = false; + bool nomux = false; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) @@ -209,6 +213,10 @@ struct SynthXilinxPass : public Pass nosrl = true; continue; } + if (args[argidx] == "-nomux") { + nomux = true; + continue; + } if (args[argidx] == "-abc9") { abc = "abc9"; continue; @@ -291,8 +299,9 @@ struct SynthXilinxPass : public Pass // shregmap -tech xilinx can cope with $shiftx and $mux // cells for identifying variable-length shift registers, // so attempt to convert $pmux-es to the former - // Also: wide multiplexers inference benefits from this too - Pass::call(design, "pmux2shiftx"); + // Also: wide multiplexer inference benefits from this too + if (!nosrl || !nomux) + Pass::call(design, "pmux2shiftx"); if (!nosrl) { // shregmap operates on bit-level flops, not word-level, @@ -305,7 +314,10 @@ struct SynthXilinxPass : public Pass Pass::call(design, "shregmap -tech xilinx -minlen 3"); } - Pass::call(design, "techmap -map +/xilinx/cells_map.v"); + std::string define; + if (nomux) + define += " -D NO_MUXFN"; + Pass::call(design, "techmap" + define + " -map +/xilinx/cells_map.v"); Pass::call(design, "clean"); } From ac1e13819e9241eea0e047ecf396f3f4cd822a5b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 22 Apr 2019 14:26:13 -0700 Subject: [PATCH 046/213] Fix for non-pow2 width muxes --- techlibs/xilinx/cells_map.v | 27 ++++++++++++++++++--------- 1 file changed, 18 insertions(+), 9 deletions(-) diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index e71d4bafb..87a14c961 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -78,7 +78,7 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o end else if (DEPTH > 65 && DEPTH <= 96) begin wire T0, T1, T2, T3, T4, T5, T6; - SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1)); + SRLC32E #(.INIT(INIT_R[32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1)); SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3)); \$__XILINX_SHREG_ #(.DEPTH(DEPTH-64), .INIT(INIT[DEPTH-64-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_2 (.C(C), .D(T3), .L(L[4:0]), .E(E), .Q(T4)); if (&_TECHMAP_CONSTMSK_L_) @@ -91,7 +91,7 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o end else if (DEPTH > 97 && DEPTH < 128) begin wire T0, T1, T2, T3, T4, T5, T6, T7, T8; - SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1)); + SRLC32E #(.INIT(INIT_R[32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1)); SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3)); SRLC32E #(.INIT(INIT_R[96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5)); \$__XILINX_SHREG_ #(.DEPTH(DEPTH-96), .INIT(INIT[DEPTH-96-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_3 (.C(C), .D(T5), .L(L[4:0]), .E(E), .Q(T6)); @@ -105,9 +105,9 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o end else if (DEPTH == 128) begin wire T0, T1, T2, T3, T4, T5, T6; - SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1)); - SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3)); - SRLC32E #(.INIT(INIT_R[96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5)); + SRLC32E #(.INIT(INIT_R[ 32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1)); + SRLC32E #(.INIT(INIT_R[ 64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3)); + SRLC32E #(.INIT(INIT_R[ 96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5)); SRLC32E #(.INIT(INIT_R[128-1:96]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_3 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T5), .Q(T6), .Q31(SO)); if (&_TECHMAP_CONSTMSK_L_) assign Q = T6; @@ -157,6 +157,15 @@ module \$shiftx (A, B, Y); parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0; parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0; + function integer first_B_nonzero; + integer i; + begin + for (i = B_WIDTH-1; i >= 0; i--) + if (_TECHMAP_CONSTMSK_B_[i] == 1'b0 || _TECHMAP_CONSTVAL_B_ != 1'b0) + first_B_nonzero = i; + end + endfunction + generate genvar i, j; if (B_SIGNED) begin @@ -167,12 +176,12 @@ module \$shiftx (A, B, Y); wire _TECHMAP_FAIL_ = 1; end else if (Y_WIDTH > 1) begin - wire [$clog2(A_WIDTH/Y_WIDTH)-1:0] B_bitty = B/Y_WIDTH; + localparam inc = first_B_nonzero(); for (i = 0; i < Y_WIDTH; i++) begin wire [A_WIDTH/Y_WIDTH-1:0] A_i; - for (j = 0; j < A_WIDTH/Y_WIDTH; j++) - assign A_i[j] = A[j*Y_WIDTH+i]; - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH/Y_WIDTH), .B_WIDTH($clog2(A_WIDTH/Y_WIDTH)), .Y_WIDTH(1)) bitblast (.A(A_i), .B(B_bitty), .Y(Y[i])); + for (j = 0; j*(1< Date: Mon, 22 Apr 2019 16:56:18 -0700 Subject: [PATCH 047/213] Fix for mux_case_* mappings --- techlibs/xilinx/cells_map.v | 26 +++++++++----------------- 1 file changed, 9 insertions(+), 17 deletions(-) diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 87a14c961..1def7b973 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -157,32 +157,24 @@ module \$shiftx (A, B, Y); parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0; parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0; - function integer first_B_nonzero; - integer i; - begin - for (i = B_WIDTH-1; i >= 0; i--) - if (_TECHMAP_CONSTMSK_B_[i] == 1'b0 || _TECHMAP_CONSTVAL_B_ != 1'b0) - first_B_nonzero = i; - end - endfunction - generate genvar i, j; if (B_SIGNED) begin if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && _TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0) // Optimisation to remove B_SIGNED if sign bit of B is constant-0 - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B[B_WIDTH-2:0]), .Y(Y)); + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B[B_WIDTH-2:0]), .Y(Y)); else wire _TECHMAP_FAIL_ = 1; end else if (Y_WIDTH > 1) begin - localparam inc = first_B_nonzero(); - for (i = 0; i < Y_WIDTH; i++) begin - wire [A_WIDTH/Y_WIDTH-1:0] A_i; - for (j = 0; j*(1< Date: Mon, 22 Apr 2019 16:58:44 -0700 Subject: [PATCH 048/213] Add comment --- techlibs/xilinx/cells_map.v | 3 +++ 1 file changed, 3 insertions(+) diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 1def7b973..38c8a49e7 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -170,6 +170,9 @@ module \$shiftx (A, B, Y); for (i = 0; i < Y_WIDTH; i++) \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A({{i{1'bx}}, A[A_WIDTH-1:i]}), .B(B), .Y(Y[i])); end + // If the LSB of B is constant zero (and Y_WIDTH is 1) then + // we can optimise by removing every other entry from A + // and popping the constant zero from B else if (_TECHMAP_CONSTMSK_B_[0] && !_TECHMAP_CONSTVAL_B_[0]) begin wire [(A_WIDTH+1)/2-1:0] A_i; for (i = 0; i < (A_WIDTH+1)/2; i++) From 1fa2c36fbd98ff8d748a70c4cb352fa1c6070dae Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 22 Apr 2019 17:14:11 -0700 Subject: [PATCH 049/213] Trim A_WIDTH by Y_WIDTH-1 --- techlibs/xilinx/cells_map.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 38c8a49e7..60bc08b48 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -168,7 +168,7 @@ module \$shiftx (A, B, Y); end else if (Y_WIDTH > 1) begin for (i = 0; i < Y_WIDTH; i++) - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A({{i{1'bx}}, A[A_WIDTH-1:i]}), .B(B), .Y(Y[i])); + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-Y_WIDTH+1), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A(A[A_WIDTH-Y_WIDTH+i:i]), .B(B), .Y(Y[i])); end // If the LSB of B is constant zero (and Y_WIDTH is 1) then // we can optimise by removing every other entry from A From 26e461f47da12b79e5b6682f692d81e2721ca0c0 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 22 Apr 2019 17:58:28 -0700 Subject: [PATCH 050/213] Fix for A_WIDTH == 2 but B_WIDTH==3 --- techlibs/xilinx/cells_map.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 60bc08b48..10dbb8b9a 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -179,7 +179,7 @@ module \$shiftx (A, B, Y); assign A_i[i] = A[i*2]; \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y)); end - else if (B_WIDTH < 3) begin + else if (B_WIDTH < 3 || A_WIDTH == 2**2) begin wire _TECHMAP_FAIL_ = 1; end else if (B_WIDTH == 3) begin From 60026842b20e04affe60a7871fd14bb544add37b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 22 Apr 2019 17:59:56 -0700 Subject: [PATCH 051/213] Tweak --- techlibs/xilinx/cells_map.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 10dbb8b9a..4275c03e6 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -179,7 +179,7 @@ module \$shiftx (A, B, Y); assign A_i[i] = A[i*2]; \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y)); end - else if (B_WIDTH < 3 || A_WIDTH == 2**2) begin + else if (B_WIDTH < 3 || A_WIDTH <= 4) begin wire _TECHMAP_FAIL_ = 1; end else if (B_WIDTH == 3) begin From 9d122d3c51575fe6803729e8f953141edb3b12c3 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 23 Apr 2019 15:06:19 -0700 Subject: [PATCH 052/213] Refactor into AigerReader::post_process() --- frontends/aiger/aigerparse.cc | 409 +++++++++++++--------------------- frontends/aiger/aigerparse.h | 1 + 2 files changed, 161 insertions(+), 249 deletions(-) diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 3fa6f5c2d..8b3fa6536 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -113,103 +113,7 @@ void AigerReader::parse_aiger() std::getline(f, line); // Ignore up to start of next line } - dict wideports_cache; - - if (!map_filename.empty()) { - std::ifstream mf(map_filename); - std::string type, symbol; - int variable, index; - while (mf >> type >> variable >> index >> symbol) { - RTLIL::IdString escaped_symbol = RTLIL::escape_id(symbol); - if (type == "input") { - log_assert(static_cast(variable) < inputs.size()); - RTLIL::Wire* wire = inputs[variable]; - log_assert(wire); - log_assert(wire->port_input); - - if (index == 0) - module->rename(wire, RTLIL::escape_id(symbol)); - else if (index > 0) { - module->rename(wire, RTLIL::escape_id(stringf("%s[%d]", symbol.c_str(), index))); - if (wideports) - wideports_cache[escaped_symbol] = std::max(wideports_cache[escaped_symbol], index); - } - } - else if (type == "output") { - log_assert(static_cast(variable) < outputs.size()); - RTLIL::Wire* wire = outputs[variable]; - log_assert(wire); - // Ignore direct output -> input connections - if (!wire->port_output) - continue; - log_assert(wire->port_output); - - if (index == 0) - module->rename(wire, RTLIL::escape_id(symbol)); - else if (index > 0) { - module->rename(wire, RTLIL::escape_id(stringf("%s[%d]", symbol.c_str(), index))); - if (wideports) - wideports_cache[escaped_symbol] = std::max(wideports_cache[escaped_symbol], index); - } - } - else - log_error("Symbol type '%s' not recognised.\n", type.c_str()); - } - } - - for (auto &wp : wideports_cache) { - auto name = wp.first; - int width = wp.second + 1; - - RTLIL::Wire *wire = module->wire(name); - if (wire) - module->rename(wire, RTLIL::escape_id(stringf("%s[%d]", name.c_str(), 0))); - - // Do not make ports with a mix of input/output into - // wide ports - bool port_input = false, port_output = false; - for (int i = 0; i < width; i++) { - RTLIL::IdString other_name = name.str() + stringf("[%d]", i); - RTLIL::Wire *other_wire = module->wire(other_name); - if (other_wire) { - port_input = port_input || other_wire->port_input; - port_output = port_output || other_wire->port_output; - } - } - if ((port_input && port_output) || (!port_input && !port_output)) - continue; - - wire = module->addWire(name, width); - wire->port_input = port_input; - wire->port_output = port_output; - - for (int i = 0; i < width; i++) { - RTLIL::IdString other_name = name.str() + stringf("[%d]", i); - RTLIL::Wire *other_wire = module->wire(other_name); - if (other_wire) { - other_wire->port_input = false; - other_wire->port_output = false; - if (wire->port_input) - module->connect(other_wire, SigSpec(wire, i)); - else - module->connect(SigSpec(wire, i), other_wire); - } - } - } - - module->fixup_ports(); - design->add(module); - - Pass::call(design, "clean"); - - for (auto cell : module->cells().to_vector()) { - if (cell->type != "$lut") continue; - auto y_port = cell->getPort("\\Y").as_bit(); - if (y_port.wire->width == 1) - module->rename(cell, stringf("%s$lut", y_port.wire->name.c_str())); - else - module->rename(cell, stringf("%s[%d]$lut", y_port.wire->name.c_str(), y_port.offset)); - } + post_process(); } static uint32_t parse_xaiger_literal(std::istream &f) @@ -438,158 +342,7 @@ next_line: module->connect(wire, out_wire); } - if (!map_filename.empty()) { - std::ifstream mf(map_filename); - std::string type, symbol; - int variable, index; - while (mf >> type >> variable >> index >> symbol) { - RTLIL::IdString escaped_s = RTLIL::escape_id(symbol); - if (type == "input") { - log_assert(static_cast(variable) < inputs.size()); - RTLIL::Wire* wire = inputs[variable]; - log_assert(wire); - log_assert(wire->port_input); - - if (index == 0) { - // Cope with the fact that a CI might be identical - // to a PI (necessary due to ABC); in those cases - // simply connect the latter to the former - RTLIL::Wire* existing = module->wire(escaped_s); - if (!existing) - module->rename(wire, escaped_s); - else { - wire->port_input = false; - module->connect(wire, existing); - } - } - else if (index > 0) { - std::string indexed_name = stringf("%s[%d]", escaped_s.c_str(), index); - RTLIL::Wire* existing = module->wire(indexed_name); - if (!existing) { - module->rename(wire, indexed_name); - if (wideports) - wideports_cache[escaped_s] = std::max(wideports_cache[escaped_s], index); - } - else { - module->connect(wire, existing); - wire->port_input = false; - } - } - } - else if (type == "output") { - log_assert(static_cast(variable) < outputs.size()); - RTLIL::Wire* wire = outputs[variable]; - log_assert(wire); - log_assert(wire->port_output); - if (escaped_s.in("\\__dummy_o__", "\\__const0__", "\\__const1__")) { - wire->port_output = false; - continue; - } - - if (index == 0) { - // Cope with the fact that a CO might be identical - // to a PO (necessary due to ABC); in those cases - // simply connect the latter to the former - RTLIL::Wire* existing = module->wire(escaped_s); - if (!existing) { - if (escaped_s.ends_with("$inout.out")) { - wire->port_output = false; - RTLIL::Wire *in_wire = module->wire(escaped_s.substr(0, escaped_s.size()-10)); - log_assert(in_wire); - log_assert(in_wire->port_input && !in_wire->port_output); - in_wire->port_output = true; - module->connect(in_wire, wire); - } - else - module->rename(wire, escaped_s); - } - else { - wire->port_output = false; - module->connect(wire, existing); - } - } - else if (index > 0) { - std::string indexed_name = stringf("%s[%d]", escaped_s.c_str(), index); - RTLIL::Wire* existing = module->wire(indexed_name); - if (!existing) { - if (escaped_s.ends_with("$inout.out")) { - wire->port_output = false; - RTLIL::Wire *in_wire = module->wire(stringf("%s[%d]", escaped_s.substr(0, escaped_s.size()-10).c_str(), index)); - log_assert(in_wire); - log_assert(in_wire->port_input && !in_wire->port_output); - in_wire->port_output = true; - module->connect(in_wire, wire); - } - else { - module->rename(wire, indexed_name); - if (wideports) - wideports_cache[escaped_s] = std::max(wideports_cache[escaped_s], index); - } - } - else { - module->connect(wire, existing); - wire->port_output = false; - } - } - } - else - log_error("Symbol type '%s' not recognised.\n", type.c_str()); - } - } - - for (auto &wp : wideports_cache) { - auto name = wp.first; - int width = wp.second + 1; - - RTLIL::Wire *wire = module->wire(name); - if (wire) - module->rename(wire, RTLIL::escape_id(stringf("%s[%d]", name.c_str(), 0))); - - // Do not make ports with a mix of input/output into - // wide ports - bool port_input = false, port_output = false; - for (int i = 0; i < width; i++) { - RTLIL::IdString other_name = name.str() + stringf("[%d]", i); - RTLIL::Wire *other_wire = module->wire(other_name); - if (other_wire) { - port_input = port_input || other_wire->port_input; - port_output = port_output || other_wire->port_output; - } - } - if ((port_input && port_output) || (!port_input && !port_output)) - continue; - - wire = module->addWire(name, width); - wire->port_input = port_input; - wire->port_output = port_output; - - for (int i = 0; i < width; i++) { - RTLIL::IdString other_name = name.str() + stringf("[%d]", i); - RTLIL::Wire *other_wire = module->wire(other_name); - if (other_wire) { - other_wire->port_input = false; - other_wire->port_output = false; - if (wire->port_input) - module->connect(other_wire, SigSpec(wire, i)); - else - module->connect(SigSpec(wire, i), other_wire); - } - } - } - - module->fixup_ports(); - design->add(module); - - Pass::call(design, "clean"); - - for (auto cell : module->cells().to_vector()) { - if (cell->type != "$lut") continue; - auto y_port = cell->getPort("\\Y").as_bit(); - if (y_port.wire->width == 1) - module->rename(cell, stringf("%s$lut", y_port.wire->name.c_str())); - else - module->rename(cell, stringf("%s[%d]$lut", y_port.wire->name.c_str(), y_port.offset)); - } + post_process(); } void AigerReader::parse_aiger_ascii() @@ -849,6 +602,164 @@ void AigerReader::parse_aiger_binary() } } +void AigerReader::post_process() +{ + dict wideports_cache; + + if (!map_filename.empty()) { + std::ifstream mf(map_filename); + std::string type, symbol; + int variable, index; + while (mf >> type >> variable >> index >> symbol) { + RTLIL::IdString escaped_s = RTLIL::escape_id(symbol); + if (type == "input") { + log_assert(static_cast(variable) < inputs.size()); + RTLIL::Wire* wire = inputs[variable]; + log_assert(wire); + log_assert(wire->port_input); + + if (index == 0) { + // Cope with the fact that a CI might be identical + // to a PI (necessary due to ABC); in those cases + // simply connect the latter to the former + RTLIL::Wire* existing = module->wire(escaped_s); + if (!existing) + module->rename(wire, escaped_s); + else { + wire->port_input = false; + module->connect(wire, existing); + } + } + else if (index > 0) { + std::string indexed_name = stringf("%s[%d]", escaped_s.c_str(), index); + RTLIL::Wire* existing = module->wire(indexed_name); + if (!existing) { + module->rename(wire, indexed_name); + if (wideports) + wideports_cache[escaped_s] = std::max(wideports_cache[escaped_s], index); + } + else { + module->connect(wire, existing); + wire->port_input = false; + } + } + } + else if (type == "output") { + log_assert(static_cast(variable) < outputs.size()); + RTLIL::Wire* wire = outputs[variable]; + log_assert(wire); + log_assert(wire->port_output); + if (escaped_s.in("\\__dummy_o__", "\\__const0__", "\\__const1__")) { + wire->port_output = false; + continue; + } + + if (index == 0) { + // Cope with the fact that a CO might be identical + // to a PO (necessary due to ABC); in those cases + // simply connect the latter to the former + RTLIL::Wire* existing = module->wire(escaped_s); + if (!existing) { + if (escaped_s.ends_with("$inout.out")) { + wire->port_output = false; + RTLIL::Wire *in_wire = module->wire(escaped_s.substr(0, escaped_s.size()-10)); + log_assert(in_wire); + log_assert(in_wire->port_input && !in_wire->port_output); + in_wire->port_output = true; + module->connect(in_wire, wire); + } + else + module->rename(wire, escaped_s); + } + else { + wire->port_output = false; + module->connect(wire, existing); + } + } + else if (index > 0) { + std::string indexed_name = stringf("%s[%d]", escaped_s.c_str(), index); + RTLIL::Wire* existing = module->wire(indexed_name); + if (!existing) { + if (escaped_s.ends_with("$inout.out")) { + wire->port_output = false; + RTLIL::Wire *in_wire = module->wire(stringf("%s[%d]", escaped_s.substr(0, escaped_s.size()-10).c_str(), index)); + log_assert(in_wire); + log_assert(in_wire->port_input && !in_wire->port_output); + in_wire->port_output = true; + module->connect(in_wire, wire); + } + else { + module->rename(wire, indexed_name); + if (wideports) + wideports_cache[escaped_s] = std::max(wideports_cache[escaped_s], index); + } + } + else { + module->connect(wire, existing); + wire->port_output = false; + } + } + } + else + log_error("Symbol type '%s' not recognised.\n", type.c_str()); + } + } + + for (auto &wp : wideports_cache) { + auto name = wp.first; + int width = wp.second + 1; + + RTLIL::Wire *wire = module->wire(name); + if (wire) + module->rename(wire, RTLIL::escape_id(stringf("%s[%d]", name.c_str(), 0))); + + // Do not make ports with a mix of input/output into + // wide ports + bool port_input = false, port_output = false; + for (int i = 0; i < width; i++) { + RTLIL::IdString other_name = name.str() + stringf("[%d]", i); + RTLIL::Wire *other_wire = module->wire(other_name); + if (other_wire) { + port_input = port_input || other_wire->port_input; + port_output = port_output || other_wire->port_output; + } + } + if ((port_input && port_output) || (!port_input && !port_output)) + continue; + + wire = module->addWire(name, width); + wire->port_input = port_input; + wire->port_output = port_output; + + for (int i = 0; i < width; i++) { + RTLIL::IdString other_name = name.str() + stringf("[%d]", i); + RTLIL::Wire *other_wire = module->wire(other_name); + if (other_wire) { + other_wire->port_input = false; + other_wire->port_output = false; + if (wire->port_input) + module->connect(other_wire, SigSpec(wire, i)); + else + module->connect(SigSpec(wire, i), other_wire); + } + } + } + + module->fixup_ports(); + design->add(module); + + Pass::call(design, "clean"); + + for (auto cell : module->cells().to_vector()) { + if (cell->type != "$lut") continue; + auto y_port = cell->getPort("\\Y").as_bit(); + if (y_port.wire->width == 1) + module->rename(cell, stringf("%s$lut", y_port.wire->name.c_str())); + else + module->rename(cell, stringf("%s[%d]$lut", y_port.wire->name.c_str(), y_port.offset)); + } +} + struct AigerFrontend : public Frontend { AigerFrontend() : Frontend("aiger", "read AIGER file") { } void help() YS_OVERRIDE diff --git a/frontends/aiger/aigerparse.h b/frontends/aiger/aigerparse.h index 39757545f..8c9f3a0c9 100644 --- a/frontends/aiger/aigerparse.h +++ b/frontends/aiger/aigerparse.h @@ -47,6 +47,7 @@ struct AigerReader void parse_xaiger(); void parse_aiger_ascii(); void parse_aiger_binary(); + void post_process(); }; YOSYS_NAMESPACE_END From bfd71e09906096c72039beebb1b3b6a79dd6b36c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 23 Apr 2019 16:11:14 -0700 Subject: [PATCH 053/213] Fix abc9 with (* keep *) wires --- backends/aiger/xaiger.cc | 20 ++++++++++++++------ tests/simple_abc9/abc9.v | 38 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 52 insertions(+), 6 deletions(-) diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index d6438a297..504a66086 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -133,6 +133,8 @@ struct XAigerWriter init_map[initsig[i]] = initval[i] == State::S1; } + bool keep = wire->attributes.count("\\keep"); + for (int i = 0; i < GetSize(wire); i++) { SigBit wirebit(wire, i); @@ -151,8 +153,10 @@ struct XAigerWriter if (wire->port_input) input_bits.insert(bit); + else if (keep) + input_bits.insert(wirebit); - if (wire->port_output) { + if (wire->port_output || keep) { if (bit != wirebit) alias_map[wirebit] = bit; output_bits.insert(wirebit); @@ -338,10 +342,12 @@ struct XAigerWriter for (auto bit : input_bits) { RTLIL::Wire *wire = bit.wire; - // If encountering an inout port, then create a new wire with $inout.out - // suffix, make it a PO driven by the existing inout, and inherit existing - // inout's drivers - if (wire->port_input && wire->port_output && !undriven_bits.count(bit)) { + // If encountering an inout port, or a keep-ed wire, then create a new wire + // with $inout.out suffix, make it a PO driven by the existing inout, and + // inherit existing inout's drivers + if ((wire->port_input && wire->port_output && !undriven_bits.count(bit)) + || wire->attributes.count("\\keep")) { + log_assert(input_bits.count(bit) && output_bits.count(bit)); RTLIL::Wire *new_wire = module->wire(wire->name.str() + "$inout.out"); if (!new_wire) new_wire = module->addWire(wire->name.str() + "$inout.out", GetSize(wire)); @@ -354,7 +360,9 @@ struct XAigerWriter else if (alias_map.count(bit)) alias_map[new_bit] = alias_map.at(bit); else + //log_abort(); alias_map[new_bit] = bit; + output_bits.erase(bit); output_bits.insert(new_bit); } } @@ -750,7 +758,7 @@ struct XAigerWriter { RTLIL::SigBit b(wire, i); if (input_bits.count(b)) { - int a = aig_map.at(sig[i]); + int a = aig_map.at(b); log_assert((a & 1) == 0); input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire)); } diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index eca340693..f37d975ff 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -104,3 +104,41 @@ always @(io or oe) assign io[3:0] = oe ? ~latch[3:0] : 4'bz; assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz; endmodule + +module abc9_test015(input a, output b, input c); +assign b = ~a; +(* keep *) wire d; +assign d = ~c; +endmodule + +module abc9_test016(input a, output b); +assign b = ~a; +(* keep *) reg c; +always @* c <= ~a; +endmodule + +module abc9_test017(input a, output b); +assign b = ~a; +(* keep *) reg c; +always @* c = b; +endmodule + +module abc9_test018(input a, output b, output c); +assign b = ~a; +(* keep *) wire [1:0] d; +assign c = &d; +endmodule + +module abc9_test019(input a, output b); +assign b = ~a; +(* keep *) reg [1:0] c; +reg d; +always @* d <= &c; +endmodule + +module abc9_test020(input a, output b); +assign b = ~a; +(* keep *) reg [1:0] c; +(* keep *) reg d; +always @* d <= &c; +endmodule From f96d82a5f1982ea86cf02182b33abe91c015b10d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 24 Apr 2019 16:46:41 -0700 Subject: [PATCH 054/213] Add -nocarry option to synth_xilinx --- techlibs/xilinx/synth_xilinx.cc | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 04b0dabca..9e4a86a84 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -63,6 +63,9 @@ struct SynthXilinxPass : public Pass log(" generate an output netlist (and BLIF file) suitable for VPR\n"); log(" (this feature is experimental and incomplete)\n"); log("\n"); + log(" -nocarry\n"); + log(" disable inference of carry chains\n"); + log("\n"); log(" -nobram\n"); log(" disable inference of block rams\n"); log("\n"); @@ -118,7 +121,7 @@ struct SynthXilinxPass : public Pass log(" memory_map\n"); log(" dffsr2dff\n"); log(" dff2dffe\n"); - log(" techmap -map +/xilinx/arith_map.v\n"); + log(" techmap -map +/xilinx/arith_map.v (without '-nocarry' only)\n"); log(" opt -fast\n"); log("\n"); log(" map_cells:\n"); @@ -161,6 +164,7 @@ struct SynthXilinxPass : public Pass bool flatten = false; bool retime = false; bool vpr = false; + bool nocarry = false; bool nobram = false; bool nodram = false; bool nosrl = false; @@ -201,6 +205,10 @@ struct SynthXilinxPass : public Pass vpr = true; continue; } + if (args[argidx] == "-nocarry") { + nocarry = true; + continue; + } if (args[argidx] == "-nobram") { nobram = true; continue; @@ -284,10 +292,11 @@ struct SynthXilinxPass : public Pass Pass::call(design, "dffsr2dff"); Pass::call(design, "dff2dffe"); - if (vpr) { - Pass::call(design, "techmap -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY"); - } else { - Pass::call(design, "techmap -map +/xilinx/arith_map.v"); + if (!nocarry) { + if (vpr) + Pass::call(design, "techmap -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY"); + else + Pass::call(design, "techmap -map +/xilinx/arith_map.v"); } Pass::call(design, "hierarchy -check"); From eec314e2621d3d055d7810f4b7e573a99e0239b2 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 24 Apr 2019 21:06:53 -0700 Subject: [PATCH 055/213] Remove topo sort no-loop assertion, with test --- backends/aiger/xaiger.cc | 13 ------- tests/simple_abc9/abc.box | 2 + tests/simple_abc9/abc9.v | 73 +++++++++++++++++++++++++++++++++++ tests/simple_abc9/run-test.sh | 2 +- 4 files changed, 76 insertions(+), 14 deletions(-) create mode 100644 tests/simple_abc9/abc.box diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 504a66086..f9d874e2d 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -294,20 +294,7 @@ struct XAigerWriter for (auto user_cell : it.second) toposort.edge(driver_cell, user_cell); -#ifndef NDEBUG - toposort.analyze_loops = true; -#endif toposort.sort(); -#ifndef NDEBUG - for (auto &it : toposort.loops) { - log(" loop"); - for (auto cell : it) - log(" %s", log_id(cell)); - log("\n"); - } -#endif - log_assert(!toposort.found_loops); - for (auto cell_name : toposort.sorted) { RTLIL::Cell *cell = module->cell(cell_name); RTLIL::Module* box_module = module->design->module(cell->type); diff --git a/tests/simple_abc9/abc.box b/tests/simple_abc9/abc.box new file mode 100644 index 000000000..a8801d807 --- /dev/null +++ b/tests/simple_abc9/abc.box @@ -0,0 +1,2 @@ +MUXF8 1 0 3 1 +1 1 1 diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index f37d975ff..fb5b759fb 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -142,3 +142,76 @@ assign b = ~a; (* keep *) reg d; always @* d <= &c; endmodule + +module abc9_test021(clk, rst, s_eth_hdr_valid, s_eth_hdr_ready, s_eth_dest_mac, s_eth_src_mac, s_eth_type, s_eth_payload_axis_tdata, s_eth_payload_axis_tkeep, s_eth_payload_axis_tvalid, s_eth_payload_axis_tready, s_eth_payload_axis_tlast, s_eth_payload_axis_tid, s_eth_payload_axis_tdest, s_eth_payload_axis_tuser, m_eth_hdr_valid, m_eth_hdr_ready, m_eth_dest_mac, m_eth_src_mac, m_eth_type, m_eth_payload_axis_tdata, m_eth_payload_axis_tkeep, m_eth_payload_axis_tvalid, m_eth_payload_axis_tready, m_eth_payload_axis_tlast, m_eth_payload_axis_tid, m_eth_payload_axis_tdest, m_eth_payload_axis_tuser); + input clk; + output [47:0] m_eth_dest_mac; + input m_eth_hdr_ready; + output m_eth_hdr_valid; + output [7:0] m_eth_payload_axis_tdata; + output [7:0] m_eth_payload_axis_tdest; + output [7:0] m_eth_payload_axis_tid; + output m_eth_payload_axis_tkeep; + output m_eth_payload_axis_tlast; + input m_eth_payload_axis_tready; + output m_eth_payload_axis_tuser; + output m_eth_payload_axis_tvalid; + output [47:0] m_eth_src_mac; + output [15:0] m_eth_type; + input rst; + input [191:0] s_eth_dest_mac; + output [3:0] s_eth_hdr_ready; + input [3:0] s_eth_hdr_valid; + input [31:0] s_eth_payload_axis_tdata; + input [31:0] s_eth_payload_axis_tdest; + input [31:0] s_eth_payload_axis_tid; + input [3:0] s_eth_payload_axis_tkeep; + input [3:0] s_eth_payload_axis_tlast; + output [3:0] s_eth_payload_axis_tready; + input [3:0] s_eth_payload_axis_tuser; + input [3:0] s_eth_payload_axis_tvalid; + input [191:0] s_eth_src_mac; + input [63:0] s_eth_type; + (* keep *) + wire [0:0] grant, request; + wire a; + not u0 ( + a, + grant[0] + ); + and u1 ( + request[0], + s_eth_hdr_valid[0], + a + ); + (* keep *) + MUXF8 u2 ( + .I0(1'bx), + .I1(1'bx), + .O(o), + .S(1'bx) + ); + arbiter arb_inst ( + .acknowledge(acknowledge), + .clk(clk), + .grant(grant), + .grant_encoded(grant_encoded), + .grant_valid(grant_valid), + .request(request), + .rst(rst) + ); +endmodule + +module arbiter (clk, rst, request, acknowledge, grant, grant_valid, grant_encoded); + input [3:0] acknowledge; + input clk; + output [3:0] grant; + output [1:0] grant_encoded; + output grant_valid; + input [3:0] request; + input rst; +endmodule + +(* abc_box_id=1 *) +module MUXF8(input I0, I1, S, output O); +endmodule diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh index 97f284378..4935d41ad 100755 --- a/tests/simple_abc9/run-test.sh +++ b/tests/simple_abc9/run-test.sh @@ -19,4 +19,4 @@ fi cp ../simple/*.v . DOLLAR='?' -exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p 'hierarchy; synth -run coarse; techmap; opt -full; abc9 -lut 4; stat; check -assert; select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%'" +exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p 'hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4 -box ../abc.box; stat; check -assert; select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%'" From feff9764540cbf1152459cb377fc68d8e10c7153 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 25 Apr 2019 17:11:18 -0700 Subject: [PATCH 056/213] synth_xilinx to call bitblast_shiftx --- techlibs/xilinx/synth_xilinx.cc | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 9e4a86a84..d787687aa 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -126,6 +126,7 @@ struct SynthXilinxPass : public Pass log("\n"); log(" map_cells:\n"); log(" pmux2shiftx (without '-nosrl' and '-nomux' only)\n"); + log(" bitblast_shiftx (without '-nosrl' and '-nomux' only)\n"); log(" simplemap t:$dff t:$dffe (without '-nosrl' only)\n"); log(" opt_expr -mux_undef (without '-nosrl' only)\n"); log(" shregmap -tech xilinx -minlen 3 (without '-nosrl' only)\n"); @@ -309,8 +310,10 @@ struct SynthXilinxPass : public Pass // cells for identifying variable-length shift registers, // so attempt to convert $pmux-es to the former // Also: wide multiplexer inference benefits from this too - if (!nosrl || !nomux) + if (!nosrl || !nomux) { Pass::call(design, "pmux2shiftx"); + Pass::call(design, "bitblast_shiftx"); + } if (!nosrl) { // shregmap operates on bit-level flops, not word-level, From 8d00b9ef7e3455a84c45441287d9a884c922ee20 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 25 Apr 2019 17:23:46 -0700 Subject: [PATCH 057/213] Make pmgen support files more generic --- passes/pmgen/.gitignore | 2 +- passes/pmgen/Makefile.inc | 13 ++++++++----- 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/passes/pmgen/.gitignore b/passes/pmgen/.gitignore index c9263057e..52dfd93f3 100644 --- a/passes/pmgen/.gitignore +++ b/passes/pmgen/.gitignore @@ -1 +1 @@ -/ice40_dsp_pm.h +*_pm.h diff --git a/passes/pmgen/Makefile.inc b/passes/pmgen/Makefile.inc index e0609d9ba..5669bd3d1 100644 --- a/passes/pmgen/Makefile.inc +++ b/passes/pmgen/Makefile.inc @@ -1,8 +1,11 @@ -OBJS += passes/pmgen/ice40_dsp.o +PMG_SRC = $(wildcard passes/pmgen/*.pmg) +PMG_OBJS += $(patsubst %.pmg, %.o, $(PMG_SRC)) +OBJS += $(PMG_OBJS) -passes/pmgen/ice40_dsp.o: passes/pmgen/ice40_dsp_pm.h -EXTRA_OBJS += passes/pmgen/ice40_dsp_pm.h -.SECONDARY: passes/pmgen/ice40_dsp_pm.h +$(PMG_OBJS): %.o: %_pm.h -passes/pmgen/ice40_dsp_pm.h: passes/pmgen/pmgen.py passes/pmgen/ice40_dsp.pmg +EXTRA_OBJS += $(patsubst %.pmg, %_pm.h, $(PMG_SRC)) +.SECONDARY: $(EXTRA_OBJS) + +%_pm.h: passes/pmgen/pmgen.py %.pmg $(P) mkdir -p passes/pmgen && python3 $^ $@ From ccd0729456e1ec105c43007a8392777893ac7d99 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 25 Apr 2019 17:23:59 -0700 Subject: [PATCH 058/213] Add split_shiftx command --- passes/pmgen/split_shiftx.cc | 78 +++++++++++++++++++++++++++++++++++ passes/pmgen/split_shiftx.pmg | 56 +++++++++++++++++++++++++ 2 files changed, 134 insertions(+) create mode 100644 passes/pmgen/split_shiftx.cc create mode 100644 passes/pmgen/split_shiftx.pmg diff --git a/passes/pmgen/split_shiftx.cc b/passes/pmgen/split_shiftx.cc new file mode 100644 index 000000000..71fb4e9ef --- /dev/null +++ b/passes/pmgen/split_shiftx.cc @@ -0,0 +1,78 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/sigtools.h" +#include "passes/pmgen/split_shiftx_pm.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +void create_split_shiftx(split_shiftx_pm &pm) +{ + if (pm.st.shiftxB.empty()) + return; + log_assert(pm.st.shiftx); + SigSpec A = pm.st.shiftx->getPort("\\A"); + SigSpec Y = pm.st.shiftx->getPort("\\Y"); + const int A_WIDTH = pm.st.shiftx->getParam("\\A_WIDTH").as_int(); + const int Y_WIDTH = pm.st.shiftx->getParam("\\Y_WIDTH").as_int(); + log_assert(Y_WIDTH > 1); + std::vector bits; + bits.resize(A_WIDTH / Y_WIDTH); + for (int i = 0; i < Y_WIDTH; ++i) { + for (int j = 0; j < A_WIDTH/Y_WIDTH; ++j) + bits[j] = A[j*Y_WIDTH + i]; + pm.module->addShiftx(NEW_ID, bits, pm.st.shiftxB, Y[i]); + } + pm.st.shiftx->unsetPort("\\Y"); + + pm.autoremove(pm.st.shiftx); + pm.autoremove(pm.st.macc); +} + +struct BitblastShiftxPass : public Pass { + BitblastShiftxPass() : Pass("split_shiftx", "Split up multi-bit $shiftx cells") { } + void help() YS_OVERRIDE + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" split_shiftx [selection]\n"); + log("\n"); + log("Split up $shiftx cells where Y_WIDTH > 1, with consideration for any $macc\n"); + log("cells that may be driving their B inputs.\n"); + log("\n"); + } + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + { + log_header(design, "Executing SPLIT_SHIFTX pass.\n"); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + break; + } + extra_args(args, argidx, design); + + for (auto module : design->selected_modules()) + split_shiftx_pm(module, module->selected_cells()).run(create_split_shiftx); + } +} BitblastShiftxPass; + +PRIVATE_NAMESPACE_END diff --git a/passes/pmgen/split_shiftx.pmg b/passes/pmgen/split_shiftx.pmg new file mode 100644 index 000000000..11b19bfe4 --- /dev/null +++ b/passes/pmgen/split_shiftx.pmg @@ -0,0 +1,56 @@ +state shiftxB + +match shiftx + select shiftx->type == $shiftx + select param(shiftx, \Y_WIDTH).as_int() > 1 +endmatch + +code shiftxB + shiftxB = port(shiftx, \B); + const int b_width = param(shiftx, \B_WIDTH).as_int(); + if (param(shiftx, \B_SIGNED) != 0 && shiftxB[b_width-1] == RTLIL::S0) + shiftxB = shiftxB.extract(0, b_width-1); +endcode + +match macc + select macc->type == $macc + select param(macc, \B_WIDTH).as_int() == 0 + index port(macc, \Y) === shiftxB + optional +endmatch + +code shiftxB + if (macc) { + Const config = param(macc, \CONFIG); + const int config_width = param(macc, \CONFIG_WIDTH).as_int(); + const int num_bits = config.extract(0, 4).as_int(); + const int num_ports = (config_width - 4) / (2 + 2*num_bits); + if (num_ports != 1) { + shiftxB = nullptr; + reject; + } + // IS_SIGNED? + if (config[4] == 1) { + shiftxB = nullptr; + reject; + } + // DO_SUBTRACT? + if (config[5] == 1) { + shiftxB = nullptr; + reject; + } + const int port_size_A = config.extract(6, num_bits).as_int(); + const int port_size_B = config.extract(6 + num_bits, num_bits).as_int(); + const SigSpec port_B = port(macc, \A).extract(port_size_A, port_size_B); + if (!port_B.is_fully_const()) { + shiftxB = nullptr; + reject; + } + const int multiply_factor = port_B.as_int(); + if (multiply_factor != param(shiftx, \Y_WIDTH).as_int()) { + shiftxB = nullptr; + reject; + } + shiftxB = port(macc, \A).extract(0, port_size_A); + } +endcode From af3c374a3589994c41ebd5fcfc75f292dbd7e602 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 25 Apr 2019 17:35:39 -0700 Subject: [PATCH 059/213] Elaborate on help message --- passes/pmgen/split_shiftx.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/passes/pmgen/split_shiftx.cc b/passes/pmgen/split_shiftx.cc index 71fb4e9ef..6eee88886 100644 --- a/passes/pmgen/split_shiftx.cc +++ b/passes/pmgen/split_shiftx.cc @@ -56,7 +56,8 @@ struct BitblastShiftxPass : public Pass { log(" split_shiftx [selection]\n"); log("\n"); log("Split up $shiftx cells where Y_WIDTH > 1, with consideration for any $macc\n"); - log("cells that may be driving their B inputs.\n"); + log("cells -- configured as a constant multiplier equal to Y_WIDTH -- that may be\n"); + log("driving their B inputs.\n"); log("\n"); } void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE From 0eb7150a5706e81ff36a6a57d8c0c6a2fda05e07 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 25 Apr 2019 18:08:05 -0700 Subject: [PATCH 060/213] Add test --- tests/various/split_shiftx.v | 118 ++++++++++++++++++++++++++++++++++ tests/various/split_shiftx.ys | 21 ++++++ 2 files changed, 139 insertions(+) create mode 100644 tests/various/split_shiftx.v create mode 100644 tests/various/split_shiftx.ys diff --git a/tests/various/split_shiftx.v b/tests/various/split_shiftx.v new file mode 100644 index 000000000..dfcea3880 --- /dev/null +++ b/tests/various/split_shiftx.v @@ -0,0 +1,118 @@ +module split_shiftx_test01(i, s, o); + wire [3:0] _0_; + input [8:0] i; + output [2:0] o; + input [1:0] s; + \$macc #( + .A_WIDTH(32'd4), + .B_WIDTH(32'd0), + .CONFIG(10'h282), + .CONFIG_WIDTH(32'd10), + .Y_WIDTH(32'd4) + ) _1_ ( + .A({ 2'h3, s }), + .B(), + .Y(_0_) + ); + \$shiftx #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd9), + .B_SIGNED(32'd1), + .B_WIDTH(32'd5), + .Y_WIDTH(32'd3) + ) _2_ ( + .A(i), + .B({ 1'h0, _0_ }), + .Y(o) + ); +endmodule + +// Sign bit is 1 +module split_shiftx_test02(i, s, o); + wire [3:0] _0_; + input [8:0] i; + output [2:0] o; + input [1:0] s; + \$macc #( + .A_WIDTH(32'd4), + .B_WIDTH(32'd0), + .CONFIG(10'h282), + .CONFIG_WIDTH(32'd10), + .Y_WIDTH(32'd4) + ) _1_ ( + .A({ 2'h3, s }), + .B(), + .Y(_0_) + ); + \$shiftx #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd9), + .B_SIGNED(32'd1), + .B_WIDTH(32'd5), + .Y_WIDTH(32'd3) + ) _2_ ( + .A(i), + .B({ 1'h1, _0_ }), + .Y(o) + ); +endmodule + +// Non constant $macc +module split_shiftx_test03(i, s, o); + wire [3:0] _0_; + input [8:0] i; + output [2:0] o; + input [1:0] s; + \$macc #( + .A_WIDTH(32'd4), + .B_WIDTH(32'd0), + .CONFIG(10'h282), + .CONFIG_WIDTH(32'd10), + .Y_WIDTH(32'd4) + ) _1_ ( + .A({ s, s }), + .B(), + .Y(_0_) + ); + \$shiftx #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd9), + .B_SIGNED(32'd1), + .B_WIDTH(32'd5), + .Y_WIDTH(32'd3) + ) _2_ ( + .A(i), + .B({ 1'h0, _0_ }), + .Y(o) + ); +endmodule + +// Wrong constant $macc +module split_shiftx_test04(i, s, o); + wire [3:0] _0_; + input [8:0] i; + output [2:0] o; + input [1:0] s; + \$macc #( + .A_WIDTH(32'd4), + .B_WIDTH(32'd0), + .CONFIG(10'h282), + .CONFIG_WIDTH(32'd10), + .Y_WIDTH(32'd4) + ) _1_ ( + .A({ 2'h2, s }), + .B(), + .Y(_0_) + ); + \$shiftx #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd9), + .B_SIGNED(32'd1), + .B_WIDTH(32'd5), + .Y_WIDTH(32'd3) + ) _2_ ( + .A(i), + .B({ 1'h0, _0_ }), + .Y(o) + ); +endmodule diff --git a/tests/various/split_shiftx.ys b/tests/various/split_shiftx.ys new file mode 100644 index 000000000..810348aa3 --- /dev/null +++ b/tests/various/split_shiftx.ys @@ -0,0 +1,21 @@ +read_verilog -icells split_shiftx.v +split_shiftx + +cd split_shiftx_test01 +select -assert-count 3 t:$shiftx +select -assert-count 0 t: t:$shiftx %n %i + +cd split_shiftx_test02 +select -assert-count 1 t:$shiftx +select -assert-count 1 t:$macc +select -assert-count 0 t: t:$shiftx t:$macc %u %n %i + +cd split_shiftx_test03 +select -assert-count 1 t:$shiftx +select -assert-count 1 t:$macc +select -assert-count 0 t: t:$shiftx t:$macc %u %n %i + +cd split_shiftx_test04 +select -assert-count 1 t:$shiftx +select -assert-count 1 t:$macc +select -assert-count 0 t: t:$shiftx t:$macc %u %n %i From ece2c49e929cb6f6ac70cccdd84efc2bb1550a39 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 25 Apr 2019 18:39:13 -0700 Subject: [PATCH 061/213] In order to indicate a failed pattern, blacklist? --- passes/pmgen/split_shiftx.cc | 4 ++-- passes/pmgen/split_shiftx.pmg | 27 ++++++++++++++------------- 2 files changed, 16 insertions(+), 15 deletions(-) diff --git a/passes/pmgen/split_shiftx.cc b/passes/pmgen/split_shiftx.cc index 6eee88886..672478959 100644 --- a/passes/pmgen/split_shiftx.cc +++ b/passes/pmgen/split_shiftx.cc @@ -26,9 +26,9 @@ PRIVATE_NAMESPACE_BEGIN void create_split_shiftx(split_shiftx_pm &pm) { - if (pm.st.shiftxB.empty()) - return; log_assert(pm.st.shiftx); + if (pm.blacklist_cells.count(pm.st.shiftx)) + return; SigSpec A = pm.st.shiftx->getPort("\\A"); SigSpec Y = pm.st.shiftx->getPort("\\Y"); const int A_WIDTH = pm.st.shiftx->getParam("\\A_WIDTH").as_int(); diff --git a/passes/pmgen/split_shiftx.pmg b/passes/pmgen/split_shiftx.pmg index 11b19bfe4..c9e0ff995 100644 --- a/passes/pmgen/split_shiftx.pmg +++ b/passes/pmgen/split_shiftx.pmg @@ -5,50 +5,51 @@ match shiftx select param(shiftx, \Y_WIDTH).as_int() > 1 endmatch -code shiftxB - shiftxB = port(shiftx, \B); - const int b_width = param(shiftx, \B_WIDTH).as_int(); - if (param(shiftx, \B_SIGNED) != 0 && shiftxB[b_width-1] == RTLIL::S0) - shiftxB = shiftxB.extract(0, b_width-1); -endcode - match macc select macc->type == $macc select param(macc, \B_WIDTH).as_int() == 0 - index port(macc, \Y) === shiftxB optional endmatch code shiftxB if (macc) { + shiftxB = port(shiftx, \B); + const int b_width = param(shiftx, \B_WIDTH).as_int(); + if (param(shiftx, \B_SIGNED) != 0 && shiftxB[b_width-1] == RTLIL::S0) + shiftxB = shiftxB.extract(0, b_width-1); + if (port(macc, \Y) != shiftxB) { + blacklist(shiftx); + reject; + } + Const config = param(macc, \CONFIG); const int config_width = param(macc, \CONFIG_WIDTH).as_int(); const int num_bits = config.extract(0, 4).as_int(); const int num_ports = (config_width - 4) / (2 + 2*num_bits); if (num_ports != 1) { - shiftxB = nullptr; + blacklist(shiftx); reject; } // IS_SIGNED? if (config[4] == 1) { - shiftxB = nullptr; + blacklist(shiftx); reject; } // DO_SUBTRACT? if (config[5] == 1) { - shiftxB = nullptr; + blacklist(shiftx); reject; } const int port_size_A = config.extract(6, num_bits).as_int(); const int port_size_B = config.extract(6 + num_bits, num_bits).as_int(); const SigSpec port_B = port(macc, \A).extract(port_size_A, port_size_B); if (!port_B.is_fully_const()) { - shiftxB = nullptr; + blacklist(shiftx); reject; } const int multiply_factor = port_B.as_int(); if (multiply_factor != param(shiftx, \Y_WIDTH).as_int()) { - shiftxB = nullptr; + blacklist(shiftx); reject; } shiftxB = port(macc, \A).extract(0, port_size_A); From fb4348f8409f038656c4ece79a43485baf34dd7f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 25 Apr 2019 19:38:19 -0700 Subject: [PATCH 062/213] Fix for when B_WIDTH has trailing zeroes --- passes/pmgen/split_shiftx.cc | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/passes/pmgen/split_shiftx.cc b/passes/pmgen/split_shiftx.cc index 672478959..2af0ebecf 100644 --- a/passes/pmgen/split_shiftx.cc +++ b/passes/pmgen/split_shiftx.cc @@ -30,16 +30,20 @@ void create_split_shiftx(split_shiftx_pm &pm) if (pm.blacklist_cells.count(pm.st.shiftx)) return; SigSpec A = pm.st.shiftx->getPort("\\A"); + SigSpec B = pm.st.shiftx->getPort("\\B"); SigSpec Y = pm.st.shiftx->getPort("\\Y"); const int A_WIDTH = pm.st.shiftx->getParam("\\A_WIDTH").as_int(); + const int B_WIDTH = pm.st.shiftx->getParam("\\B_WIDTH").as_int(); const int Y_WIDTH = pm.st.shiftx->getParam("\\Y_WIDTH").as_int(); - log_assert(Y_WIDTH > 1); + int trailing_zeroes = 0; + for (; B[trailing_zeroes] == RTLIL::S0; ++trailing_zeroes) ; + const int WIDTH = trailing_zeroes > 0 ? 1 << trailing_zeroes : Y_WIDTH; std::vector bits; - bits.resize(A_WIDTH / Y_WIDTH); + bits.resize(A_WIDTH / WIDTH); for (int i = 0; i < Y_WIDTH; ++i) { - for (int j = 0; j < A_WIDTH/Y_WIDTH; ++j) - bits[j] = A[j*Y_WIDTH + i]; - pm.module->addShiftx(NEW_ID, bits, pm.st.shiftxB, Y[i]); + for (int j = 0; j < A_WIDTH/WIDTH; ++j) + bits[j] = A[j*WIDTH + i]; + pm.module->addShiftx(NEW_ID, bits, B.extract(trailing_zeroes, B_WIDTH-trailing_zeroes), Y[i]); } pm.st.shiftx->unsetPort("\\Y"); From 019c48b5083f065d3485b5c9e5c8d4b4554f3af3 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 25 Apr 2019 19:38:35 -0700 Subject: [PATCH 063/213] bitblast_shiftx -> split_shiftx --- techlibs/xilinx/synth_xilinx.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index d787687aa..f65ae87f5 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -126,7 +126,7 @@ struct SynthXilinxPass : public Pass log("\n"); log(" map_cells:\n"); log(" pmux2shiftx (without '-nosrl' and '-nomux' only)\n"); - log(" bitblast_shiftx (without '-nosrl' and '-nomux' only)\n"); + log(" split_shiftx (without '-nosrl' and '-nomux' only)\n"); log(" simplemap t:$dff t:$dffe (without '-nosrl' only)\n"); log(" opt_expr -mux_undef (without '-nosrl' only)\n"); log(" shregmap -tech xilinx -minlen 3 (without '-nosrl' only)\n"); @@ -312,7 +312,7 @@ struct SynthXilinxPass : public Pass // Also: wide multiplexer inference benefits from this too if (!nosrl || !nomux) { Pass::call(design, "pmux2shiftx"); - Pass::call(design, "bitblast_shiftx"); + Pass::call(design, "split_shiftx"); } if (!nosrl) { From f14d7f0df65c6892b911c74e1674a94ad3e556db Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 25 Apr 2019 19:43:41 -0700 Subject: [PATCH 064/213] Cleanup superseded --- techlibs/xilinx/cells_map.v | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 4275c03e6..c814f3a96 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -167,17 +167,7 @@ module \$shiftx (A, B, Y); wire _TECHMAP_FAIL_ = 1; end else if (Y_WIDTH > 1) begin - for (i = 0; i < Y_WIDTH; i++) - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-Y_WIDTH+1), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A(A[A_WIDTH-Y_WIDTH+i:i]), .B(B), .Y(Y[i])); - end - // If the LSB of B is constant zero (and Y_WIDTH is 1) then - // we can optimise by removing every other entry from A - // and popping the constant zero from B - else if (_TECHMAP_CONSTMSK_B_[0] && !_TECHMAP_CONSTVAL_B_[0]) begin - wire [(A_WIDTH+1)/2-1:0] A_i; - for (i = 0; i < (A_WIDTH+1)/2; i++) - assign A_i[i] = A[i*2]; - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y)); + wire _TECHMAP_FAIL_ = 1; end else if (B_WIDTH < 3 || A_WIDTH <= 4) begin wire _TECHMAP_FAIL_ = 1; From 976d8030dce8cd242401933ac8ea6c8ffe8af224 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 25 Apr 2019 19:59:33 -0700 Subject: [PATCH 065/213] Actually use pm.st.shiftxB --- passes/pmgen/split_shiftx.cc | 5 +++-- passes/pmgen/split_shiftx.pmg | 4 +++- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/passes/pmgen/split_shiftx.cc b/passes/pmgen/split_shiftx.cc index 2af0ebecf..3cbabcd76 100644 --- a/passes/pmgen/split_shiftx.cc +++ b/passes/pmgen/split_shiftx.cc @@ -30,10 +30,11 @@ void create_split_shiftx(split_shiftx_pm &pm) if (pm.blacklist_cells.count(pm.st.shiftx)) return; SigSpec A = pm.st.shiftx->getPort("\\A"); - SigSpec B = pm.st.shiftx->getPort("\\B"); + SigSpec B = pm.st.shiftxB; + log_assert(!B.empty()); SigSpec Y = pm.st.shiftx->getPort("\\Y"); const int A_WIDTH = pm.st.shiftx->getParam("\\A_WIDTH").as_int(); - const int B_WIDTH = pm.st.shiftx->getParam("\\B_WIDTH").as_int(); + const int B_WIDTH = GetSize(pm.st.shiftxB); const int Y_WIDTH = pm.st.shiftx->getParam("\\Y_WIDTH").as_int(); int trailing_zeroes = 0; for (; B[trailing_zeroes] == RTLIL::S0; ++trailing_zeroes) ; diff --git a/passes/pmgen/split_shiftx.pmg b/passes/pmgen/split_shiftx.pmg index c9e0ff995..3aafe1975 100644 --- a/passes/pmgen/split_shiftx.pmg +++ b/passes/pmgen/split_shiftx.pmg @@ -12,11 +12,13 @@ match macc endmatch code shiftxB + shiftxB = port(shiftx, \B); + if (macc) { - shiftxB = port(shiftx, \B); const int b_width = param(shiftx, \B_WIDTH).as_int(); if (param(shiftx, \B_SIGNED) != 0 && shiftxB[b_width-1] == RTLIL::S0) shiftxB = shiftxB.extract(0, b_width-1); + if (port(macc, \Y) != shiftxB) { blacklist(shiftx); reject; From 4473fd15020cc186fde71eadc2325f69c92ae7ac Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 26 Apr 2019 11:14:33 -0700 Subject: [PATCH 066/213] Add -undef option to equiv_opt, passed to equiv_induct --- passes/equiv/equiv_opt.cc | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/passes/equiv/equiv_opt.cc b/passes/equiv/equiv_opt.cc index e5dda9c24..3596dfd7b 100644 --- a/passes/equiv/equiv_opt.cc +++ b/passes/equiv/equiv_opt.cc @@ -44,7 +44,10 @@ struct EquivOptPass:public ScriptPass log(" useful for handling architecture-specific primitives.\n"); log("\n"); log(" -assert\n"); - log(" produce an error if the circuits are not equivalent\n"); + log(" produce an error if the circuits are not equivalent.\n"); + log("\n"); + log(" -undef\n"); + log(" enable modelling of undef states during equiv_induct.\n"); log("\n"); log("The following commands are executed by this verification command:\n"); help_script(); @@ -52,13 +55,14 @@ struct EquivOptPass:public ScriptPass } std::string command, techmap_opts; - bool assert; + bool assert, undef; void clear_flags() YS_OVERRIDE { command = ""; techmap_opts = ""; assert = false; + undef = false; } void execute(std::vector < std::string > args, RTLIL::Design * design) YS_OVERRIDE @@ -84,6 +88,10 @@ struct EquivOptPass:public ScriptPass assert = true; continue; } + if (args[argidx] == "-undef") { + undef = true; + continue; + } break; } @@ -139,7 +147,12 @@ struct EquivOptPass:public ScriptPass if (check_label("prove")) { run("equiv_make gold gate equiv"); - run("equiv_induct equiv"); + if (help_mode) + run("equiv_induct [-undef] equiv"); + else if (undef) + run("equiv_induct -undef equiv"); + else + run("equiv_induct equiv"); if (help_mode) run("equiv_status [-assert] equiv"); else if (assert) From 8469d9fe9ff0a819c6b67aa6121cfd01cd1d0665 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 26 Apr 2019 14:51:37 -0700 Subject: [PATCH 067/213] Missing newline --- techlibs/xilinx/synth_xilinx.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index f65ae87f5..b6b22284c 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -139,7 +139,7 @@ struct SynthXilinxPass : public Pass log(" abc -luts 2:2,3,6:5,10,20 [-dff]\n"); log(" clean\n"); log(" shregmap -minlen 3 -init -params -enpol any_or_none (without '-nosrl' only)\n"); - log(" techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v"); + log(" techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v\n"); log(" dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT \\\n"); log(" -ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT\n"); log("\n"); From dcc8a13e481c058f17b98ea900f9feb9192ea5ae Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 26 Apr 2019 15:32:02 -0700 Subject: [PATCH 068/213] Revert "Merge branch 'eddie/split_shiftx' into xc7mux" This reverts commit 3042d5833041021bb45252b0cc862e9eff3d27d3, reversing changes made to feff9764540cbf1152459cb377fc68d8e10c7153. --- README.md | 6 +-- kernel/cellaigs.cc | 2 +- kernel/celltypes.h | 2 +- passes/opt/wreduce.cc | 2 + passes/pmgen/.gitignore | 2 +- passes/pmgen/Makefile.inc | 13 +++--- passes/pmgen/README.md | 2 +- passes/pmgen/split_shiftx.cc | 84 ----------------------------------- passes/pmgen/split_shiftx.pmg | 59 ------------------------ 9 files changed, 14 insertions(+), 158 deletions(-) delete mode 100644 passes/pmgen/split_shiftx.cc delete mode 100644 passes/pmgen/split_shiftx.pmg diff --git a/README.md b/README.md index 913777f2e..46bed4242 100644 --- a/README.md +++ b/README.md @@ -370,7 +370,7 @@ Verilog Attributes and non-standard features - When defining a macro with `define, all text between triple double quotes is interpreted as macro body, even if it contains unescaped newlines. The - triple double quotes are removed from the macro body. For example: + tipple double quotes are removed from the macro body. For example: `define MY_MACRO(a, b) """ assign a = 23; @@ -457,7 +457,7 @@ Non-standard or SystemVerilog features for formal verification supported in any clocked block. - The syntax ``@($global_clock)`` can be used to create FFs that have no - explicit clock input (``$ff`` cells). The same can be achieved by using + explicit clock input ($ff cells). The same can be achieved by using ``@(posedge )`` or ``@(negedge )`` when ```` is marked with the ``(* gclk *)`` Verilog attribute. @@ -470,7 +470,7 @@ from SystemVerilog: - The ``assert`` statement from SystemVerilog is supported in its most basic form. In module context: ``assert property ();`` and within an - always block: ``assert();``. It is transformed to an ``$assert`` cell. + always block: ``assert();``. It is transformed to a $assert cell. - The ``assume``, ``restrict``, and ``cover`` statements from SystemVerilog are also supported. The same limitations as with the ``assert`` statement apply. diff --git a/kernel/cellaigs.cc b/kernel/cellaigs.cc index 26c625f89..5fd76afe5 100644 --- a/kernel/cellaigs.cc +++ b/kernel/cellaigs.cc @@ -453,7 +453,7 @@ Aig::Aig(Cell *cell) int B = mk.inport("\\B"); int C = mk.inport("\\C"); int D = mk.inport("\\D"); - int Y = mk.nand_gate(mk.or_gate(A, B), mk.or_gate(C, D)); + int Y = mk.nand_gate(mk.nor_gate(A, B), mk.nor_gate(C, D)); mk.outport(Y, "\\Y"); goto optimize; } diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 0da78c313..ae88f4aaf 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -464,7 +464,7 @@ struct CellTypes if (cell->type == "$_AOI4_") return eval_not(const_or(const_and(arg1, arg2, false, false, 1), const_and(arg3, arg4, false, false, 1), false, false, 1)); if (cell->type == "$_OAI4_") - return eval_not(const_and(const_or(arg1, arg2, false, false, 1), const_or(arg3, arg4, false, false, 1), false, false, 1)); + return eval_not(const_and(const_or(arg1, arg2, false, false, 1), const_and(arg3, arg4, false, false, 1), false, false, 1)); log_assert(arg4.bits.size() == 0); return eval(cell, arg1, arg2, arg3, errp); diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index 68e077cf9..52245ce3e 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -462,10 +462,12 @@ struct WreduceWorker SigSpec initsig = init_attr_sigmap(w); int width = std::min(GetSize(initval), GetSize(initsig)); for (int i = 0; i < width; i++) { + log_dump(initsig[i], remove_init_bits.count(initsig[i])); if (!remove_init_bits.count(initsig[i])) new_initval[i] = initval[i]; } w->attributes.at("\\init") = new_initval; + log_dump(w->name, initval, new_initval); } } } diff --git a/passes/pmgen/.gitignore b/passes/pmgen/.gitignore index 52dfd93f3..c9263057e 100644 --- a/passes/pmgen/.gitignore +++ b/passes/pmgen/.gitignore @@ -1 +1 @@ -*_pm.h +/ice40_dsp_pm.h diff --git a/passes/pmgen/Makefile.inc b/passes/pmgen/Makefile.inc index 5669bd3d1..e0609d9ba 100644 --- a/passes/pmgen/Makefile.inc +++ b/passes/pmgen/Makefile.inc @@ -1,11 +1,8 @@ -PMG_SRC = $(wildcard passes/pmgen/*.pmg) -PMG_OBJS += $(patsubst %.pmg, %.o, $(PMG_SRC)) -OBJS += $(PMG_OBJS) +OBJS += passes/pmgen/ice40_dsp.o -$(PMG_OBJS): %.o: %_pm.h +passes/pmgen/ice40_dsp.o: passes/pmgen/ice40_dsp_pm.h +EXTRA_OBJS += passes/pmgen/ice40_dsp_pm.h +.SECONDARY: passes/pmgen/ice40_dsp_pm.h -EXTRA_OBJS += $(patsubst %.pmg, %_pm.h, $(PMG_SRC)) -.SECONDARY: $(EXTRA_OBJS) - -%_pm.h: passes/pmgen/pmgen.py %.pmg +passes/pmgen/ice40_dsp_pm.h: passes/pmgen/pmgen.py passes/pmgen/ice40_dsp.pmg $(P) mkdir -p passes/pmgen && python3 $^ $@ diff --git a/passes/pmgen/README.md b/passes/pmgen/README.md index 320e95a77..7a46558b1 100644 --- a/passes/pmgen/README.md +++ b/passes/pmgen/README.md @@ -220,5 +220,5 @@ But in some cases it is more natural to utilize the implicit branch statement: portAB = \B; endcode -There is an implicit `code..endcode` block at the end of each `.pmg` file +There is an implicit `code..endcode` block at the end of each `.pgm` file that just accepts everything that gets all the way there. diff --git a/passes/pmgen/split_shiftx.cc b/passes/pmgen/split_shiftx.cc deleted file mode 100644 index 3cbabcd76..000000000 --- a/passes/pmgen/split_shiftx.cc +++ /dev/null @@ -1,84 +0,0 @@ -/* - * yosys -- Yosys Open SYnthesis Suite - * - * Copyright (C) 2012 Clifford Wolf - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - * - */ - -#include "kernel/yosys.h" -#include "kernel/sigtools.h" -#include "passes/pmgen/split_shiftx_pm.h" - -USING_YOSYS_NAMESPACE -PRIVATE_NAMESPACE_BEGIN - -void create_split_shiftx(split_shiftx_pm &pm) -{ - log_assert(pm.st.shiftx); - if (pm.blacklist_cells.count(pm.st.shiftx)) - return; - SigSpec A = pm.st.shiftx->getPort("\\A"); - SigSpec B = pm.st.shiftxB; - log_assert(!B.empty()); - SigSpec Y = pm.st.shiftx->getPort("\\Y"); - const int A_WIDTH = pm.st.shiftx->getParam("\\A_WIDTH").as_int(); - const int B_WIDTH = GetSize(pm.st.shiftxB); - const int Y_WIDTH = pm.st.shiftx->getParam("\\Y_WIDTH").as_int(); - int trailing_zeroes = 0; - for (; B[trailing_zeroes] == RTLIL::S0; ++trailing_zeroes) ; - const int WIDTH = trailing_zeroes > 0 ? 1 << trailing_zeroes : Y_WIDTH; - std::vector bits; - bits.resize(A_WIDTH / WIDTH); - for (int i = 0; i < Y_WIDTH; ++i) { - for (int j = 0; j < A_WIDTH/WIDTH; ++j) - bits[j] = A[j*WIDTH + i]; - pm.module->addShiftx(NEW_ID, bits, B.extract(trailing_zeroes, B_WIDTH-trailing_zeroes), Y[i]); - } - pm.st.shiftx->unsetPort("\\Y"); - - pm.autoremove(pm.st.shiftx); - pm.autoremove(pm.st.macc); -} - -struct BitblastShiftxPass : public Pass { - BitblastShiftxPass() : Pass("split_shiftx", "Split up multi-bit $shiftx cells") { } - void help() YS_OVERRIDE - { - // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| - log("\n"); - log(" split_shiftx [selection]\n"); - log("\n"); - log("Split up $shiftx cells where Y_WIDTH > 1, with consideration for any $macc\n"); - log("cells -- configured as a constant multiplier equal to Y_WIDTH -- that may be\n"); - log("driving their B inputs.\n"); - log("\n"); - } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE - { - log_header(design, "Executing SPLIT_SHIFTX pass.\n"); - - size_t argidx; - for (argidx = 1; argidx < args.size(); argidx++) - { - break; - } - extra_args(args, argidx, design); - - for (auto module : design->selected_modules()) - split_shiftx_pm(module, module->selected_cells()).run(create_split_shiftx); - } -} BitblastShiftxPass; - -PRIVATE_NAMESPACE_END diff --git a/passes/pmgen/split_shiftx.pmg b/passes/pmgen/split_shiftx.pmg deleted file mode 100644 index 3aafe1975..000000000 --- a/passes/pmgen/split_shiftx.pmg +++ /dev/null @@ -1,59 +0,0 @@ -state shiftxB - -match shiftx - select shiftx->type == $shiftx - select param(shiftx, \Y_WIDTH).as_int() > 1 -endmatch - -match macc - select macc->type == $macc - select param(macc, \B_WIDTH).as_int() == 0 - optional -endmatch - -code shiftxB - shiftxB = port(shiftx, \B); - - if (macc) { - const int b_width = param(shiftx, \B_WIDTH).as_int(); - if (param(shiftx, \B_SIGNED) != 0 && shiftxB[b_width-1] == RTLIL::S0) - shiftxB = shiftxB.extract(0, b_width-1); - - if (port(macc, \Y) != shiftxB) { - blacklist(shiftx); - reject; - } - - Const config = param(macc, \CONFIG); - const int config_width = param(macc, \CONFIG_WIDTH).as_int(); - const int num_bits = config.extract(0, 4).as_int(); - const int num_ports = (config_width - 4) / (2 + 2*num_bits); - if (num_ports != 1) { - blacklist(shiftx); - reject; - } - // IS_SIGNED? - if (config[4] == 1) { - blacklist(shiftx); - reject; - } - // DO_SUBTRACT? - if (config[5] == 1) { - blacklist(shiftx); - reject; - } - const int port_size_A = config.extract(6, num_bits).as_int(); - const int port_size_B = config.extract(6 + num_bits, num_bits).as_int(); - const SigSpec port_B = port(macc, \A).extract(port_size_A, port_size_B); - if (!port_B.is_fully_const()) { - blacklist(shiftx); - reject; - } - const int multiply_factor = port_B.as_int(); - if (multiply_factor != param(shiftx, \Y_WIDTH).as_int()) { - blacklist(shiftx); - reject; - } - shiftxB = port(macc, \A).extract(0, port_size_A); - } -endcode From 6b9ca7cd6d14ac5e3ebf8354849a5c31d9a3a49b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 26 Apr 2019 15:32:58 -0700 Subject: [PATCH 069/213] Remove split_shiftx call --- techlibs/xilinx/synth_xilinx.cc | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index b6b22284c..1320673e5 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -126,7 +126,6 @@ struct SynthXilinxPass : public Pass log("\n"); log(" map_cells:\n"); log(" pmux2shiftx (without '-nosrl' and '-nomux' only)\n"); - log(" split_shiftx (without '-nosrl' and '-nomux' only)\n"); log(" simplemap t:$dff t:$dffe (without '-nosrl' only)\n"); log(" opt_expr -mux_undef (without '-nosrl' only)\n"); log(" shregmap -tech xilinx -minlen 3 (without '-nosrl' only)\n"); @@ -310,10 +309,8 @@ struct SynthXilinxPass : public Pass // cells for identifying variable-length shift registers, // so attempt to convert $pmux-es to the former // Also: wide multiplexer inference benefits from this too - if (!nosrl || !nomux) { + if (!nosrl || !nomux) Pass::call(design, "pmux2shiftx"); - Pass::call(design, "split_shiftx"); - } if (!nosrl) { // shregmap operates on bit-level flops, not word-level, From e31e21766d3bf323ce61754a28ac58ec7118b9c0 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 26 Apr 2019 16:09:54 -0700 Subject: [PATCH 070/213] Try a different approach with 'muxcover' --- techlibs/xilinx/cells_map.v | 82 ++++++--------------------------- techlibs/xilinx/synth_xilinx.cc | 44 +++++++++--------- 2 files changed, 37 insertions(+), 89 deletions(-) diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index c814f3a96..258b6c3de 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -143,75 +143,23 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o endmodule `ifndef NO_MUXFN -module \$shiftx (A, B, Y); - parameter A_SIGNED = 0; - parameter B_SIGNED = 0; - parameter A_WIDTH = 1; - parameter B_WIDTH = 1; - parameter Y_WIDTH = 1; +module \$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y); + input A, B, C, D, E, F, G, H, S, T, U; + output Y; - input [A_WIDTH-1:0] A; - input [B_WIDTH-1:0] B; - output [Y_WIDTH-1:0] Y; + wire [1:0] Z; + assign Z = T ? (S ? {D,H} : {C,G}) : + (S ? {B,F} : {A,E}); + MUXF7 fpga_muxf7 (.I0(Z[0]), .I1(Z[1]), .S(U), .O(Y)); +endmodule - parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0; - parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0; +module \$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y); + input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V; + output Y; - generate - genvar i, j; - if (B_SIGNED) begin - if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && _TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0) - // Optimisation to remove B_SIGNED if sign bit of B is constant-0 - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B[B_WIDTH-2:0]), .Y(Y)); - else - wire _TECHMAP_FAIL_ = 1; - end - else if (Y_WIDTH > 1) begin - wire _TECHMAP_FAIL_ = 1; - end - else if (B_WIDTH < 3 || A_WIDTH <= 4) begin - wire _TECHMAP_FAIL_ = 1; - end - else if (B_WIDTH == 3) begin - localparam a_width0 = 2 ** 2; - localparam a_widthN = A_WIDTH - a_width0; - wire T0, T1; - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[a_width0-1:0]), .B(B[2-1:0]), .Y(T0)); - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1)); - MUXF7 fpga_mux (.I0(T0), .I1(T1), .S(B[B_WIDTH-1]), .O(Y)); - end - else if (B_WIDTH == 4) begin - localparam a_width0 = 2 ** 2; - localparam num_mux8 = A_WIDTH / a_width0; - localparam a_widthN = A_WIDTH - num_mux8*a_width0; - wire [4-1:0] T; - wire T0, T1; - for (i = 0; i < 4; i++) - if (i < num_mux8) - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[i*a_width0+:a_width0]), .B(B[2-1:0]), .Y(T[i])); - else if (i == num_mux8 && a_widthN > 0) - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i])); - else - assign T[i] = 1'bx; - MUXF7 fpga_mux_0 (.I0(T[0]), .I1(T[1]), .S(B[2]), .O(T0)); - MUXF7 fpga_mux_1 (.I0(T[2]), .I1(T[3]), .S(B[2]), .O(T1)); - MUXF8 fpga_mux_2 (.I0(T0), .I1(T1), .S(B[3]), .O(Y)); - end - else begin - localparam a_width0 = 2 ** 4; - localparam num_mux16 = A_WIDTH / a_width0; - localparam a_widthN = A_WIDTH - num_mux16*a_width0; - wire [(2**(B_WIDTH-4))-1:0] T; - for (i = 0; i < 2 ** (B_WIDTH-4); i++) - if (i < num_mux16) - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]), .Y(T[i])); - else if (i == num_mux16 && a_widthN > 0) begin - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i])); - end - else - assign T[i] = 1'bx; - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(2**(B_WIDTH-4)), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y)); - end - endgenerate + wire [1:0] Z; + \$_MUX8_ fpga_mux8_0 (.A(A), .B(B), .C(C), .D(D), .E(E), .F(F), .G(G), .H(H), .S(S), .T(T), .U(U), .Y(Z[0])); + \$_MUX8_ fpga_mux8_1 (.A(I), .B(J), .C(K), .D(L), .E(M), .F(N), .G(O), .H(P), .S(S), .T(T), .U(U), .Y(Z[1])); + MUXF8 fpga_muxf8 (.I0(Z[0]), .I1(Z[1]), .S(V), .O(Y)); endmodule `endif // NO_MUXFN diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 524c54d3b..5652806f7 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -292,18 +292,6 @@ struct SynthXilinxPass : public Pass Pass::call(design, "dffsr2dff"); Pass::call(design, "dff2dffe"); - if (!nocarry) { - if (vpr) - Pass::call(design, "techmap -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY"); - else - Pass::call(design, "techmap -map +/xilinx/arith_map.v"); - } - - Pass::call(design, "opt -fast"); - } - - if (check_label(active, run_from, run_to, "map_cells")) - { // shregmap -tech xilinx can cope with $shiftx and $mux // cells for identifying variable-length shift registers, // so attempt to convert $pmux-es to the former @@ -311,17 +299,30 @@ struct SynthXilinxPass : public Pass if (!nosrl || !nomux) Pass::call(design, "pmux2shiftx"); - if (!nosrl) { - // shregmap operates on bit-level flops, not word-level, - // so break those down here - Pass::call(design, "simplemap t:$dff t:$dffe"); - // pmux2shiftx can leave behind a $pmux with a single entry - // -- need this to clean that up before shregmap - Pass::call(design, "opt_expr -mux_undef"); - // shregmap with '-tech xilinx' infers variable length shift regs - Pass::call(design, "shregmap -tech xilinx -minlen 3"); + Pass::call(design, "opt -full"); + if (!nocarry) { + if (vpr) + Pass::call(design, "techmap -map +/techmap.v -D _EXPLICIT_CARRY -map +/xilinx/arith_map.v"); + else + Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v"); } + else { + Pass::call(design, "techmap"); + } + Pass::call(design, "opt -fast"); + // shregmap with '-tech xilinx' infers variable length shift regs + if (!nosrl) + Pass::call(design, "shregmap -tech xilinx -minlen 3"); + + if (!nomux) + Pass::call(design, "muxcover -mux8 -mux16"); + + Pass::call(design, "opt -fast"); + } + + if (check_label(active, run_from, run_to, "map_cells")) + { std::string define; if (nomux) define += " -D NO_MUXFN"; @@ -331,7 +332,6 @@ struct SynthXilinxPass : public Pass if (check_label(active, run_from, run_to, "map_luts")) { - Pass::call(design, "opt -full"); Pass::call(design, "techmap -map +/techmap.v -D _NO_POS_SR -map +/xilinx/ff_map.v"); if (abc == "abc9") Pass::call(design, abc + " -lut +/xilinx/abc.lut -box +/xilinx/abc.box" + string(retime ? " -dff" : "")); From ccc283737d99cb0f4d5742692d5d86c4ad9396c6 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 26 Apr 2019 16:28:48 -0700 Subject: [PATCH 071/213] Apparently, this reduces number of MUXCY/XORCY --- techlibs/xilinx/synth_xilinx.cc | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 5652806f7..4ec115bec 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -287,11 +287,18 @@ struct SynthXilinxPass : public Pass if (check_label(active, run_from, run_to, "fine")) { - Pass::call(design, "opt -fast"); + Pass::call(design, "opt -fast -full"); Pass::call(design, "memory_map"); Pass::call(design, "dffsr2dff"); Pass::call(design, "dff2dffe"); + if (!nocarry) { + if (vpr) + Pass::call(design, "techmap -D _EXPLICIT_CARRY -map +/xilinx/arith_map.v"); + else + Pass::call(design, "techmap -map +/xilinx/arith_map.v"); + } + // shregmap -tech xilinx can cope with $shiftx and $mux // cells for identifying variable-length shift registers, // so attempt to convert $pmux-es to the former @@ -300,15 +307,7 @@ struct SynthXilinxPass : public Pass Pass::call(design, "pmux2shiftx"); Pass::call(design, "opt -full"); - if (!nocarry) { - if (vpr) - Pass::call(design, "techmap -map +/techmap.v -D _EXPLICIT_CARRY -map +/xilinx/arith_map.v"); - else - Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v"); - } - else { - Pass::call(design, "techmap"); - } + Pass::call(design, "techmap"); Pass::call(design, "opt -fast"); // shregmap with '-tech xilinx' infers variable length shift regs From 0f1ba949243aa7ccc7c6b42738a60a09be7a209e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 26 Apr 2019 19:45:47 -0700 Subject: [PATCH 072/213] Remove split_shiftx tests --- tests/various/split_shiftx.v | 118 ---------------------------------- tests/various/split_shiftx.ys | 21 ------ 2 files changed, 139 deletions(-) delete mode 100644 tests/various/split_shiftx.v delete mode 100644 tests/various/split_shiftx.ys diff --git a/tests/various/split_shiftx.v b/tests/various/split_shiftx.v deleted file mode 100644 index dfcea3880..000000000 --- a/tests/various/split_shiftx.v +++ /dev/null @@ -1,118 +0,0 @@ -module split_shiftx_test01(i, s, o); - wire [3:0] _0_; - input [8:0] i; - output [2:0] o; - input [1:0] s; - \$macc #( - .A_WIDTH(32'd4), - .B_WIDTH(32'd0), - .CONFIG(10'h282), - .CONFIG_WIDTH(32'd10), - .Y_WIDTH(32'd4) - ) _1_ ( - .A({ 2'h3, s }), - .B(), - .Y(_0_) - ); - \$shiftx #( - .A_SIGNED(32'd0), - .A_WIDTH(32'd9), - .B_SIGNED(32'd1), - .B_WIDTH(32'd5), - .Y_WIDTH(32'd3) - ) _2_ ( - .A(i), - .B({ 1'h0, _0_ }), - .Y(o) - ); -endmodule - -// Sign bit is 1 -module split_shiftx_test02(i, s, o); - wire [3:0] _0_; - input [8:0] i; - output [2:0] o; - input [1:0] s; - \$macc #( - .A_WIDTH(32'd4), - .B_WIDTH(32'd0), - .CONFIG(10'h282), - .CONFIG_WIDTH(32'd10), - .Y_WIDTH(32'd4) - ) _1_ ( - .A({ 2'h3, s }), - .B(), - .Y(_0_) - ); - \$shiftx #( - .A_SIGNED(32'd0), - .A_WIDTH(32'd9), - .B_SIGNED(32'd1), - .B_WIDTH(32'd5), - .Y_WIDTH(32'd3) - ) _2_ ( - .A(i), - .B({ 1'h1, _0_ }), - .Y(o) - ); -endmodule - -// Non constant $macc -module split_shiftx_test03(i, s, o); - wire [3:0] _0_; - input [8:0] i; - output [2:0] o; - input [1:0] s; - \$macc #( - .A_WIDTH(32'd4), - .B_WIDTH(32'd0), - .CONFIG(10'h282), - .CONFIG_WIDTH(32'd10), - .Y_WIDTH(32'd4) - ) _1_ ( - .A({ s, s }), - .B(), - .Y(_0_) - ); - \$shiftx #( - .A_SIGNED(32'd0), - .A_WIDTH(32'd9), - .B_SIGNED(32'd1), - .B_WIDTH(32'd5), - .Y_WIDTH(32'd3) - ) _2_ ( - .A(i), - .B({ 1'h0, _0_ }), - .Y(o) - ); -endmodule - -// Wrong constant $macc -module split_shiftx_test04(i, s, o); - wire [3:0] _0_; - input [8:0] i; - output [2:0] o; - input [1:0] s; - \$macc #( - .A_WIDTH(32'd4), - .B_WIDTH(32'd0), - .CONFIG(10'h282), - .CONFIG_WIDTH(32'd10), - .Y_WIDTH(32'd4) - ) _1_ ( - .A({ 2'h2, s }), - .B(), - .Y(_0_) - ); - \$shiftx #( - .A_SIGNED(32'd0), - .A_WIDTH(32'd9), - .B_SIGNED(32'd1), - .B_WIDTH(32'd5), - .Y_WIDTH(32'd3) - ) _2_ ( - .A(i), - .B({ 1'h0, _0_ }), - .Y(o) - ); -endmodule diff --git a/tests/various/split_shiftx.ys b/tests/various/split_shiftx.ys deleted file mode 100644 index 810348aa3..000000000 --- a/tests/various/split_shiftx.ys +++ /dev/null @@ -1,21 +0,0 @@ -read_verilog -icells split_shiftx.v -split_shiftx - -cd split_shiftx_test01 -select -assert-count 3 t:$shiftx -select -assert-count 0 t: t:$shiftx %n %i - -cd split_shiftx_test02 -select -assert-count 1 t:$shiftx -select -assert-count 1 t:$macc -select -assert-count 0 t: t:$shiftx t:$macc %u %n %i - -cd split_shiftx_test03 -select -assert-count 1 t:$shiftx -select -assert-count 1 t:$macc -select -assert-count 0 t: t:$shiftx t:$macc %u %n %i - -cd split_shiftx_test04 -select -assert-count 1 t:$shiftx -select -assert-count 1 t:$macc -select -assert-count 0 t: t:$shiftx t:$macc %u %n %i From 4aca928033874e8e35ecc4a18f22475c00bebad9 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 26 Apr 2019 19:46:34 -0700 Subject: [PATCH 073/213] Fix spacing --- techlibs/xilinx/cells_map.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 258b6c3de..6c280e0f1 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -147,7 +147,7 @@ module \$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y); input A, B, C, D, E, F, G, H, S, T, U; output Y; - wire [1:0] Z; + wire [1:0] Z; assign Z = T ? (S ? {D,H} : {C,G}) : (S ? {B,F} : {A,E}); MUXF7 fpga_muxf7 (.I0(Z[0]), .I1(Z[1]), .S(U), .O(Y)); @@ -157,9 +157,9 @@ module \$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y) input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V; output Y; - wire [1:0] Z; - \$_MUX8_ fpga_mux8_0 (.A(A), .B(B), .C(C), .D(D), .E(E), .F(F), .G(G), .H(H), .S(S), .T(T), .U(U), .Y(Z[0])); - \$_MUX8_ fpga_mux8_1 (.A(I), .B(J), .C(K), .D(L), .E(M), .F(N), .G(O), .H(P), .S(S), .T(T), .U(U), .Y(Z[1])); + wire [1:0] Z; + \$_MUX8_ fpga_mux8_0 (.A(A), .B(B), .C(C), .D(D), .E(E), .F(F), .G(G), .H(H), .S(S), .T(T), .U(U), .Y(Z[0])); + \$_MUX8_ fpga_mux8_1 (.A(I), .B(J), .C(K), .D(L), .E(M), .F(N), .G(O), .H(P), .S(S), .T(T), .U(U), .Y(Z[1])); MUXF8 fpga_muxf8 (.I0(Z[0]), .I1(Z[1]), .S(V), .O(Y)); endmodule `endif // NO_MUXFN From 3b5e8c86a4516c202e877ee5ca154062682e15b9 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 2 May 2019 11:00:49 -0700 Subject: [PATCH 074/213] Fix -nocarry --- techlibs/xilinx/synth_xilinx.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index bde95c638..a0e77021a 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -241,10 +241,10 @@ struct SynthXilinxPass : public ScriptPass run("dff2dffe"); run("opt -full"); - if (!vpr || help_mode) - run("techmap -map +/xilinx/arith_map.v"); - else + if (vpr && !nocarry && !help_mode) run("techmap -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY"); + else if (!nocarry || help_mode) + run("techmap -map +/xilinx/arith_map.v", "(skip if '-nocarry')"); if (!nosrl || help_mode) { // shregmap operates on bit-level flops, not word-level, From d05ac7257e437466db0ce7f4c3264d8ad8e18fcd Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 2 May 2019 11:14:28 -0700 Subject: [PATCH 075/213] Missing help_mode --- techlibs/xilinx/synth_xilinx.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index a0e77021a..dd8b51818 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -232,7 +232,7 @@ struct SynthXilinxPass : public ScriptPass // cells for identifying variable-length shift registers, // so attempt to convert $pmux-es to the former // Also: wide multiplexer inference benefits from this too - if (!nosrl || !nomux) + if (!nosrl || !nomux || help_mode) run("pmux2shiftx", "(skip if '-nosrl' and '-nomux')"); run("opt -fast -full"); From 95867109ea4201d77a95a22f51cd3c4309ff8240 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 2 May 2019 11:25:10 -0700 Subject: [PATCH 076/213] Revert to pre-muxcover approach --- techlibs/xilinx/cells_map.v | 98 ++++++++++++++++++++++++++------- techlibs/xilinx/synth_xilinx.cc | 13 ++--- 2 files changed, 84 insertions(+), 27 deletions(-) diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index a80988480..0ec72b6a4 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -150,24 +150,84 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o endgenerate endmodule -`ifndef NO_MUXFN -module \$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y); - input A, B, C, D, E, F, G, H, S, T, U; - output Y; +module \$shiftx (A, B, Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 1; + parameter B_WIDTH = 1; + parameter Y_WIDTH = 1; - wire [1:0] Z; - assign Z = T ? (S ? {D,H} : {C,G}) : - (S ? {B,F} : {A,E}); - MUXF7 fpga_muxf7 (.I0(Z[0]), .I1(Z[1]), .S(U), .O(Y)); + input [A_WIDTH-1:0] A; + input [B_WIDTH-1:0] B; + output [Y_WIDTH-1:0] Y; + + parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0; + parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0; + + generate + genvar i, j; + if (B_SIGNED) begin + if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && _TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0) + // Optimisation to remove B_SIGNED if sign bit of B is constant-0 + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B[B_WIDTH-2:0]), .Y(Y)); + else + wire _TECHMAP_FAIL_ = 1; + end + else if (Y_WIDTH > 1) begin + for (i = 0; i < Y_WIDTH; i++) + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-Y_WIDTH+1), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A(A[A_WIDTH-Y_WIDTH+i:i]), .B(B), .Y(Y[i])); + end + // If the LSB of B is constant zero (and Y_WIDTH is 1) then + // we can optimise by removing every other entry from A + // and popping the constant zero from B + else if (_TECHMAP_CONSTMSK_B_[0] && !_TECHMAP_CONSTVAL_B_[0]) begin + wire [(A_WIDTH+1)/2-1:0] A_i; + for (i = 0; i < (A_WIDTH+1)/2; i++) + assign A_i[i] = A[i*2]; + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y)); + end + else if (B_WIDTH < 3 || A_WIDTH <= 4) begin + wire _TECHMAP_FAIL_ = 1; + end + else if (B_WIDTH == 3) begin + localparam a_width0 = 2 ** 2; + localparam a_widthN = A_WIDTH - a_width0; + wire T0, T1; + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[a_width0-1:0]), .B(B[2-1:0]), .Y(T0)); + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1)); + MUXF7 fpga_mux (.I0(T0), .I1(T1), .S(B[B_WIDTH-1]), .O(Y)); + end + else if (B_WIDTH == 4) begin + localparam a_width0 = 2 ** 2; + localparam num_mux8 = A_WIDTH / a_width0; + localparam a_widthN = A_WIDTH - num_mux8*a_width0; + wire [4-1:0] T; + wire T0, T1; + for (i = 0; i < 4; i++) + if (i < num_mux8) + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[i*a_width0+:a_width0]), .B(B[2-1:0]), .Y(T[i])); + else if (i == num_mux8 && a_widthN > 0) + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i])); + else + assign T[i] = 1'bx; + MUXF7 fpga_mux_0 (.I0(T[0]), .I1(T[1]), .S(B[2]), .O(T0)); + MUXF7 fpga_mux_1 (.I0(T[2]), .I1(T[3]), .S(B[2]), .O(T1)); + MUXF8 fpga_mux_2 (.I0(T0), .I1(T1), .S(B[3]), .O(Y)); + end + else begin + localparam a_width0 = 2 ** 4; + localparam num_mux16 = A_WIDTH / a_width0; + localparam a_widthN = A_WIDTH - num_mux16*a_width0; + wire [(2**(B_WIDTH-4))-1:0] T; + for (i = 0; i < 2 ** (B_WIDTH-4); i++) + if (i < num_mux16) + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]), .Y(T[i])); + else if (i == num_mux16 && a_widthN > 0) begin + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i])); + end + else + assign T[i] = 1'bx; + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(2**(B_WIDTH-4)), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y)); + end + endgenerate endmodule - -module \$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y); - input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V; - output Y; - - wire [1:0] Z; - \$_MUX8_ fpga_mux8_0 (.A(A), .B(B), .C(C), .D(D), .E(E), .F(F), .G(G), .H(H), .S(S), .T(T), .U(U), .Y(Z[0])); - \$_MUX8_ fpga_mux8_1 (.A(I), .B(J), .C(K), .D(L), .E(M), .F(N), .G(O), .H(P), .S(S), .T(T), .U(U), .Y(Z[1])); - MUXF8 fpga_muxf8 (.I0(Z[0]), .I1(Z[1]), .S(V), .O(Y)); -endmodule -`endif // NO_MUXFN diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index dd8b51818..7d7a05616 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -232,7 +232,7 @@ struct SynthXilinxPass : public ScriptPass // cells for identifying variable-length shift registers, // so attempt to convert $pmux-es to the former // Also: wide multiplexer inference benefits from this too - if (!nosrl || !nomux || help_mode) + if ((!nosrl && !nomux) || help_mode) run("pmux2shiftx", "(skip if '-nosrl' and '-nomux')"); run("opt -fast -full"); @@ -254,18 +254,15 @@ struct SynthXilinxPass : public ScriptPass run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')"); } + if (!nomux || help_mode) + run("techmap -map +/xilinx/cells_map.v"); + run("techmap"); run("opt -fast"); - - if (!nomux || help_mode) - run("muxcover -mux8 -mux16"); } if (check_label("map_cells")) { - std::string define; - if (nomux) - define += " -D NO_MUXFN"; - run("techmap -map +/techmap.v -map +/xilinx/cells_map.v" + define); + run("techmap -map +/techmap.v -map +/xilinx/cells_map.v"); run("clean"); } From d80445e0492c67b63435880b3bca4ccbf6f3db43 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 2 May 2019 11:35:57 -0700 Subject: [PATCH 077/213] Use new peepopt from #969 --- techlibs/xilinx/synth_xilinx.cc | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 7d7a05616..a1c4acf7e 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -211,6 +211,18 @@ struct SynthXilinxPass : public ScriptPass if (check_label("coarse")) { run("synth -run coarse"); + + // shregmap -tech xilinx can cope with $shiftx and $mux + // cells for identifying variable-length shift registers, + // so attempt to convert $pmux-es to the former + // Also: wide multiplexer inference benefits from this too + if ((!nosrl && !nomux) || help_mode) + run("pmux2shiftx", "(skip if '-nosrl' and '-nomux')"); + + // Run a number of peephole optimisations, including one + // that optimises $mul cells driving $shiftx's B input + // and that aids wide mux analysis + run("peepopt"); } if (check_label("bram", "(skip if '-nobram')")) { @@ -228,13 +240,6 @@ struct SynthXilinxPass : public ScriptPass } if (check_label("fine")) { - // shregmap -tech xilinx can cope with $shiftx and $mux - // cells for identifying variable-length shift registers, - // so attempt to convert $pmux-es to the former - // Also: wide multiplexer inference benefits from this too - if ((!nosrl && !nomux) || help_mode) - run("pmux2shiftx", "(skip if '-nosrl' and '-nomux')"); - run("opt -fast -full"); run("memory_map"); run("dffsr2dff"); @@ -246,6 +251,9 @@ struct SynthXilinxPass : public ScriptPass else if (!nocarry || help_mode) run("techmap -map +/xilinx/arith_map.v", "(skip if '-nocarry')"); + if (!nomux || help_mode) + run("techmap -map +/xilinx/cells_map.v"); + if (!nosrl || help_mode) { // shregmap operates on bit-level flops, not word-level, // so break those down here @@ -254,9 +262,6 @@ struct SynthXilinxPass : public ScriptPass run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')"); } - if (!nomux || help_mode) - run("techmap -map +/xilinx/cells_map.v"); - run("techmap"); run("opt -fast"); } From fc72f07efdfbc1b87c4838af6138cdaa3cfd97ff Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 2 May 2019 15:01:37 -0700 Subject: [PATCH 078/213] Add don't care optimisation --- techlibs/xilinx/cells_map.v | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 0ec72b6a4..ecfbe2555 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -161,11 +161,14 @@ module \$shiftx (A, B, Y); input [B_WIDTH-1:0] B; output [Y_WIDTH-1:0] Y; + parameter [A_WIDTH-1:0] _TECHMAP_CONSTMSK_A_ = 0; + parameter [A_WIDTH-1:0] _TECHMAP_CONSTVAL_A_ = 0; parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0; parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0; generate genvar i, j; + // TODO: Check if this opt still necessary if (B_SIGNED) begin if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && _TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0) // Optimisation to remove B_SIGNED if sign bit of B is constant-0 @@ -186,6 +189,14 @@ module \$shiftx (A, B, Y); assign A_i[i] = A[i*2]; \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y)); end + // If upper half of A input is all constant 1'bx then + // chop this $shiftx in half + else if (_TECHMAP_CONSTMSK_A_[A_WIDTH-1:2**(B_WIDTH-1)] == {A_WIDTH-2**(B_WIDTH-1){1'b1}} && _TECHMAP_CONSTVAL_A_[A_WIDTH-1:2**(B_WIDTH-1)] === {A_WIDTH-2**(B_WIDTH-1){1'bx}}) begin + if (B_WIDTH > 1) + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(2**(B_WIDTH-1)), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A[2**(B_WIDTH-1)-1:0]), .B(B[B_WIDTH-2:0]), .Y(Y)); + else + assign Y = A[0]; + end else if (B_WIDTH < 3 || A_WIDTH <= 4) begin wire _TECHMAP_FAIL_ = 1; end From 283e33ba5aad3a66bd14c30e1f52361c5f4c9789 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 2 May 2019 16:02:37 -0700 Subject: [PATCH 079/213] Trim off leading 1'bx in A --- techlibs/xilinx/cells_map.v | 27 ++++++++++++++++++++------- 1 file changed, 20 insertions(+), 7 deletions(-) diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index ecfbe2555..729cda139 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -166,6 +166,20 @@ module \$shiftx (A, B, Y); parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0; parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0; + function integer compute_num_leading_X_in_A; + integer i, c; + begin + compute_num_leading_X_in_A = 0; + c = 1; + for (i = A_WIDTH-1; i >= 0; i=i-1) begin + if (!_TECHMAP_CONSTMSK_A_[i] || _TECHMAP_CONSTVAL_A_[i] !== 1'bx) + c = 0; + compute_num_leading_X_in_A = compute_num_leading_X_in_A + c; + end + end + endfunction + localparam num_leading_X_in_A = compute_num_leading_X_in_A(); + generate genvar i, j; // TODO: Check if this opt still necessary @@ -176,6 +190,7 @@ module \$shiftx (A, B, Y); else wire _TECHMAP_FAIL_ = 1; end + // Bit-blast else if (Y_WIDTH > 1) begin for (i = 0; i < Y_WIDTH; i++) \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-Y_WIDTH+1), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A(A[A_WIDTH-Y_WIDTH+i:i]), .B(B), .Y(Y[i])); @@ -189,13 +204,11 @@ module \$shiftx (A, B, Y); assign A_i[i] = A[i*2]; \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y)); end - // If upper half of A input is all constant 1'bx then - // chop this $shiftx in half - else if (_TECHMAP_CONSTMSK_A_[A_WIDTH-1:2**(B_WIDTH-1)] == {A_WIDTH-2**(B_WIDTH-1){1'b1}} && _TECHMAP_CONSTVAL_A_[A_WIDTH-1:2**(B_WIDTH-1)] === {A_WIDTH-2**(B_WIDTH-1){1'bx}}) begin - if (B_WIDTH > 1) - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(2**(B_WIDTH-1)), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A[2**(B_WIDTH-1)-1:0]), .B(B[B_WIDTH-2:0]), .Y(Y)); - else - assign Y = A[0]; + // Trim off any leading 1'bx -es in A, and resize B accordingly + else if (num_leading_X_in_A > 0) begin + localparam A_WIDTH_new = A_WIDTH - num_leading_X_in_A; + localparam B_WIDTH_new = $clog2(A_WIDTH_new); + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH_new), .B_WIDTH(B_WIDTH_new), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A[A_WIDTH_new-1:0]), .B(B[B_WIDTH_new-1:0]), .Y(Y)); end else if (B_WIDTH < 3 || A_WIDTH <= 4) begin wire _TECHMAP_FAIL_ = 1; From 36a219063ad7b4e70581bf83a00365db764737bf Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 21 May 2019 14:31:19 -0700 Subject: [PATCH 080/213] Modify LUT area cost to be same as old abc --- techlibs/xilinx/abc.lut | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/techlibs/xilinx/abc.lut b/techlibs/xilinx/abc.lut index c6bc7b1f7..c53cd50a1 100644 --- a/techlibs/xilinx/abc.lut +++ b/techlibs/xilinx/abc.lut @@ -1,12 +1,11 @@ -# Max delays from https://pastebin.com/v2hrcksd -# from https://github.com/SymbiFlow/prjxray/pull/706#issuecomment-479380321 +# Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf # K area delay -1 11 624 -2 12 624 -3 13 624 -4 14 624 -5 15 624 -6 20 724 -7 40 1020 -8 80 1293 +1 1 624 +2 2 624 +3 3 624 +4 3 624 +5 3 624 +6 5 724 +7 10 1020 +8 20 1293 From 0f094fba08b69baa2329e749daf19f41a624a0a0 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 21 May 2019 16:19:23 -0700 Subject: [PATCH 081/213] Pad all boxes so that all input/output connections specified --- backends/aiger/xaiger.cc | 91 ++++++++++++++++++++++++++++++---------- 1 file changed, 68 insertions(+), 23 deletions(-) diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index f9d874e2d..676311440 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -301,6 +301,35 @@ struct XAigerWriter if (!box_module || !box_module->attributes.count("\\abc_box_id")) continue; + // Fully pad all unused input connections of this box cell with S0 + // Fully pad all undriven output connections of thix box cell with anonymous wires + for (const auto w : box_module->wires()) { + if (w->port_input) { + auto it = cell->connections_.find(w->name); + if (it != cell->connections_.end()) { + if (GetSize(it->second) < GetSize(w)) { + RTLIL::SigSpec padded_connection(RTLIL::S0, GetSize(w)-GetSize(it->second)); + padded_connection.append(it->second); + it->second = std::move(padded_connection); + } + } + else + cell->connections_[w->name] = RTLIL::SigSpec(RTLIL::S0, GetSize(w)); + } + if (w->port_output) { + auto it = cell->connections_.find(w->name); + if (it != cell->connections_.end()) { + if (GetSize(it->second) < GetSize(w)) { + RTLIL::SigSpec padded_connection = module->addWire(NEW_ID, GetSize(w)-GetSize(it->second)); + padded_connection.append(it->second); + it->second = std::move(padded_connection); + } + } + else + cell->connections_[w->name] = module->addWire(NEW_ID, GetSize(w)); + } + } + // Box ordering is alphabetical cell->connections_.sort(RTLIL::sort_by_id_str()); for (const auto &c : cell->connections()) { @@ -646,37 +675,53 @@ struct XAigerWriter RTLIL::Module *holes_module = nullptr; holes_module = module->design->addModule("\\__holes__"); + log_assert(holes_module); + dict> box_io; for (auto cell : box_list) { - int box_inputs = 0, box_outputs = 0; - int box_id = module->design->module(cell->type)->attributes.at("\\abc_box_id").as_int(); + RTLIL::Module* box_module = module->design->module(cell->type); + int box_id = box_module->attributes.at("\\abc_box_id").as_int(); Cell *holes_cell = nullptr; - if (holes_module && !holes_module->cell(stringf("\\u%d", box_id))) + int box_inputs = 0, box_outputs = 0; + + auto it = box_io.find(cell->type); + if (it == box_io.end()) { holes_cell = holes_module->addCell(stringf("\\u%d", box_id), cell->type); - RTLIL::Wire *holes_wire; - // NB: cell->connections_ already sorted from before - for (const auto &c : cell->connections()) { - log_assert(c.second.size() == 1); - if (cell->input(c.first)) { - box_inputs += c.second.size(); - if (holes_cell) { - holes_wire = holes_module->wire(stringf("\\i%d", box_inputs)); - if (!holes_wire) { - holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs)); - holes_wire->port_input = true; + + RTLIL::Wire *holes_wire; + box_module->wires_.sort(RTLIL::sort_by_id_str()); + for (const auto w : box_module->wires()) { + RTLIL::SigSpec port_wire; + if (w->port_input) { + for (int i = 0; i < GetSize(w); i++) { + box_inputs++; + holes_wire = holes_module->wire(stringf("\\i%d", box_inputs)); + if (!holes_wire) { + holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs)); + holes_wire->port_input = true; + } + port_wire.append(holes_wire); } - holes_cell->setPort(c.first, holes_wire); - } - } - if (cell->output(c.first)) { - box_outputs += c.second.size(); - if (holes_cell) { - holes_wire = holes_module->addWire(stringf("\\%s.%s", cell->type.c_str(), c.first.c_str())); - holes_wire->port_output = true; - holes_cell->setPort(c.first, holes_wire); + holes_cell->setPort(w->name, holes_wire); + } + if (w->port_output) { + box_outputs += GetSize(w); + for (int i = 0; i < GetSize(w); i++) { + if (GetSize(w) == 1) + holes_wire = holes_module->addWire(stringf("%s.%s", cell->type.c_str(), w->name.c_str())); + else + holes_wire = holes_module->addWire(stringf("%s.%s[%d]", cell->type.c_str(), w->name.c_str(), i)); + holes_wire->port_output = true; + port_wire.append(holes_wire); + } + holes_cell->setPort(w->name, holes_wire); } } + box_io[cell->type] = std::make_pair(box_inputs,box_outputs); } + else + std::tie(box_inputs,box_outputs) = it->second; + write_h_buffer(box_inputs); write_h_buffer(box_outputs); write_h_buffer(box_id); From ee8435b820bbea4a4ceb2c46a81de9d03d4aa44c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 21 May 2019 16:19:45 -0700 Subject: [PATCH 082/213] Instead of MUXCY/XORCY use CARRY4 (with timing) --- techlibs/xilinx/abc.box | 22 +++++++++++++++------- techlibs/xilinx/arith_map.v | 4 ++-- techlibs/xilinx/cells_sim.v | 3 +-- techlibs/xilinx/synth_xilinx.cc | 2 ++ 4 files changed, 20 insertions(+), 11 deletions(-) diff --git a/techlibs/xilinx/abc.box b/techlibs/xilinx/abc.box index d572817df..57ea1670c 100644 --- a/techlibs/xilinx/abc.box +++ b/techlibs/xilinx/abc.box @@ -1,5 +1,4 @@ -# Max delays from https://pastebin.com/v2hrcksd -# from https://github.com/SymbiFlow/prjxray/pull/706#issuecomment-479380321 +# Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf # F7BMUX slower than F7AMUX # Inputs: I0 I1 S0 @@ -12,8 +11,17 @@ F7BMUX 1 1 3 1 MUXF8 2 1 3 1 104 94 273 -MUXCY 3 1 3 1 -1 1 1 - -XORCY 4 1 2 1 -1 1 +# CARRY4 + CARRY4_[ABCD]X +# Inputs: CI CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 +# Outputs: CO0 CO1 CO2 CO3 O0 O1 O2 O3 +CARRY4 3 1 10 8 +271 157 228 114 222 334 239 313 +536 494 592 580 482 598 584 642 +379 465 540 526 - 407 556 615 +- 445 520 507 - - 537 596 +- - 356 398 - - - 438 +- - - 385 - - - - +340 433 512 508 223 400 523 582 +- 469 548 528 - 205 558 618 +- - 292 376 - - 226 330 +- - - 380 - - - 227 diff --git a/techlibs/xilinx/arith_map.v b/techlibs/xilinx/arith_map.v index 09a5f07e8..5c848d4e6 100644 --- a/techlibs/xilinx/arith_map.v +++ b/techlibs/xilinx/arith_map.v @@ -180,7 +180,7 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO); // First one if (i == 0) begin - CARRY4 #(.IS_INITIALIZED(1'd1)) carry4_1st_part + CARRY4 carry4_1st_part ( .CYINIT(CI), .CI (1'd0), @@ -207,7 +207,7 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO); // First one if (i == 0) begin - CARRY4 #(.IS_INITIALIZED(1'd1)) carry4_1st_full + CARRY4 carry4_1st_full ( .CYINIT(CI), .CI (1'd0), diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 8b231480f..9db52b67a 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -155,7 +155,6 @@ module LUT6_2(output O6, output O5, input I0, I1, I2, I3, I4, I5); assign O5 = I0 ? s5_1[1] : s5_1[0]; endmodule -(* abc_box_id = 3, lib_whitebox *) module MUXCY(output O, input CI, DI, S); assign O = S ? CI : DI; endmodule @@ -170,11 +169,11 @@ module MUXF8(output O, input I0, I1, S); assign O = S ? I1 : I0; endmodule -(* abc_box_id = 4, lib_whitebox *) module XORCY(output O, input CI, LI); assign O = CI ^ LI; endmodule +(* abc_box_id = 3, lib_whitebox *) module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S); assign O = S ^ {CO[2:0], CI | CYINIT}; assign CO[0] = S[0] ? CI | CYINIT : DI[0]; diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index e9a3b53a0..ec7768ffe 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -261,6 +261,8 @@ struct SynthXilinxPass : public ScriptPass if (vpr && !nocarry && !help_mode) run("techmap -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY"); + else if (abc == "abc9" && !nocarry && !help_mode) + run("techmap -map +/xilinx/arith_map.v -D _CLB_CARRY", "(skip if '-nocarry')"); else if (!nocarry || help_mode) run("techmap -map +/xilinx/arith_map.v", "(skip if '-nocarry')"); From 9b1078b9bde70141514488acd01bb32b5422f9bd Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 21 May 2019 18:50:02 -0700 Subject: [PATCH 083/213] Fix/workaround symptom unveiled by #1023 --- techlibs/xilinx/cells_map.v | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index f566a8584..af6414667 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -220,7 +220,10 @@ module \$shiftx (A, B, Y); localparam a_widthN = A_WIDTH - a_width0; wire T0, T1; \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[a_width0-1:0]), .B(B[2-1:0]), .Y(T0)); - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1)); + if (a_widthN > 1) + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1)); + else + assign T1 = A[A_WIDTH-1]; MUXF7 fpga_mux (.I0(T0), .I1(T1), .S(B[B_WIDTH-1]), .O(Y)); end else if (B_WIDTH == 4) begin @@ -232,8 +235,12 @@ module \$shiftx (A, B, Y); for (i = 0; i < 4; i++) if (i < num_mux8) \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[i*a_width0+:a_width0]), .B(B[2-1:0]), .Y(T[i])); - else if (i == num_mux8 && a_widthN > 0) - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i])); + else if (i == num_mux8 && a_widthN > 0) begin + if (a_widthN > 1) + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i])); + else + assign T[i] = A[A_WIDTH-1]; + end else assign T[i] = 1'bx; MUXF7 fpga_mux_0 (.I0(T[0]), .I1(T[1]), .S(B[2]), .O(T0)); @@ -249,7 +256,10 @@ module \$shiftx (A, B, Y); if (i < num_mux16) \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]), .Y(T[i])); else if (i == num_mux16 && a_widthN > 0) begin - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i])); + if (a_widthN > 1) + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i])); + else + assign T[i] = A[A_WIDTH-1]; end else assign T[i] = 1'bx; From 4f44e3399ba6c959c830943c44c4ad728be895fa Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 22 May 2019 02:36:28 -0700 Subject: [PATCH 084/213] shift register inference before mux --- techlibs/xilinx/synth_xilinx.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index ec7768ffe..3cee81a7b 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -266,9 +266,6 @@ struct SynthXilinxPass : public ScriptPass else if (!nocarry || help_mode) run("techmap -map +/xilinx/arith_map.v", "(skip if '-nocarry')"); - if (!nomux || help_mode) - run("techmap -map +/xilinx/cells_map.v"); - if (!nosrl || help_mode) { // shregmap operates on bit-level flops, not word-level, // so break those down here @@ -277,6 +274,9 @@ struct SynthXilinxPass : public ScriptPass run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')"); } + if (!nomux || help_mode) + run("techmap -map +/xilinx/cells_map.v"); + run("techmap"); run("opt -fast"); } From ae89e6ab26d2d87a604e20ebc14dcda8c9901585 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 23 May 2019 08:58:57 -0700 Subject: [PATCH 085/213] Add whitebox support to DRAM --- techlibs/xilinx/abc.box | 14 ++++++++++++++ techlibs/xilinx/cells_sim.v | 10 ++++++++-- techlibs/xilinx/cells_xtra.sh | 4 ++-- techlibs/xilinx/cells_xtra.v | 18 ------------------ techlibs/xilinx/synth_xilinx.cc | 4 ++-- 5 files changed, 26 insertions(+), 24 deletions(-) diff --git a/techlibs/xilinx/abc.box b/techlibs/xilinx/abc.box index 57ea1670c..92ea5537b 100644 --- a/techlibs/xilinx/abc.box +++ b/techlibs/xilinx/abc.box @@ -25,3 +25,17 @@ CARRY4 3 1 10 8 - 469 548 528 - 205 558 618 - - 292 376 - - 226 330 - - - 380 - - - 227 + +# SLICEM/A6LUT +# Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE +# Outputs: DPO SPO +RAM64X1D 4 1 15 2 +- - - - - - - 124 124 124 124 124 124 - - +124 124 124 124 124 124 - - - - - - 124 - - + +# SLICEM/A6LUT + F7[AB]MUX +# Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE +# Outputs: DPO SPO +RAM128X1D 5 1 17 2 +- - - - - - - - 314 314 314 314 314 314 292 - - +347 347 347 347 347 347 296 - - - - - - - - - - diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 9db52b67a..29c79f689 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -281,8 +281,9 @@ module FDPE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, PRE); always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; endmodule +(* abc_box_id = 4, lib_whitebox *) module RAM64X1D ( - (* abc_flop_q *) output DPO, SPO, + output DPO, SPO, input D, WCLK, WE, input A0, A1, A2, A3, A4, A5, input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5 @@ -294,12 +295,15 @@ module RAM64X1D ( reg [63:0] mem = INIT; assign SPO = mem[a]; assign DPO = mem[dpra]; +`ifndef _ABC wire clk = WCLK ^ IS_WCLK_INVERTED; always @(posedge clk) if (WE) mem[a] <= D; +`endif endmodule +(* abc_box_id = 5, lib_whitebox *) module RAM128X1D ( - (* abc_flop_q *) output DPO, SPO, + output DPO, SPO, input D, WCLK, WE, input [6:0] A, DPRA ); @@ -308,8 +312,10 @@ module RAM128X1D ( reg [127:0] mem = INIT; assign SPO = mem[A]; assign DPO = mem[DPRA]; +`ifndef _ABC wire clk = WCLK ^ IS_WCLK_INVERTED; always @(posedge clk) if (WE) mem[A] <= D; +`endif endmodule module SRL16E ( diff --git a/techlibs/xilinx/cells_xtra.sh b/techlibs/xilinx/cells_xtra.sh index 8e39b440d..e3b847c36 100644 --- a/techlibs/xilinx/cells_xtra.sh +++ b/techlibs/xilinx/cells_xtra.sh @@ -116,7 +116,7 @@ function xtract_cell_decl() xtract_cell_decl PS7 "(* keep *)" xtract_cell_decl PULLDOWN xtract_cell_decl PULLUP - xtract_cell_decl RAM128X1D + #xtract_cell_decl RAM128X1D xtract_cell_decl RAM128X1S xtract_cell_decl RAM256X1S xtract_cell_decl RAM32M @@ -125,7 +125,7 @@ function xtract_cell_decl() xtract_cell_decl RAM32X1S_1 xtract_cell_decl RAM32X2S xtract_cell_decl RAM64M - xtract_cell_decl RAM64X1D + x#tract_cell_decl RAM64X1D xtract_cell_decl RAM64X1S xtract_cell_decl RAM64X1S_1 xtract_cell_decl RAM64X2S diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v index fbcc74682..0ec3d0df0 100644 --- a/techlibs/xilinx/cells_xtra.v +++ b/techlibs/xilinx/cells_xtra.v @@ -3655,17 +3655,6 @@ module PULLUP (...); output O; endmodule -module RAM128X1D (...); - parameter [127:0] INIT = 128'h00000000000000000000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output DPO, SPO; - input [6:0] A; - input [6:0] DPRA; - input D; - input WCLK; - input WE; -endmodule - module RAM128X1S (...); parameter [127:0] INIT = 128'h00000000000000000000000000000000; parameter [0:0] IS_WCLK_INVERTED = 1'b0; @@ -3756,13 +3745,6 @@ module RAM64M (...); input WE; endmodule -module RAM64X1D (...); - parameter [63:0] INIT = 64'h0000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output DPO, SPO; - input A0, A1, A2, A3, A4, A5, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5, WCLK, WE; -endmodule - module RAM64X1S (...); parameter [63:0] INIT = 64'h0000000000000000; parameter [0:0] IS_WCLK_INVERTED = 1'b0; diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 3cee81a7b..ecfb94610 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -203,9 +203,9 @@ struct SynthXilinxPass : public ScriptPass { if (check_label("begin")) { if (vpr) - run("read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v"); + run("read_verilog -lib -D_ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v"); else - run("read_verilog -lib +/xilinx/cells_sim.v"); + run("read_verilog -lib -D_ABC +/xilinx/cells_sim.v"); run("read_verilog -lib +/xilinx/cells_xtra.v"); From 60af2ca94de482f09aaaa7d6eed66c299248f8f1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 24 May 2019 14:09:15 -0700 Subject: [PATCH 086/213] Transpose CARRY4 delays --- techlibs/xilinx/abc.box | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/techlibs/xilinx/abc.box b/techlibs/xilinx/abc.box index 92ea5537b..9653fe5b8 100644 --- a/techlibs/xilinx/abc.box +++ b/techlibs/xilinx/abc.box @@ -15,16 +15,14 @@ MUXF8 2 1 3 1 # Inputs: CI CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 # Outputs: CO0 CO1 CO2 CO3 O0 O1 O2 O3 CARRY4 3 1 10 8 -271 157 228 114 222 334 239 313 -536 494 592 580 482 598 584 642 -379 465 540 526 - 407 556 615 -- 445 520 507 - - 537 596 -- - 356 398 - - - 438 -- - - 385 - - - - -340 433 512 508 223 400 523 582 -- 469 548 528 - 205 558 618 -- - 292 376 - - 226 330 -- - - 380 - - - 227 +271 536 379 - - - 340 - - - +157 494 465 445 - - 433 469 - - +228 592 540 520 356 - 512 548 292 - +114 580 526 507 398 385 508 528 378 380 +222 482 - - - - 223 - - - +334 598 407 - - - 400 205 - - +239 584 556 537 - - 523 558 226 - +313 642 615 596 438 - 582 618 330 227 # SLICEM/A6LUT # Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE From 6ad09bfcea4711eaff609a4e804e29fa888d4b14 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 24 May 2019 15:10:18 -0700 Subject: [PATCH 087/213] Add &fraig and &mfs back --- passes/techmap/abc9.cc | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 3cee5a586..9f3d2287b 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -25,8 +25,7 @@ #define ABC_COMMAND_LIB "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put" #define ABC_COMMAND_CTR "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put; buffer; upsize {D}; dnsize {D}; stime -p" //#define ABC_COMMAND_LUT "strash; ifraig; scorr; dc2; dretime; strash; dch -f; if; mfs2" -//#define ABC_COMMAND_LUT "&st; &sweep; &scorr; &dc2; &retime; &dch -f; &if; &mfs; &ps" -#define ABC_COMMAND_LUT "&st; &scorr; &dc2; &retime; &dch -f; &if; &ps -l -m" +#define ABC_COMMAND_LUT "&st; &fraig; &scorr; &dc2; &retime; &dch -f; &if; &mfs; &ps -l -m" #define ABC_COMMAND_SOP "strash; ifraig; scorr; dc2; dretime; strash; dch -f; cover {I} {P}" #define ABC_COMMAND_DFL "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put" From ca5774ed40db8dafe3696deb9fe9827d7196d7bf Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 24 May 2019 20:39:55 -0700 Subject: [PATCH 088/213] Try new LUT delays --- techlibs/xilinx/abc.lut | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/techlibs/xilinx/abc.lut b/techlibs/xilinx/abc.lut index c53cd50a1..438ed0368 100644 --- a/techlibs/xilinx/abc.lut +++ b/techlibs/xilinx/abc.lut @@ -1,11 +1,14 @@ # Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf # K area delay -1 1 624 -2 2 624 -3 3 624 -4 3 624 -5 3 624 -6 5 724 -7 10 1020 -8 20 1293 +1 1 248 +2 2 248 372 +3 3 248 372 496 +4 3 248 372 496 620 +5 3 248 372 496 620 744 +6 5 124 248 372 496 620 744 + # F7BMUX +7 10 296 420 544 668 792 916 1040 + # F8MUX + # F8MUX+F7BMUX +8 20 273 569 693 817 941 1065 1189 1313 From 01684643b6edd4290701b2e08114cb731db5f446 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 25 May 2019 22:34:50 -0700 Subject: [PATCH 089/213] Fix "write_xaiger", and to write each box contents into holes --- backends/aiger/xaiger.cc | 103 ++++++++++++++++++++++++--------------- 1 file changed, 63 insertions(+), 40 deletions(-) diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 676311440..7e674cb87 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -385,8 +385,9 @@ struct XAigerWriter // Do some CI/CO post-processing: // Erase all POs that are undriven - for (auto bit : undriven_bits) - output_bits.erase(bit); + if (!holes_mode) + for (auto bit : undriven_bits) + output_bits.erase(bit); // CIs cannot be undriven for (const auto &c : ci_bits) undriven_bits.erase(c.first); @@ -676,55 +677,45 @@ struct XAigerWriter RTLIL::Module *holes_module = nullptr; holes_module = module->design->addModule("\\__holes__"); log_assert(holes_module); - dict> box_io; for (auto cell : box_list) { RTLIL::Module* box_module = module->design->module(cell->type); - int box_id = box_module->attributes.at("\\abc_box_id").as_int(); - Cell *holes_cell = nullptr; int box_inputs = 0, box_outputs = 0; + Cell *holes_cell = holes_module->addCell(cell->name, cell->type); - auto it = box_io.find(cell->type); - if (it == box_io.end()) { - holes_cell = holes_module->addCell(stringf("\\u%d", box_id), cell->type); - - RTLIL::Wire *holes_wire; - box_module->wires_.sort(RTLIL::sort_by_id_str()); - for (const auto w : box_module->wires()) { - RTLIL::SigSpec port_wire; - if (w->port_input) { - for (int i = 0; i < GetSize(w); i++) { - box_inputs++; - holes_wire = holes_module->wire(stringf("\\i%d", box_inputs)); - if (!holes_wire) { - holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs)); - holes_wire->port_input = true; - } - port_wire.append(holes_wire); + RTLIL::Wire *holes_wire; + box_module->wires_.sort(RTLIL::sort_by_id_str()); + for (const auto w : box_module->wires()) { + RTLIL::SigSpec port_wire; + if (w->port_input) { + for (int i = 0; i < GetSize(w); i++) { + box_inputs++; + holes_wire = holes_module->wire(stringf("\\i%d", box_inputs)); + if (!holes_wire) { + holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs)); + holes_wire->port_input = true; } - holes_cell->setPort(w->name, holes_wire); - } - if (w->port_output) { - box_outputs += GetSize(w); - for (int i = 0; i < GetSize(w); i++) { - if (GetSize(w) == 1) - holes_wire = holes_module->addWire(stringf("%s.%s", cell->type.c_str(), w->name.c_str())); - else - holes_wire = holes_module->addWire(stringf("%s.%s[%d]", cell->type.c_str(), w->name.c_str(), i)); - holes_wire->port_output = true; - port_wire.append(holes_wire); - } - holes_cell->setPort(w->name, holes_wire); + port_wire.append(holes_wire); } + holes_cell->setPort(w->name, port_wire); + } + if (w->port_output) { + box_outputs += GetSize(w); + for (int i = 0; i < GetSize(w); i++) { + if (GetSize(w) == 1) + holes_wire = holes_module->addWire(stringf("%s.%s", cell->name.c_str(), w->name.c_str())); + else + holes_wire = holes_module->addWire(stringf("%s.%s[%d]", cell->name.c_str(), w->name.c_str(), i)); + holes_wire->port_output = true; + port_wire.append(holes_wire); + } + holes_cell->setPort(w->name, port_wire); } - box_io[cell->type] = std::make_pair(box_inputs,box_outputs); } - else - std::tie(box_inputs,box_outputs) = it->second; write_h_buffer(box_inputs); write_h_buffer(box_outputs); - write_h_buffer(box_id); + write_h_buffer(box_module->attributes.at("\\abc_box_id").as_int()); write_h_buffer(0 /* OldBoxNum */); } @@ -746,7 +737,16 @@ struct XAigerWriter RTLIL::Selection& sel = holes_module->design->selection_stack.back(); sel.select(holes_module); - Pass::call(holes_module->design, "flatten -wb; aigmap; clean -purge"); + // TODO: Should not need to opt_merge if we only instantiate + // each box type once... + Pass::call(holes_module->design, "opt_merge -share_all"); + + Pass::call(holes_module->design, "flatten -wb;"); + + // TODO: Should techmap all lib_whitebox-es once + Pass::call(holes_module->design, "techmap;"); + + Pass::call(holes_module->design, "aigmap; clean -purge"); holes_module->design->selection_stack.pop_back(); @@ -766,6 +766,29 @@ struct XAigerWriter f.write(buffer_str.data(), buffer_str.size()); holes_module->design->remove(holes_module); } + + std::stringstream r_buffer; + auto write_r_buffer = [&r_buffer](int i32) { + // TODO: Don't assume we're on little endian +#ifdef _WIN32 + int i32_be = _byteswap_ulong(i32); +#else + int i32_be = __builtin_bswap32(i32); +#endif + r_buffer.write(reinterpret_cast(&i32_be), sizeof(i32_be)); + }; + write_r_buffer(0); + + f << "r"; + buffer_str = r_buffer.str(); + // TODO: Don't assume we're on little endian +#ifdef _WIN32 + buffer_size_be = _byteswap_ulong(buffer_str.size()); +#else + buffer_size_be = __builtin_bswap32(buffer_str.size()); +#endif + f.write(reinterpret_cast(&buffer_size_be), sizeof(buffer_size_be)); + f.write(buffer_str.data(), buffer_str.size()); } f << stringf("Generated by %s\n", yosys_version_str); From 32a4c10c0df7e82c69b0d96a63be0c5267d33257 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sun, 26 May 2019 02:44:36 -0700 Subject: [PATCH 090/213] Fix "a" extension --- backends/aiger/xaiger.cc | 26 ++++++++++++++++++-------- passes/techmap/abc9.cc | 4 +++- 2 files changed, 21 insertions(+), 9 deletions(-) diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 7e674cb87..3d275214b 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -681,9 +681,12 @@ struct XAigerWriter for (auto cell : box_list) { RTLIL::Module* box_module = module->design->module(cell->type); int box_inputs = 0, box_outputs = 0; - Cell *holes_cell = holes_module->addCell(cell->name, cell->type); + Cell *holes_cell = nullptr; + if (box_module->get_bool_attribute("\\whitebox")) + holes_cell = holes_module->addCell(cell->name, cell->type); RTLIL::Wire *holes_wire; + // TODO: Only sort once box_module->wires_.sort(RTLIL::sort_by_id_str()); for (const auto w : box_module->wires()) { RTLIL::SigSpec port_wire; @@ -695,9 +698,11 @@ struct XAigerWriter holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs)); holes_wire->port_input = true; } - port_wire.append(holes_wire); + if (holes_cell) + port_wire.append(holes_wire); } - holes_cell->setPort(w->name, port_wire); + if (!port_wire.empty()) + holes_cell->setPort(w->name, port_wire); } if (w->port_output) { box_outputs += GetSize(w); @@ -707,9 +712,13 @@ struct XAigerWriter else holes_wire = holes_module->addWire(stringf("%s.%s[%d]", cell->name.c_str(), w->name.c_str(), i)); holes_wire->port_output = true; - port_wire.append(holes_wire); + if (holes_cell) + port_wire.append(holes_wire); + else + holes_module->connect(holes_wire, RTLIL::S0); } - holes_cell->setPort(w->name, port_wire); + if (!port_wire.empty()) + holes_cell->setPort(w->name, port_wire); } } @@ -741,12 +750,13 @@ struct XAigerWriter // each box type once... Pass::call(holes_module->design, "opt_merge -share_all"); - Pass::call(holes_module->design, "flatten -wb;"); + Pass::call(holes_module->design, "flatten -wb"); // TODO: Should techmap all lib_whitebox-es once - Pass::call(holes_module->design, "techmap;"); + //Pass::call(holes_module->design, "techmap"); - Pass::call(holes_module->design, "aigmap; clean -purge"); + Pass::call(holes_module->design, "aigmap"); + Pass::call(holes_module->design, "clean -purge"); holes_module->design->selection_stack.pop_back(); diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 9f3d2287b..3c0132135 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -25,7 +25,9 @@ #define ABC_COMMAND_LIB "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put" #define ABC_COMMAND_CTR "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put; buffer; upsize {D}; dnsize {D}; stime -p" //#define ABC_COMMAND_LUT "strash; ifraig; scorr; dc2; dretime; strash; dch -f; if; mfs2" -#define ABC_COMMAND_LUT "&st; &fraig; &scorr; &dc2; &retime; &dch -f; &if; &mfs; &ps -l -m" +//#define ABC_COMMAND_LUT "&st; &sweep -v; &ps -l -m; &scorr; &dc2; &retime; &dch -f; &if; &mfs; &ps -l -m" +#define ABC_COMMAND_LUT "&st; "/*"&sweep; "*/"&scorr; "/*"dc2; "*/"&retime; &dch -f; &ps -l -m; &if; &ps -l -m" +//#define ABC_COMMAND_LUT "&st; &scorr; &dc2; &retime; &dch -f; &if; &mfs; &ps -l -m" #define ABC_COMMAND_SOP "strash; ifraig; scorr; dc2; dretime; strash; dch -f; cover {I} {P}" #define ABC_COMMAND_DFL "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put" From 823153e418e743852ee927f797c3cc5bb81d19c9 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sun, 26 May 2019 02:47:06 -0700 Subject: [PATCH 091/213] Combine ABC_COMMAND_LUT --- passes/techmap/abc9.cc | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 3c0132135..118bdf37b 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -25,8 +25,7 @@ #define ABC_COMMAND_LIB "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put" #define ABC_COMMAND_CTR "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put; buffer; upsize {D}; dnsize {D}; stime -p" //#define ABC_COMMAND_LUT "strash; ifraig; scorr; dc2; dretime; strash; dch -f; if; mfs2" -//#define ABC_COMMAND_LUT "&st; &sweep -v; &ps -l -m; &scorr; &dc2; &retime; &dch -f; &if; &mfs; &ps -l -m" -#define ABC_COMMAND_LUT "&st; "/*"&sweep; "*/"&scorr; "/*"dc2; "*/"&retime; &dch -f; &ps -l -m; &if; &ps -l -m" +#define ABC_COMMAND_LUT "&st; "/*"&sweep -v; "*/"&scorr; "/*"dc2; "*/"&retime; &dch -f; &ps -l -m; &if; &ps -l -m" //#define ABC_COMMAND_LUT "&st; &scorr; &dc2; &retime; &dch -f; &if; &mfs; &ps -l -m" #define ABC_COMMAND_SOP "strash; ifraig; scorr; dc2; dretime; strash; dch -f; cover {I} {P}" #define ABC_COMMAND_DFL "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put" From 66701c5fcc399d83e736e83064a39466361763ba Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sun, 26 May 2019 02:52:48 -0700 Subject: [PATCH 092/213] Muck about with LUT delays some more --- techlibs/xilinx/abc.lut | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/techlibs/xilinx/abc.lut b/techlibs/xilinx/abc.lut index 438ed0368..5550a4039 100644 --- a/techlibs/xilinx/abc.lut +++ b/techlibs/xilinx/abc.lut @@ -1,11 +1,11 @@ # Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf # K area delay -1 1 248 -2 2 248 372 -3 3 248 372 496 -4 3 248 372 496 620 -5 3 248 372 496 620 744 +1 1 124 +2 2 124 248 +3 3 124 248 372 +4 3 124 248 372 496 +5 3 124 248 372 496 620 6 5 124 248 372 496 620 744 # F7BMUX 7 10 296 420 544 668 792 916 1040 From 086b6560b463878c543f9c9f981515b3b9409528 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sun, 26 May 2019 03:17:20 -0700 Subject: [PATCH 093/213] Typo --- passes/techmap/abc9.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 118bdf37b..513630a9a 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -25,7 +25,7 @@ #define ABC_COMMAND_LIB "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put" #define ABC_COMMAND_CTR "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put; buffer; upsize {D}; dnsize {D}; stime -p" //#define ABC_COMMAND_LUT "strash; ifraig; scorr; dc2; dretime; strash; dch -f; if; mfs2" -#define ABC_COMMAND_LUT "&st; "/*"&sweep -v; "*/"&scorr; "/*"dc2; "*/"&retime; &dch -f; &ps -l -m; &if; &ps -l -m" +#define ABC_COMMAND_LUT "&st; "/*"&sweep -v; "*/"&scorr; "/*"&dc2; */"&retime; &dch -f; &ps -l -m; &if; &ps -l -m" //#define ABC_COMMAND_LUT "&st; &scorr; &dc2; &retime; &dch -f; &if; &mfs; &ps -l -m" #define ABC_COMMAND_SOP "strash; ifraig; scorr; dc2; dretime; strash; dch -f; cover {I} {P}" #define ABC_COMMAND_DFL "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put" From 67f7c64a778e46882f884fd7058dc7bc07c5ca1e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sun, 26 May 2019 11:26:38 -0700 Subject: [PATCH 094/213] Fix padding, remove CIs from undriven_bits before erasing undriven POs --- backends/aiger/xaiger.cc | 22 ++++++++-------------- 1 file changed, 8 insertions(+), 14 deletions(-) diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 3d275214b..618a6500d 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -302,16 +302,13 @@ struct XAigerWriter continue; // Fully pad all unused input connections of this box cell with S0 - // Fully pad all undriven output connections of thix box cell with anonymous wires + // Fully pad all undriven output connections of this box cell with anonymous wires for (const auto w : box_module->wires()) { if (w->port_input) { auto it = cell->connections_.find(w->name); if (it != cell->connections_.end()) { - if (GetSize(it->second) < GetSize(w)) { - RTLIL::SigSpec padded_connection(RTLIL::S0, GetSize(w)-GetSize(it->second)); - padded_connection.append(it->second); - it->second = std::move(padded_connection); - } + if (GetSize(it->second) < GetSize(w)) + it->second.append(RTLIL::SigSpec(RTLIL::S0, GetSize(w)-GetSize(it->second))); } else cell->connections_[w->name] = RTLIL::SigSpec(RTLIL::S0, GetSize(w)); @@ -319,11 +316,8 @@ struct XAigerWriter if (w->port_output) { auto it = cell->connections_.find(w->name); if (it != cell->connections_.end()) { - if (GetSize(it->second) < GetSize(w)) { - RTLIL::SigSpec padded_connection = module->addWire(NEW_ID, GetSize(w)-GetSize(it->second)); - padded_connection.append(it->second); - it->second = std::move(padded_connection); - } + if (GetSize(it->second) < GetSize(w)) + it->second.append(module->addWire(NEW_ID, GetSize(w)-GetSize(it->second))); } else cell->connections_[w->name] = module->addWire(NEW_ID, GetSize(w)); @@ -384,13 +378,13 @@ struct XAigerWriter } // Do some CI/CO post-processing: + // CIs cannot be undriven + for (const auto &c : ci_bits) + undriven_bits.erase(c.first); // Erase all POs that are undriven if (!holes_mode) for (auto bit : undriven_bits) output_bits.erase(bit); - // CIs cannot be undriven - for (const auto &c : ci_bits) - undriven_bits.erase(c.first); for (auto bit : unused_bits) undriven_bits.erase(bit); From 3981eba999e1116f8f065451c6a71b8d3686b1bf Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sun, 26 May 2019 11:31:35 -0700 Subject: [PATCH 095/213] ABC9 to call &sweep --- passes/techmap/abc9.cc | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 513630a9a..8341741fa 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -25,8 +25,7 @@ #define ABC_COMMAND_LIB "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put" #define ABC_COMMAND_CTR "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put; buffer; upsize {D}; dnsize {D}; stime -p" //#define ABC_COMMAND_LUT "strash; ifraig; scorr; dc2; dretime; strash; dch -f; if; mfs2" -#define ABC_COMMAND_LUT "&st; "/*"&sweep -v; "*/"&scorr; "/*"&dc2; */"&retime; &dch -f; &ps -l -m; &if; &ps -l -m" -//#define ABC_COMMAND_LUT "&st; &scorr; &dc2; &retime; &dch -f; &if; &mfs; &ps -l -m" +#define ABC_COMMAND_LUT "&st; &sweep; &scorr; "/*"&dc2; */"&retime; &dch -f; &ps -l; &if; &ps -l" #define ABC_COMMAND_SOP "strash; ifraig; scorr; dc2; dretime; strash; dch -f; cover {I} {P}" #define ABC_COMMAND_DFL "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put" From 4311b9b583488817aaae0019f6ebc47deb030644 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sun, 26 May 2019 11:32:02 -0700 Subject: [PATCH 096/213] Blackboxes --- techlibs/xilinx/abc.box | 10 +++++----- techlibs/xilinx/cells_sim.v | 10 +++++----- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/techlibs/xilinx/abc.box b/techlibs/xilinx/abc.box index 9653fe5b8..4d907c7e2 100644 --- a/techlibs/xilinx/abc.box +++ b/techlibs/xilinx/abc.box @@ -3,18 +3,18 @@ # F7BMUX slower than F7AMUX # Inputs: I0 I1 S0 # Outputs: O -F7BMUX 1 1 3 1 +F7BMUX 1 0 3 1 217 223 296 # Inputs: I0 I1 S0 # Outputs: O -MUXF8 2 1 3 1 +MUXF8 2 0 3 1 104 94 273 # CARRY4 + CARRY4_[ABCD]X # Inputs: CI CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 # Outputs: CO0 CO1 CO2 CO3 O0 O1 O2 O3 -CARRY4 3 1 10 8 +CARRY4 3 0 10 8 271 536 379 - - - 340 - - - 157 494 465 445 - - 433 469 - - 228 592 540 520 356 - 512 548 292 - @@ -27,13 +27,13 @@ CARRY4 3 1 10 8 # SLICEM/A6LUT # Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE # Outputs: DPO SPO -RAM64X1D 4 1 15 2 +RAM64X1D 4 0 15 2 - - - - - - - 124 124 124 124 124 124 - - 124 124 124 124 124 124 - - - - - - 124 - - # SLICEM/A6LUT + F7[AB]MUX # Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE # Outputs: DPO SPO -RAM128X1D 5 1 17 2 +RAM128X1D 5 0 17 2 - - - - - - - - 314 314 314 314 314 314 292 - - 347 347 347 347 347 347 296 - - - - - - - - - - diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 29c79f689..db47b4230 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -159,12 +159,12 @@ module MUXCY(output O, input CI, DI, S); assign O = S ? CI : DI; endmodule -(* abc_box_id = 1, lib_whitebox *) +(* abc_box_id = 1 /*, lib_whitebox*/ *) module MUXF7(output O, input I0, I1, S); assign O = S ? I1 : I0; endmodule -(* abc_box_id = 2, lib_whitebox *) +(* abc_box_id = 2 /*, lib_whitebox*/ *) module MUXF8(output O, input I0, I1, S); assign O = S ? I1 : I0; endmodule @@ -173,7 +173,7 @@ module XORCY(output O, input CI, LI); assign O = CI ^ LI; endmodule -(* abc_box_id = 3, lib_whitebox *) +(* abc_box_id = 3 /*, lib_whitebox*/ *) module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S); assign O = S ^ {CO[2:0], CI | CYINIT}; assign CO[0] = S[0] ? CI | CYINIT : DI[0]; @@ -281,7 +281,7 @@ module FDPE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, PRE); always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; endmodule -(* abc_box_id = 4, lib_whitebox *) +(* abc_box_id = 4 /*, lib_whitebox*/ *) module RAM64X1D ( output DPO, SPO, input D, WCLK, WE, @@ -301,7 +301,7 @@ module RAM64X1D ( `endif endmodule -(* abc_box_id = 5, lib_whitebox *) +(* abc_box_id = 5 /*, lib_whitebox*/ *) module RAM128X1D ( output DPO, SPO, input D, WCLK, WE, From 3c8368454f5f9643425bab0065158587b03e2716 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sun, 26 May 2019 14:14:13 -0700 Subject: [PATCH 097/213] Fix "a" connectivity --- backends/aiger/xaiger.cc | 35 ++++++++++++++++++++++++++++++----- 1 file changed, 30 insertions(+), 5 deletions(-) diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 618a6500d..6cf0cb026 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -398,8 +398,25 @@ struct XAigerWriter } init_map.sort(); - input_bits.sort(); - output_bits.sort(); + if (holes_mode) { +#ifndef NDEBUG + RTLIL::SigBit last_bit; + for (auto bit : input_bits) { + log_assert(!last_bit.wire || last_bit.wire->port_id < bit.wire->port_id); + last_bit = bit; + } + last_bit = RTLIL::SigBit(); + for (auto bit : output_bits) { + log_assert(!last_bit.wire || last_bit.wire->port_id < bit.wire->port_id); + last_bit = bit; + } +#endif + } + else { + input_bits.sort(); + output_bits.sort(); + } + not_map.sort(); ff_map.sort(); and_map.sort(); @@ -415,7 +432,7 @@ struct XAigerWriter for (auto &c : ci_bits) { aig_m++, aig_i++; c.second = 2*aig_m; - aig_map[c.first] = c.second; + aig_map[c.first] = c.second; } if (imode && input_bits.empty()) { @@ -672,6 +689,7 @@ struct XAigerWriter holes_module = module->design->addModule("\\__holes__"); log_assert(holes_module); + int port_id = 1; for (auto cell : box_list) { RTLIL::Module* box_module = module->design->module(cell->type); int box_inputs = 0, box_outputs = 0; @@ -691,6 +709,8 @@ struct XAigerWriter if (!holes_wire) { holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs)); holes_wire->port_input = true; + holes_wire->port_id = port_id++; + holes_module->ports.push_back(holes_wire->name); } if (holes_cell) port_wire.append(holes_wire); @@ -706,6 +726,8 @@ struct XAigerWriter else holes_wire = holes_module->addWire(stringf("%s.%s[%d]", cell->name.c_str(), w->name.c_str(), i)); holes_wire->port_output = true; + holes_wire->port_id = port_id++; + holes_module->ports.push_back(holes_wire->name); if (holes_cell) port_wire.append(holes_wire); else @@ -734,7 +756,9 @@ struct XAigerWriter f.write(buffer_str.data(), buffer_str.size()); if (holes_module) { - holes_module->fixup_ports(); + // NB: fixup_ports() will sort ports by name + //holes_module->fixup_ports(); + holes_module->check(); holes_module->design->selection_stack.emplace_back(false); RTLIL::Selection& sel = holes_module->design->selection_stack.back(); @@ -750,7 +774,8 @@ struct XAigerWriter //Pass::call(holes_module->design, "techmap"); Pass::call(holes_module->design, "aigmap"); - Pass::call(holes_module->design, "clean -purge"); + //TODO: clean will mess up port_ids + //Pass::call(holes_module->design, "clean -purge"); holes_module->design->selection_stack.pop_back(); From 03b289a851c62eb2a7e3592432876bfa8a56770b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 27 May 2019 11:38:52 -0700 Subject: [PATCH 098/213] Add 'cinput' and 'coutput' to symbols file for boxes --- backends/aiger/xaiger.cc | 58 +++++++++++++++-------------------- frontends/aiger/aigerparse.cc | 35 +++++++++++++++++++++ passes/techmap/abc9.cc | 25 ++++++++++----- 3 files changed, 77 insertions(+), 41 deletions(-) diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 6cf0cb026..582e8e076 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -49,7 +49,8 @@ struct XAigerWriter dict not_map, ff_map, alias_map; dict> and_map; //pool initstate_bits; - vector> ci_bits, co_bits; + vector> ci_bits; + vector> co_bits; vector> aig_gates; vector aig_latchin, aig_latchinit, aig_outputs; @@ -327,6 +328,7 @@ struct XAigerWriter // Box ordering is alphabetical cell->connections_.sort(RTLIL::sort_by_id_str()); for (const auto &c : cell->connections()) { + int offset = 0; for (auto b : c.second.bits()) { auto is_input = cell->input(c.first); auto is_output = cell->output(c.first); @@ -335,11 +337,11 @@ struct XAigerWriter SigBit I = sigmap(b); if (I != b) alias_map[b] = I; - co_bits.emplace_back(b, 0); + co_bits.emplace_back(b, cell, c.first, offset++, 0); } if (is_output) { SigBit O = sigmap(b); - ci_bits.emplace_back(O, 0); + ci_bits.emplace_back(O, cell, c.first, offset++); } } } @@ -380,7 +382,7 @@ struct XAigerWriter // Do some CI/CO post-processing: // CIs cannot be undriven for (const auto &c : ci_bits) - undriven_bits.erase(c.first); + undriven_bits.erase(std::get<0>(c)); // Erase all POs that are undriven if (!holes_mode) for (auto bit : undriven_bits) @@ -399,18 +401,13 @@ struct XAigerWriter init_map.sort(); if (holes_mode) { -#ifndef NDEBUG - RTLIL::SigBit last_bit; - for (auto bit : input_bits) { - log_assert(!last_bit.wire || last_bit.wire->port_id < bit.wire->port_id); - last_bit = bit; - } - last_bit = RTLIL::SigBit(); - for (auto bit : output_bits) { - log_assert(!last_bit.wire || last_bit.wire->port_id < bit.wire->port_id); - last_bit = bit; - } -#endif + struct sort_by_port_id { + bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const { + return a.wire->port_id < b.wire->port_id; + } + }; + input_bits.sort(sort_by_port_id()); + output_bits.sort(sort_by_port_id()); } else { input_bits.sort(); @@ -431,8 +428,7 @@ struct XAigerWriter for (auto &c : ci_bits) { aig_m++, aig_i++; - c.second = 2*aig_m; - aig_map[c.first] = c.second; + aig_map[std::get<0>(c)] = 2*aig_m; } if (imode && input_bits.empty()) { @@ -496,9 +492,9 @@ struct XAigerWriter // aig_latchin.push_back(1); for (auto &c : co_bits) { - RTLIL::SigBit bit = c.first; - c.second = aig_o++; - ordered_outputs[bit] = c.second; + RTLIL::SigBit bit = std::get<0>(c); + std::get<4>(c) = aig_o++; + ordered_outputs[bit] = std::get<4>(c); aig_outputs.push_back(bit2aig(bit)); } @@ -774,8 +770,7 @@ struct XAigerWriter //Pass::call(holes_module->design, "techmap"); Pass::call(holes_module->design, "aigmap"); - //TODO: clean will mess up port_ids - //Pass::call(holes_module->design, "clean -purge"); + Pass::call(holes_module->design, "clean -purge"); holes_module->design->selection_stack.pop_back(); @@ -880,22 +875,17 @@ struct XAigerWriter } for (const auto &c : ci_bits) { - RTLIL::SigBit b = c.first; - RTLIL::Wire *wire = b.wire; - int i = b.offset; + RTLIL::SigBit b = std::get<0>(c); + int i = std::get<3>(c); int a = bit2aig(b); log_assert((a & 1) == 0); - input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire)); + input_lines[a] += stringf("cinput %d %d %s %s\n", (a >> 1)-1, i, log_id(std::get<1>(c)), log_id(std::get<2>(c))); } for (const auto &c : co_bits) { - RTLIL::SigBit b = c.first; - RTLIL::Wire *wire = b.wire; - int o = c.second; - if (wire) - output_lines[o] += stringf("output %d %d %s\n", o, b.offset, log_id(wire)); - else - output_lines[o] += stringf("output %d %d __const%d__\n", o, 0, b.data); + int i = std::get<3>(c); + int o = std::get<4>(c); + output_lines[o] += stringf("coutput %d %d %s %s\n", o, i, log_id(std::get<1>(c)), log_id(std::get<2>(c))); } input_lines.sort(); diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 94bfdfa3e..2441ee937 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -704,6 +704,41 @@ void AigerReader::post_process() } } } + else if (type == "cinput" || type == "coutput") { + RTLIL::Wire* wire; + if (type == "cinput") { + log_assert(static_cast(variable) < inputs.size()); + wire = inputs[variable]; + log_assert(wire); + log_assert(wire->port_input); + } + else if (type == "coutput") { + log_assert(static_cast(variable) < outputs.size()); + wire = outputs[variable]; + log_assert(wire); + log_assert(wire->port_output); + } + else log_abort(); + + std::string port; + mf >> port; + RTLIL::IdString cell_name = RTLIL::escape_id(symbol); + RTLIL::IdString cell_port = RTLIL::escape_id(port); + + RTLIL::Cell* cell = module->cell(cell_name); + if (!cell) + cell = module->addCell(cell_name, "$__blackbox__"); + wire->port_input = false; + wire->port_output = false; + if (cell->hasPort(cell_port)) { + log_assert(index == GetSize(cell->getPort(cell_port))); + cell->connections_[cell_port].append(wire); + } + else { + log_assert(index == 0); + cell->setPort(cell_port, wire); + } + } else log_error("Symbol type '%s' not recognised.\n", type.c_str()); } diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 8341741fa..89e3eb948 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -786,14 +786,24 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri continue; } - if (c->type == "$lut" && GetSize(c->getPort("\\A")) == 1 && c->getParam("\\LUT").as_int() == 2) { - SigSpec my_a = module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]; - SigSpec my_y = module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]; - module->connect(my_y, my_a); - continue; + RTLIL::Cell* cell; + if (c->type == "$lut") { + if (GetSize(c->getPort("\\A")) == 1 && c->getParam("\\LUT").as_int() == 2) { + SigSpec my_a = module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]; + SigSpec my_y = module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]; + module->connect(my_y, my_a); + continue; + } + else { + cell = module->addCell(remap_name(c->name), c->type); + } + } + else { + cell = module->cell(c->name); + log_assert(cell); + log_assert(c->type == "$__blackbox__"); } - RTLIL::Cell *cell = module->addCell(remap_name(c->name), c->type); if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx; cell->parameters = c->parameters; for (auto &conn : c->connections()) { @@ -802,7 +812,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri if (c.width == 0) continue; //log_assert(c.width == 1); - c.wire = module->wires_[remap_name(c.wire->name)]; + if (c.wire) + c.wire = module->wires_[remap_name(c.wire->name)]; newsig.append(c); } cell->setPort(conn.first, newsig); From 234156c01a4086a69ff9ac9f6ae668d64734d525 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 27 May 2019 12:16:10 -0700 Subject: [PATCH 099/213] Instantiate cell type (from sym file) otherwise 'clean' warnings --- backends/aiger/xaiger.cc | 6 ++++-- frontends/aiger/aigerparse.cc | 9 ++++++--- passes/techmap/abc9.cc | 12 +++++------- 3 files changed, 15 insertions(+), 12 deletions(-) diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 582e8e076..3c96f6c9e 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -879,13 +879,15 @@ struct XAigerWriter int i = std::get<3>(c); int a = bit2aig(b); log_assert((a & 1) == 0); - input_lines[a] += stringf("cinput %d %d %s %s\n", (a >> 1)-1, i, log_id(std::get<1>(c)), log_id(std::get<2>(c))); + RTLIL::Cell* cell = std::get<1>(c); + input_lines[a] += stringf("cinput %d %d %s %s %s\n", (a >> 1)-1, i, log_id(cell), log_id(std::get<2>(c)), log_id(cell->type)); } for (const auto &c : co_bits) { int i = std::get<3>(c); int o = std::get<4>(c); - output_lines[o] += stringf("coutput %d %d %s %s\n", o, i, log_id(std::get<1>(c)), log_id(std::get<2>(c))); + RTLIL::Cell* cell = std::get<1>(c); + output_lines[o] += stringf("coutput %d %d %s %s %s\n", o, i, log_id(cell), log_id(std::get<2>(c)), log_id(cell->type)); } input_lines.sort(); diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 2441ee937..6c174871b 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -720,14 +720,17 @@ void AigerReader::post_process() } else log_abort(); - std::string port; - mf >> port; + std::string port, type; + mf >> port >> type; RTLIL::IdString cell_name = RTLIL::escape_id(symbol); RTLIL::IdString cell_port = RTLIL::escape_id(port); + RTLIL::IdString cell_type = RTLIL::escape_id(type); RTLIL::Cell* cell = module->cell(cell_name); if (!cell) - cell = module->addCell(cell_name, "$__blackbox__"); + cell = module->addCell(cell_name, cell_type); + else + log_assert(cell->type == cell_type); wire->port_input = false; wire->port_output = false; if (cell->hasPort(cell_port)) { diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 89e3eb948..475508e02 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -535,18 +535,18 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri log_error("Can't open ABC output file `%s'.\n", buffer.c_str()); bool builtin_lib = liberty_file.empty(); - RTLIL::Design *mapped_design = new RTLIL::Design; //parse_blif(mapped_design, ifs, builtin_lib ? "\\DFF" : "\\_dff_", false, sop_mode); buffer = stringf("%s/%s", tempdir_name.c_str(), "input.sym"); - AigerReader reader(mapped_design, ifs, "\\netlist", "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */); + log_assert(!design->module("$__abc9__")); + AigerReader reader(design, ifs, "$__abc9__", "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */); reader.parse_xaiger(); ifs.close(); log_header(design, "Re-integrating ABC9 results.\n"); - RTLIL::Module *mapped_mod = mapped_design->modules_["\\netlist"]; + RTLIL::Module *mapped_mod = design->module("$__abc9__"); if (mapped_mod == NULL) - log_error("ABC output file does not contain a module `netlist'.\n"); + log_error("ABC output file does not contain a module `$__abc9__'.\n"); pool output_bits; for (auto &it : mapped_mod->wires_) { @@ -801,7 +801,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri else { cell = module->cell(c->name); log_assert(cell); - log_assert(c->type == "$__blackbox__"); + log_assert(c->type == cell->type); } if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx; @@ -937,8 +937,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri //log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires); log("ABC RESULTS: input signals: %8d\n", in_wires); log("ABC RESULTS: output signals: %8d\n", out_wires); - - delete mapped_design; } //else //{ From bf3b8d5e45771a543c2481dee5b1b3a9aba0881e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 27 May 2019 12:19:21 -0700 Subject: [PATCH 100/213] Remove mapped_mod when done --- passes/techmap/abc9.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 475508e02..acbab959e 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -937,6 +937,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri //log("ABC RESULTS: internal signals: %8d\n", int(signal_list.size()) - in_wires - out_wires); log("ABC RESULTS: input signals: %8d\n", in_wires); log("ABC RESULTS: output signals: %8d\n", out_wires); + + design->remove(mapped_mod); } //else //{ From 75bd41eaeb43ec7a25f0b27ff0cdf3be361446f1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 27 May 2019 12:22:05 -0700 Subject: [PATCH 101/213] Parse without wideports --- passes/techmap/abc9.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index acbab959e..a2948548d 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -538,7 +538,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri //parse_blif(mapped_design, ifs, builtin_lib ? "\\DFF" : "\\_dff_", false, sop_mode); buffer = stringf("%s/%s", tempdir_name.c_str(), "input.sym"); log_assert(!design->module("$__abc9__")); - AigerReader reader(design, ifs, "$__abc9__", "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */); + AigerReader reader(design, ifs, "$__abc9__", "" /* clk_name */, buffer.c_str() /* map_filename */, false /* wideports */); reader.parse_xaiger(); ifs.close(); From e115e736fa58ff1b3acc5e97897f09efbe112823 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 27 May 2019 12:34:17 -0700 Subject: [PATCH 102/213] parse_xaiger to not parse symbol table --- frontends/aiger/aigerparse.cc | 64 ----------------------------------- 1 file changed, 64 deletions(-) diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 6c174871b..a70db6c76 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -219,9 +219,6 @@ void AigerReader::parse_xaiger() unsigned l1; std::string s; bool comment_seen = false; - std::vector> deferred_renames; - std::vector> deferred_inouts; - deferred_renames.reserve(inputs.size() + latches.size() + outputs.size()); for (int c = f.peek(); c != EOF; c = f.peek()) { if (comment_seen || c == 'c') { if (!comment_seen) { @@ -281,71 +278,10 @@ void AigerReader::parse_xaiger() break; } } - else if (c == 'i' || c == 'l' || c == 'o') { - f.ignore(1); - if (!(f >> l1 >> s)) - log_error("Line %u cannot be interpreted as a symbol entry!\n", line_count); - - if ((c == 'i' && l1 > inputs.size()) || (c == 'l' && l1 > latches.size()) || (c == 'o' && l1 > outputs.size())) - log_error("Line %u has invalid symbol position!\n", line_count); - - RTLIL::Wire* wire; - if (c == 'i') wire = inputs[l1]; - else if (c == 'l') wire = latches[l1]; - else if (c == 'o') wire = outputs[l1]; - else log_abort(); - - RTLIL::IdString escaped_s = RTLIL::escape_id(s); - - if (escaped_s.ends_with("$inout.out")) { - deferred_inouts.emplace_back(wire, escaped_s.substr(0, escaped_s.size()-10)); - goto next_line; - } - else if (wideports && (wire->port_input || wire->port_output)) { - RTLIL::IdString wide_symbol; - int index; - std::tie(wide_symbol,index) = wideports_split(escaped_s.str()); - if (wide_symbol.ends_with("$inout.out")) { - deferred_inouts.emplace_back(wire, stringf("%s[%d]", wide_symbol.substr(0, wide_symbol.size()-10).c_str(), index)); - goto next_line; - } - } - deferred_renames.emplace_back(wire, escaped_s); - -next_line: - std::getline(f, line); // Ignore up to start of next line - ++line_count; - } else log_error("Line %u: cannot interpret first character '%c'!\n", line_count, c); } - dict wideports_cache; - for (const auto &i : deferred_renames) { - RTLIL::Wire *wire = i.first; - - module->rename(wire, i.second); - - if (wideports && (wire->port_input || wire->port_output)) { - RTLIL::IdString escaped_symbol; - int index; - std::tie(escaped_symbol,index) = wideports_split(wire->name.str()); - if (index > 0) - wideports_cache[escaped_symbol] = std::max(wideports_cache[escaped_symbol], index); - } - } - - for (const auto &i : deferred_inouts) { - RTLIL::Wire *out_wire = i.first; - log_assert(out_wire->port_output); - out_wire->port_output = false; - RTLIL::Wire *wire = module->wire(i.second); - log_assert(wire); - log_assert(wire->port_input && !wire->port_output); - wire->port_output = true; - module->connect(wire, out_wire); - } - post_process(); } From 428d7c8e11db3aa4d65b0509946a47b005f87988 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 27 May 2019 13:49:42 -0700 Subject: [PATCH 103/213] Remove unused function --- frontends/aiger/aigerparse.cc | 23 ----------------------- 1 file changed, 23 deletions(-) diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index a70db6c76..66b27fdd8 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -162,29 +162,6 @@ static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned litera return wire; } -static std::pair wideports_split(std::string name) -{ - int pos = -1; - - if (name.empty() || name.back() != ']') - goto failed; - - for (int i = 0; i+1 < GetSize(name); i++) { - if (name[i] == '[') - pos = i; - else if (name[i] < '0' || name[i] > '9') - pos = -1; - else if (i == pos+1 && name[i] == '0' && name[i+1] != ']') - pos = -1; - } - - if (pos >= 0) - return std::pair(RTLIL::escape_id(name.substr(0, pos)), atoi(name.c_str() + pos+1)); - -failed: - return std::pair(name, 0); -} - void AigerReader::parse_xaiger() { std::string header; From 4df37c77fdb709e67528cf6fe1a2cf52b004c156 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 27 May 2019 19:40:27 -0700 Subject: [PATCH 104/213] Disconnect all ABC boxes too --- passes/techmap/abc9.cc | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index a2948548d..10c795525 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -867,21 +867,19 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri // module->connect(conn); // } - // Go through all AND and NOT output connections, - // and for those output ports driving wires - // also driven by mapped_mod, disconnect them + // Go through all AND, NOT, and ABC box instances, + // and disconnect their output connections in + // preparation for stitching mapped_mod in for (auto cell : module->cells()) { - if (!cell->type.in("$_AND_", "$_NOT_")) - continue; + if (!cell->type.in("$_AND_", "$_NOT_")) { + RTLIL::Module* cell_module = design->module(cell->type); + if (!cell_module || !cell_module->attributes.count("\\abc_box_id")) + continue; + } for (auto &it : cell->connections_) { auto port_name = it.first; if (!cell->output(port_name)) continue; - auto &signal = it.second; - auto bits = signal.bits(); - for (auto &b : bits) - if (output_bits.count(b)) - b = module->addWire(NEW_ID); - signal = std::move(bits); + it.second = RTLIL::SigSpec(); } } // Do the same for module connections From 54e28eb3ea8bd79c55397d2f53771991039c7eed Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 27 May 2019 23:08:55 -0700 Subject: [PATCH 105/213] Re-enable lib_whitebox --- techlibs/xilinx/cells_sim.v | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index db47b4230..29c79f689 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -159,12 +159,12 @@ module MUXCY(output O, input CI, DI, S); assign O = S ? CI : DI; endmodule -(* abc_box_id = 1 /*, lib_whitebox*/ *) +(* abc_box_id = 1, lib_whitebox *) module MUXF7(output O, input I0, I1, S); assign O = S ? I1 : I0; endmodule -(* abc_box_id = 2 /*, lib_whitebox*/ *) +(* abc_box_id = 2, lib_whitebox *) module MUXF8(output O, input I0, I1, S); assign O = S ? I1 : I0; endmodule @@ -173,7 +173,7 @@ module XORCY(output O, input CI, LI); assign O = CI ^ LI; endmodule -(* abc_box_id = 3 /*, lib_whitebox*/ *) +(* abc_box_id = 3, lib_whitebox *) module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S); assign O = S ^ {CO[2:0], CI | CYINIT}; assign CO[0] = S[0] ? CI | CYINIT : DI[0]; @@ -281,7 +281,7 @@ module FDPE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, PRE); always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; endmodule -(* abc_box_id = 4 /*, lib_whitebox*/ *) +(* abc_box_id = 4, lib_whitebox *) module RAM64X1D ( output DPO, SPO, input D, WCLK, WE, @@ -301,7 +301,7 @@ module RAM64X1D ( `endif endmodule -(* abc_box_id = 5 /*, lib_whitebox*/ *) +(* abc_box_id = 5, lib_whitebox *) module RAM128X1D ( output DPO, SPO, input D, WCLK, WE, From e032e5bcde1c9e975c6947c27495b3049cd51737 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 27 May 2019 23:09:06 -0700 Subject: [PATCH 106/213] Make MUXF{7,8} and CARRY4 whitebox --- techlibs/xilinx/abc.box | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/techlibs/xilinx/abc.box b/techlibs/xilinx/abc.box index 4d907c7e2..b3972ddb3 100644 --- a/techlibs/xilinx/abc.box +++ b/techlibs/xilinx/abc.box @@ -3,18 +3,18 @@ # F7BMUX slower than F7AMUX # Inputs: I0 I1 S0 # Outputs: O -F7BMUX 1 0 3 1 +F7BMUX 1 1 3 1 217 223 296 # Inputs: I0 I1 S0 # Outputs: O -MUXF8 2 0 3 1 +MUXF8 2 1 3 1 104 94 273 # CARRY4 + CARRY4_[ABCD]X # Inputs: CI CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 # Outputs: CO0 CO1 CO2 CO3 O0 O1 O2 O3 -CARRY4 3 0 10 8 +CARRY4 3 1 10 8 271 536 379 - - - 340 - - - 157 494 465 445 - - 433 469 - - 228 592 540 520 356 - 512 548 292 - From 3f60061615a8b5df3ad05b997407f195c8197754 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 27 May 2019 23:10:59 -0700 Subject: [PATCH 107/213] Map file to include boxes not CI/CO --- backends/aiger/xaiger.cc | 83 ++++++++++++++++++---------------------- 1 file changed, 38 insertions(+), 45 deletions(-) diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 3c96f6c9e..2bc059dc5 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -304,48 +304,52 @@ struct XAigerWriter // Fully pad all unused input connections of this box cell with S0 // Fully pad all undriven output connections of this box cell with anonymous wires - for (const auto w : box_module->wires()) { + // NB: Assume box_module->ports are sorted alphabetically + // (as RTLIL::Module::fixup_ports() would do) + for (const auto &port_name : box_module->ports) { + RTLIL::Wire* w = box_module->wire(port_name); + log_assert(w); + auto it = cell->connections_.find(port_name); if (w->port_input) { - auto it = cell->connections_.find(w->name); + RTLIL::SigSpec rhs; if (it != cell->connections_.end()) { if (GetSize(it->second) < GetSize(w)) it->second.append(RTLIL::SigSpec(RTLIL::S0, GetSize(w)-GetSize(it->second))); + rhs = it->second; + } + else { + rhs = RTLIL::SigSpec(RTLIL::S0, GetSize(w)); + cell->setPort(port_name, rhs); + } + + int offset = 0; + for (const auto &b : rhs.bits()) { + SigBit I = sigmap(b); + if (I != b) + alias_map[b] = I; + co_bits.emplace_back(b, cell, port_name, offset++, 0); } - else - cell->connections_[w->name] = RTLIL::SigSpec(RTLIL::S0, GetSize(w)); } if (w->port_output) { + RTLIL::SigSpec rhs; auto it = cell->connections_.find(w->name); if (it != cell->connections_.end()) { if (GetSize(it->second) < GetSize(w)) it->second.append(module->addWire(NEW_ID, GetSize(w)-GetSize(it->second))); + rhs = it->second; + } + else { + rhs = module->addWire(NEW_ID, GetSize(w)); + cell->setPort(port_name, rhs); } - else - cell->connections_[w->name] = module->addWire(NEW_ID, GetSize(w)); - } - } - // Box ordering is alphabetical - cell->connections_.sort(RTLIL::sort_by_id_str()); - for (const auto &c : cell->connections()) { - int offset = 0; - for (auto b : c.second.bits()) { - auto is_input = cell->input(c.first); - auto is_output = cell->output(c.first); - log_assert(is_input || is_output); - if (is_input) { - SigBit I = sigmap(b); - if (I != b) - alias_map[b] = I; - co_bits.emplace_back(b, cell, c.first, offset++, 0); - } - if (is_output) { + int offset = 0; + for (const auto &b : rhs.bits()) { SigBit O = sigmap(b); - ci_bits.emplace_back(O, cell, c.first, offset++); + ci_bits.emplace_back(O, cell, port_name, offset++); } } } - box_list.emplace_back(cell); } @@ -686,6 +690,7 @@ struct XAigerWriter log_assert(holes_module); int port_id = 1; + int box_count = 0; for (auto cell : box_list) { RTLIL::Module* box_module = module->design->module(cell->type); int box_inputs = 0, box_outputs = 0; @@ -737,7 +742,7 @@ struct XAigerWriter write_h_buffer(box_inputs); write_h_buffer(box_outputs); write_h_buffer(box_module->attributes.at("\\abc_box_id").as_int()); - write_h_buffer(0 /* OldBoxNum */); + write_h_buffer(box_count++); } f << "h"; @@ -844,7 +849,7 @@ struct XAigerWriter if (output_bits.count(b)) { int o = ordered_outputs.at(b); - output_lines[o] += stringf("output %d %d %s\n", o, i, log_id(wire)); + output_lines[o] += stringf("output %lu %d %s\n", o - co_bits.size(), i, log_id(wire)); continue; } @@ -874,35 +879,23 @@ struct XAigerWriter } } - for (const auto &c : ci_bits) { - RTLIL::SigBit b = std::get<0>(c); - int i = std::get<3>(c); - int a = bit2aig(b); - log_assert((a & 1) == 0); - RTLIL::Cell* cell = std::get<1>(c); - input_lines[a] += stringf("cinput %d %d %s %s %s\n", (a >> 1)-1, i, log_id(cell), log_id(std::get<2>(c)), log_id(cell->type)); - } - - for (const auto &c : co_bits) { - int i = std::get<3>(c); - int o = std::get<4>(c); - RTLIL::Cell* cell = std::get<1>(c); - output_lines[o] += stringf("coutput %d %d %s %s %s\n", o, i, log_id(cell), log_id(std::get<2>(c)), log_id(cell->type)); - } - input_lines.sort(); for (auto &it : input_lines) f << it.second; - log_assert(input_lines.size() == input_bits.size() + ci_bits.size()); + log_assert(input_lines.size() == input_bits.size()); init_lines.sort(); for (auto &it : init_lines) f << it.second; + int box_count = 0; + for (auto cell : box_list) + f << stringf("box %d %d %s\n", box_count++, 0, log_id(cell->name)); + output_lines.sort(); for (auto &it : output_lines) f << it.second; - log_assert(output_lines.size() == output_bits.size() + co_bits.size()); + log_assert(output_lines.size() == output_bits.size()); if (omode && output_bits.empty()) f << "output " << output_lines.size() << " 0 __dummy_o__\n"; From 3eec100748c195eb60efcbd789b94d915d5cc260 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 27 May 2019 23:11:21 -0700 Subject: [PATCH 108/213] Parse "a" extension and boxes from map file --- frontends/aiger/aigerparse.cc | 101 ++++++++++++++++++++-------------- 1 file changed, 60 insertions(+), 41 deletions(-) diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 66b27fdd8..e8a355671 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -192,8 +192,15 @@ void AigerReader::parse_xaiger() else log_abort(); + dict box_lookup; + for (auto m : design->modules()) { + auto it = m->attributes.find("\\abc_box_id"); + if (it == m->attributes.end()) + continue; + box_lookup[it->second.as_int()] = m->name; + } + // Parse footer (symbol table, comments, etc.) - unsigned l1; std::string s; bool comment_seen = false; for (int c = f.peek(); c != EOF; c = f.peek()) { @@ -247,7 +254,21 @@ void AigerReader::parse_xaiger() f >> s; log_debug("n: '%s'\n", s.c_str()); } - else if (c == 'a' || c == 'i' || c == 'o' || c == 'h') { + else if (c == 'h') { + f.ignore(sizeof(uint32_t)); + uint32_t version = parse_xaiger_literal(f); + log_assert(version == 1); + f.ignore(4*sizeof(uint32_t)); + uint32_t boxNum = parse_xaiger_literal(f); + for (unsigned i = 0; i < boxNum; i++) { + f.ignore(2*sizeof(uint32_t)); + uint32_t boxUniqueId = parse_xaiger_literal(f); + log_assert(boxUniqueId > 0); + uint32_t oldBoxNum = parse_xaiger_literal(f); + module->addCell(stringf("$__box%u__", oldBoxNum), box_lookup.at(boxUniqueId)); + } + } + else if (c == 'a' || c == 'i' || c == 'o') { uint32_t dataSize = parse_xaiger_literal(f); f.ignore(dataSize); } @@ -471,7 +492,7 @@ void AigerReader::parse_aiger_binary() log_debug("%d is an output\n", l1); const unsigned variable = l1 >> 1; const bool invert = l1 & 1; - RTLIL::IdString wire_name(stringf("\\__%d%s__", variable, invert ? "b" : "")); // FIXME: is "_inv" the right suffix? + RTLIL::IdString wire_name(stringf("\\__%d%s__", variable, invert ? "b" : "")); // FIXME: is "_b" the right suffix? wire = module->wire(wire_name); if (!wire) wire = createWireIfNotExists(module, l1); @@ -527,6 +548,7 @@ void AigerReader::post_process() std::ifstream mf(map_filename); std::string type, symbol; int variable, index; + int pi_count = 0, ci_count = 0, co_count = 0; while (mf >> type >> variable >> index >> symbol) { RTLIL::IdString escaped_s = RTLIL::escape_id(symbol); if (type == "input") { @@ -534,6 +556,7 @@ void AigerReader::post_process() RTLIL::Wire* wire = inputs[variable]; log_assert(wire); log_assert(wire->port_input); + pi_count++; if (index == 0) { // Cope with the fact that a CI might be identical @@ -562,8 +585,8 @@ void AigerReader::post_process() } } else if (type == "output") { - log_assert(static_cast(variable) < outputs.size()); - RTLIL::Wire* wire = outputs[variable]; + log_assert(static_cast(variable + co_count) < outputs.size()); + RTLIL::Wire* wire = outputs[variable + co_count]; log_assert(wire); log_assert(wire->port_output); if (escaped_s.in("\\__dummy_o__", "\\__const0__", "\\__const1__")) { @@ -617,42 +640,38 @@ void AigerReader::post_process() } } } - else if (type == "cinput" || type == "coutput") { - RTLIL::Wire* wire; - if (type == "cinput") { - log_assert(static_cast(variable) < inputs.size()); - wire = inputs[variable]; - log_assert(wire); - log_assert(wire->port_input); - } - else if (type == "coutput") { - log_assert(static_cast(variable) < outputs.size()); - wire = outputs[variable]; - log_assert(wire); - log_assert(wire->port_output); - } - else log_abort(); - - std::string port, type; - mf >> port >> type; - RTLIL::IdString cell_name = RTLIL::escape_id(symbol); - RTLIL::IdString cell_port = RTLIL::escape_id(port); - RTLIL::IdString cell_type = RTLIL::escape_id(type); - - RTLIL::Cell* cell = module->cell(cell_name); - if (!cell) - cell = module->addCell(cell_name, cell_type); - else - log_assert(cell->type == cell_type); - wire->port_input = false; - wire->port_output = false; - if (cell->hasPort(cell_port)) { - log_assert(index == GetSize(cell->getPort(cell_port))); - cell->connections_[cell_port].append(wire); - } - else { - log_assert(index == 0); - cell->setPort(cell_port, wire); + else if (type == "box") { + RTLIL::Cell* cell = module->cell(stringf("$__box%d__", variable)); + if (cell) { + module->rename(cell, escaped_s); + RTLIL::Module* box_module = design->module(cell->type); + log_assert(box_module); + // NB: Assume box_module->ports are sorted alphabetically + // (as RTLIL::Module::fixup_ports() would do) + for (auto port_name : box_module->ports) { + RTLIL::Wire* w = box_module->wire(port_name); + log_assert(w); + RTLIL::SigSpec rhs; + for (int i = 0; i < GetSize(w); i++) { + if (w->port_input) { + log_assert(static_cast(co_count) < outputs.size()); + RTLIL::Wire* wire = outputs[co_count++]; + log_assert(wire); + log_assert(wire->port_output); + wire->port_output = false; + rhs.append(wire); + } + if (w->port_output) { + log_assert(static_cast(pi_count + ci_count) < inputs.size()); + RTLIL::Wire* wire = inputs[pi_count + ci_count++]; + log_assert(wire); + log_assert(wire->port_input); + wire->port_input = false; + rhs.append(wire); + } + } + cell->setPort(port_name, rhs); + } } } else From 89bd6b85045b371c1088004d8e4af0dd78a3981d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 27 May 2019 23:12:21 -0700 Subject: [PATCH 109/213] If driver not found, use LUT2 --- passes/techmap/abc9.cc | 56 ++++++++++++++++++++---------------------- 1 file changed, 27 insertions(+), 29 deletions(-) diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 10c795525..1b45085be 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -588,30 +588,34 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri RTLIL::SigBit a_bit = c->getPort("\\A").as_bit(); RTLIL::SigBit y_bit = c->getPort("\\Y").as_bit(); if (!lut_costs.empty() || !lut_file.empty()) { + RTLIL::Cell* driving_lut = nullptr; // ABC can return NOT gates that drive POs - if (a_bit.wire->port_input) { - // If it's a NOT gate that comes from a primary input directly - // then implement it using a LUT - cell = module->addLut(remap_name(stringf("%s$lut", c->name.c_str())), - RTLIL::SigBit(module->wires_[remap_name(a_bit.wire->name)], a_bit.offset), - RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset), - 1); - } - else { - // Otherwise, clone the driving LUT to guarantee that we - // won't increase the max logic depth + if (!a_bit.wire->port_input) { + // If it's not a NOT gate that that comes from a PI directly, + // find the driving LUT and clone that to guarantee that we won't + // increase the max logic depth // (TODO: Optimise by not cloning unless will increase depth) RTLIL::IdString driver_name; if (GetSize(a_bit.wire) == 1) driver_name = stringf("%s$lut", a_bit.wire->name.c_str()); else driver_name = stringf("%s[%d]$lut", a_bit.wire->name.c_str(), a_bit.offset); - RTLIL::Cell* driver = mapped_mod->cell(driver_name); - log_assert(driver); - auto driver_a = driver->getPort("\\A").chunks(); + driving_lut = mapped_mod->cell(driver_name); + } + + if (!driving_lut) { + // If a driver couldn't be found (could be from PI, + // or from a box) then implement using a LUT + cell = module->addLut(remap_name(stringf("%s$lut", c->name.c_str())), + RTLIL::SigBit(module->wires_[remap_name(a_bit.wire->name)], a_bit.offset), + RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset), + 1); + } + else { + auto driver_a = driving_lut->getPort("\\A").chunks(); for (auto &chunk : driver_a) chunk.wire = module->wires_[remap_name(chunk.wire->name)]; - RTLIL::Const driver_lut = driver->getParam("\\LUT"); + RTLIL::Const driver_lut = driving_lut->getParam("\\LUT"); for (auto &b : driver_lut.bits) { if (b == RTLIL::State::S0) b = RTLIL::State::S1; else if (b == RTLIL::State::S1) b = RTLIL::State::S0; @@ -867,20 +871,14 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri // module->connect(conn); // } - // Go through all AND, NOT, and ABC box instances, - // and disconnect their output connections in - // preparation for stitching mapped_mod in - for (auto cell : module->cells()) { - if (!cell->type.in("$_AND_", "$_NOT_")) { - RTLIL::Module* cell_module = design->module(cell->type); - if (!cell_module || !cell_module->attributes.count("\\abc_box_id")) - continue; - } - for (auto &it : cell->connections_) { - auto port_name = it.first; - if (!cell->output(port_name)) continue; - it.second = RTLIL::SigSpec(); - } + // Remove all AND, NOT, instances + // in preparation for stitching mapped_mod in + for (auto it = module->cells_.begin(); it != module->cells_.end(); ) { + RTLIL::Cell* cell = it->second; + if (cell->type.in("$_AND_", "$_NOT_")) + it = module->cells_.erase(it); + else + ++it; } // Do the same for module connections for (auto &it : module->connections_) { From 4a76b425cc0588ef5a8e46c06eecbfab869a35d9 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 28 May 2019 08:44:59 -0700 Subject: [PATCH 110/213] Misspell --- passes/techmap/abc9.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 1b45085be..328f0e3c3 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -567,7 +567,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri // Attempt another wideports_split here because there // exists the possibility that different bits of a port - // could be an input and output, therefore parse_xiager() + // could be an input and output, therefore parse_xaiger() // could not combine it into a wideport auto r = wideports_split(w->name.str()); wire = module->wire(r.first); From f745727de5af085412b2e5f8161aa1018cc5e276 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 28 May 2019 08:45:10 -0700 Subject: [PATCH 111/213] read_aiger to only clean own design --- frontends/aiger/aigerparse.cc | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index e8a355671..8d7588f88 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -722,8 +722,14 @@ void AigerReader::post_process() module->fixup_ports(); design->add(module); + design->selection_stack.emplace_back(false); + RTLIL::Selection& sel = design->selection_stack.back(); + sel.select(module); + Pass::call(design, "clean"); + design->selection_stack.pop_back(); + for (auto cell : module->cells().to_vector()) { if (cell->type != "$lut") continue; auto y_port = cell->getPort("\\Y").as_bit(); From 6931a3a47da5119ac44449ef117f3985e2fda417 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 28 May 2019 09:32:18 -0700 Subject: [PATCH 112/213] Update README.md from master --- README.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/README.md b/README.md index e6be0f37e..19306cda3 100644 --- a/README.md +++ b/README.md @@ -366,7 +366,7 @@ Verilog Attributes and non-standard features - When defining a macro with `define, all text between triple double quotes is interpreted as macro body, even if it contains unescaped newlines. The - tipple double quotes are removed from the macro body. For example: + triple double quotes are removed from the macro body. For example: `define MY_MACRO(a, b) """ assign a = 23; @@ -459,7 +459,7 @@ Non-standard or SystemVerilog features for formal verification supported in any clocked block. - The syntax ``@($global_clock)`` can be used to create FFs that have no - explicit clock input ($ff cells). The same can be achieved by using + explicit clock input (``$ff`` cells). The same can be achieved by using ``@(posedge )`` or ``@(negedge )`` when ```` is marked with the ``(* gclk *)`` Verilog attribute. @@ -472,7 +472,7 @@ from SystemVerilog: - The ``assert`` statement from SystemVerilog is supported in its most basic form. In module context: ``assert property ();`` and within an - always block: ``assert();``. It is transformed to a $assert cell. + always block: ``assert();``. It is transformed to an ``$assert`` cell. - The ``assume``, ``restrict``, and ``cover`` statements from SystemVerilog are also supported. The same limitations as with the ``assert`` statement apply. From 914074a07c14709523cc72084e1673bd3c2eaf30 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 28 May 2019 09:35:45 -0700 Subject: [PATCH 113/213] Update from master --- backends/json/json.cc | 115 ++++++++++++++++++++---------------------- kernel/cellaigs.cc | 2 +- kernel/celltypes.h | 2 +- passes/opt/wreduce.cc | 2 - passes/sat/expose.cc | 2 +- 5 files changed, 59 insertions(+), 64 deletions(-) diff --git a/backends/json/json.cc b/backends/json/json.cc index b4f82a3fe..f5c687981 100644 --- a/backends/json/json.cc +++ b/backends/json/json.cc @@ -130,75 +130,72 @@ struct JsonWriter f << stringf(" }"); first = false; } - f << stringf("\n }"); + f << stringf("\n },\n"); - if (!module->get_blackbox_attribute()) { - f << stringf(",\n \"cells\": {"); - first = true; - for (auto c : module->cells()) { - if (use_selection && !module->selected(c)) - continue; - f << stringf("%s\n", first ? "" : ","); - f << stringf(" %s: {\n", get_name(c->name).c_str()); - f << stringf(" \"hide_name\": %s,\n", c->name[0] == '$' ? "1" : "0"); - f << stringf(" \"type\": %s,\n", get_name(c->type).c_str()); - if (aig_mode) { - Aig aig(c); - if (!aig.name.empty()) { - f << stringf(" \"model\": \"%s\",\n", aig.name.c_str()); - aig_models.insert(aig); - } + f << stringf(" \"cells\": {"); + first = true; + for (auto c : module->cells()) { + if (use_selection && !module->selected(c)) + continue; + f << stringf("%s\n", first ? "" : ","); + f << stringf(" %s: {\n", get_name(c->name).c_str()); + f << stringf(" \"hide_name\": %s,\n", c->name[0] == '$' ? "1" : "0"); + f << stringf(" \"type\": %s,\n", get_name(c->type).c_str()); + if (aig_mode) { + Aig aig(c); + if (!aig.name.empty()) { + f << stringf(" \"model\": \"%s\",\n", aig.name.c_str()); + aig_models.insert(aig); } - f << stringf(" \"parameters\": {"); - write_parameters(c->parameters); - f << stringf("\n },\n"); - f << stringf(" \"attributes\": {"); - write_parameters(c->attributes); - f << stringf("\n },\n"); - if (c->known()) { - f << stringf(" \"port_directions\": {"); - bool first2 = true; - for (auto &conn : c->connections()) { - string direction = "output"; - if (c->input(conn.first)) - direction = c->output(conn.first) ? "inout" : "input"; - f << stringf("%s\n", first2 ? "" : ","); - f << stringf(" %s: \"%s\"", get_name(conn.first).c_str(), direction.c_str()); - first2 = false; - } - f << stringf("\n },\n"); - } - f << stringf(" \"connections\": {"); + } + f << stringf(" \"parameters\": {"); + write_parameters(c->parameters); + f << stringf("\n },\n"); + f << stringf(" \"attributes\": {"); + write_parameters(c->attributes); + f << stringf("\n },\n"); + if (c->known()) { + f << stringf(" \"port_directions\": {"); bool first2 = true; for (auto &conn : c->connections()) { + string direction = "output"; + if (c->input(conn.first)) + direction = c->output(conn.first) ? "inout" : "input"; f << stringf("%s\n", first2 ? "" : ","); - f << stringf(" %s: %s", get_name(conn.first).c_str(), get_bits(conn.second).c_str()); + f << stringf(" %s: \"%s\"", get_name(conn.first).c_str(), direction.c_str()); first2 = false; } - f << stringf("\n }\n"); - f << stringf(" }"); - first = false; + f << stringf("\n },\n"); } - f << stringf("\n },\n"); - - f << stringf(" \"netnames\": {"); - first = true; - for (auto w : module->wires()) { - if (use_selection && !module->selected(w)) - continue; - f << stringf("%s\n", first ? "" : ","); - f << stringf(" %s: {\n", get_name(w->name).c_str()); - f << stringf(" \"hide_name\": %s,\n", w->name[0] == '$' ? "1" : "0"); - f << stringf(" \"bits\": %s,\n", get_bits(w).c_str()); - f << stringf(" \"attributes\": {"); - write_parameters(w->attributes); - f << stringf("\n }\n"); - f << stringf(" }"); - first = false; + f << stringf(" \"connections\": {"); + bool first2 = true; + for (auto &conn : c->connections()) { + f << stringf("%s\n", first2 ? "" : ","); + f << stringf(" %s: %s", get_name(conn.first).c_str(), get_bits(conn.second).c_str()); + first2 = false; } - f << stringf("\n }"); + f << stringf("\n }\n"); + f << stringf(" }"); + first = false; } - f << stringf("\n"); + f << stringf("\n },\n"); + + f << stringf(" \"netnames\": {"); + first = true; + for (auto w : module->wires()) { + if (use_selection && !module->selected(w)) + continue; + f << stringf("%s\n", first ? "" : ","); + f << stringf(" %s: {\n", get_name(w->name).c_str()); + f << stringf(" \"hide_name\": %s,\n", w->name[0] == '$' ? "1" : "0"); + f << stringf(" \"bits\": %s,\n", get_bits(w).c_str()); + f << stringf(" \"attributes\": {"); + write_parameters(w->attributes); + f << stringf("\n }\n"); + f << stringf(" }"); + first = false; + } + f << stringf("\n }\n"); f << stringf(" }"); } diff --git a/kernel/cellaigs.cc b/kernel/cellaigs.cc index 5fd76afe5..26c625f89 100644 --- a/kernel/cellaigs.cc +++ b/kernel/cellaigs.cc @@ -453,7 +453,7 @@ Aig::Aig(Cell *cell) int B = mk.inport("\\B"); int C = mk.inport("\\C"); int D = mk.inport("\\D"); - int Y = mk.nand_gate(mk.nor_gate(A, B), mk.nor_gate(C, D)); + int Y = mk.nand_gate(mk.or_gate(A, B), mk.or_gate(C, D)); mk.outport(Y, "\\Y"); goto optimize; } diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 89df36222..4e91eddda 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -469,7 +469,7 @@ struct CellTypes if (cell->type == "$_AOI4_") return eval_not(const_or(const_and(arg1, arg2, false, false, 1), const_and(arg3, arg4, false, false, 1), false, false, 1)); if (cell->type == "$_OAI4_") - return eval_not(const_and(const_or(arg1, arg2, false, false, 1), const_and(arg3, arg4, false, false, 1), false, false, 1)); + return eval_not(const_and(const_or(arg1, arg2, false, false, 1), const_or(arg3, arg4, false, false, 1), false, false, 1)); log_assert(arg4.bits.size() == 0); return eval(cell, arg1, arg2, arg3, errp); diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index cfe4b4067..1fbc41082 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -465,12 +465,10 @@ struct WreduceWorker SigSpec initsig = init_attr_sigmap(w); int width = std::min(GetSize(initval), GetSize(initsig)); for (int i = 0; i < width; i++) { - log_dump(initsig[i], remove_init_bits.count(initsig[i])); if (!remove_init_bits.count(initsig[i])) new_initval[i] = initval[i]; } w->attributes.at("\\init") = new_initval; - log_dump(w->name, initval, new_initval); } } } diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index 50ab38063..71ce1683d 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -42,7 +42,7 @@ struct dff_map_bit_info_t { bool consider_wire(RTLIL::Wire *wire, std::map &dff_dq_map) { - if (/*wire->name[0] == '$' ||*/ dff_dq_map.count(wire->name)) + if (wire->name[0] == '$' || dff_dq_map.count(wire->name)) return false; if (wire->port_input) return false; From f228621b80d727b4dc1d7a9b3b934c1fbc170642 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 28 May 2019 09:36:01 -0700 Subject: [PATCH 114/213] Typo --- techlibs/xilinx/cells_xtra.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/xilinx/cells_xtra.sh b/techlibs/xilinx/cells_xtra.sh index e3b847c36..2b384f405 100644 --- a/techlibs/xilinx/cells_xtra.sh +++ b/techlibs/xilinx/cells_xtra.sh @@ -125,7 +125,7 @@ function xtract_cell_decl() xtract_cell_decl RAM32X1S_1 xtract_cell_decl RAM32X2S xtract_cell_decl RAM64M - x#tract_cell_decl RAM64X1D + #xtract_cell_decl RAM64X1D xtract_cell_decl RAM64X1S xtract_cell_decl RAM64X1S_1 xtract_cell_decl RAM64X2S From cdedf51c326122a3154a587e3784bbf5a5b4e727 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 28 May 2019 09:37:50 -0700 Subject: [PATCH 115/213] From master --- passes/pmgen/README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/pmgen/README.md b/passes/pmgen/README.md index d0711c730..2f0b1fd5a 100644 --- a/passes/pmgen/README.md +++ b/passes/pmgen/README.md @@ -232,5 +232,5 @@ But in some cases it is more natural to utilize the implicit branch statement: portAB = \B; endcode -There is an implicit `code..endcode` block at the end of each `.pgm` file +There is an implicit `code..endcode` block at the end of each `.pmg` file that just accepts everything that gets all the way there. From 5f39c262c278f90f6bbb55d5969b970230876ef5 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 28 May 2019 09:38:58 -0700 Subject: [PATCH 116/213] From master --- tests/tools/autotest.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index 1825990a9..920474a84 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -132,13 +132,13 @@ do fn=$(basename $fn) bn=$(basename $bn) + rm -f ${bn}_ref.fir if [[ "$ext" == "v" ]]; then egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext} else "$toolsdir"/../../yosys -f "$frontend $include_opts" -b "verilog" -o ${bn}_ref.v ../${fn} frontend="verilog -noblackbox" fi - rm -f ${bn}_ref.fir if [ ! -f ../${bn}_tb.v ]; then "$toolsdir"/../../yosys -f "$frontend $include_opts" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.v From 13e233217cd0caceeb5d30d2eefa5238ffc5bfc9 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 28 May 2019 11:29:59 -0700 Subject: [PATCH 117/213] Small improvement --- backends/aiger/xaiger.cc | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 2bc059dc5..5919b2302 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -328,6 +328,7 @@ struct XAigerWriter if (I != b) alias_map[b] = I; co_bits.emplace_back(b, cell, port_name, offset++, 0); + unused_bits.erase(b); } } if (w->port_output) { @@ -347,6 +348,7 @@ struct XAigerWriter for (const auto &b : rhs.bits()) { SigBit O = sigmap(b); ci_bits.emplace_back(O, cell, port_name, offset++); + undriven_bits.erase(O); } } } @@ -383,10 +385,6 @@ struct XAigerWriter } } - // Do some CI/CO post-processing: - // CIs cannot be undriven - for (const auto &c : ci_bits) - undriven_bits.erase(std::get<0>(c)); // Erase all POs that are undriven if (!holes_mode) for (auto bit : undriven_bits) From b4321a31bbd9f215e753563d5d031b2c24f1b371 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 28 May 2019 12:42:17 -0700 Subject: [PATCH 118/213] Fix for abc9_test022 --- backends/aiger/xaiger.cc | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 5919b2302..2ffd460dd 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -277,8 +277,10 @@ struct XAigerWriter } } if (is_output) { + input_bits.insert(b); SigBit O = sigmap(b); - input_bits.insert(O); + if (O != b) + alias_map[O] = b; undriven_bits.erase(O); } } @@ -346,8 +348,10 @@ struct XAigerWriter int offset = 0; for (const auto &b : rhs.bits()) { + ci_bits.emplace_back(b, cell, port_name, offset++); SigBit O = sigmap(b); - ci_bits.emplace_back(O, cell, port_name, offset++); + if (O != b) + alias_map[O] = b; undriven_bits.erase(O); } } From 92197326b8fa406e94c952cfcb778611642a3e00 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 28 May 2019 12:43:07 -0700 Subject: [PATCH 119/213] Add abc9_test022 --- tests/simple_abc9/abc9.v | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index fb5b759fb..e666d1a6a 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -143,6 +143,7 @@ assign b = ~a; always @* d <= &c; endmodule +// Citation: https://github.com/alexforencich/verilog-ethernet module abc9_test021(clk, rst, s_eth_hdr_valid, s_eth_hdr_ready, s_eth_dest_mac, s_eth_src_mac, s_eth_type, s_eth_payload_axis_tdata, s_eth_payload_axis_tkeep, s_eth_payload_axis_tvalid, s_eth_payload_axis_tready, s_eth_payload_axis_tlast, s_eth_payload_axis_tid, s_eth_payload_axis_tdest, s_eth_payload_axis_tuser, m_eth_hdr_valid, m_eth_hdr_ready, m_eth_dest_mac, m_eth_src_mac, m_eth_type, m_eth_payload_axis_tdata, m_eth_payload_axis_tkeep, m_eth_payload_axis_tvalid, m_eth_payload_axis_tready, m_eth_payload_axis_tlast, m_eth_payload_axis_tid, m_eth_payload_axis_tdest, m_eth_payload_axis_tuser); input clk; output [47:0] m_eth_dest_mac; @@ -215,3 +216,24 @@ endmodule (* abc_box_id=1 *) module MUXF8(input I0, I1, S, output O); endmodule + +// Citation: https://github.com/alexforencich/verilog-ethernet +// TODO: yosys -p "synth_xilinx -abc9 -top abc9_test022" abc9.v -q +// returns before b4321a31 +// Warning: Wire abc9_test022.\m_eth_payload_axis_tkeep [7] is used but has no +// driver. +// Warning: Wire abc9_test022.\m_eth_payload_axis_tkeep [3] is used but has no +// driver. +module abc9_test022 +( + input wire clk, + input wire i, + output wire [7:0] m_eth_payload_axis_tkeep +); + +reg [7:0] m_eth_payload_axis_tkeep_reg = 8'd0; +assign m_eth_payload_axis_tkeep = m_eth_payload_axis_tkeep_reg; +always @(posedge clk) + m_eth_payload_axis_tkeep_reg <= i ? 8'hff : 8'h0f; + +endmodule From ecaa7856e96dad8de5ef162bb1c9c5814de5254f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 29 May 2019 15:21:41 -0700 Subject: [PATCH 120/213] Add some debug to abc9 --- passes/techmap/abc9.cc | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 328f0e3c3..41ab9abea 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -423,6 +423,21 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri Pass::call(design, stringf("write_xaiger -O -map %s/input.sym %s/input.xaig; ", tempdir_name.c_str(), tempdir_name.c_str())); +#if 0 + std::string buffer = stringf("%s/%s", tempdir_name.c_str(), "input.xaig"); + std::ifstream ifs; + ifs.open(buffer); + if (ifs.fail()) + log_error("Can't open ABC output file `%s'.\n", buffer.c_str()); + buffer = stringf("%s/%s", tempdir_name.c_str(), "input.sym"); + log_assert(!design->module("$__abc9__")); + AigerReader reader(design, ifs, "$__abc9__", "" /* clk_name */, buffer.c_str() /* map_filename */, false /* wideports */); + reader.parse_xaiger(); + ifs.close(); + Pass::call(design, stringf("write_verilog -noexpr -norename %s/%s", tempdir_name.c_str(), "input.v")); + design->remove(design->module("$__abc9__")); +#endif + design->selection_stack.pop_back(); // Now 'unexpose' those wires by undoing @@ -540,9 +555,12 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri log_assert(!design->module("$__abc9__")); AigerReader reader(design, ifs, "$__abc9__", "" /* clk_name */, buffer.c_str() /* map_filename */, false /* wideports */); reader.parse_xaiger(); - ifs.close(); +#if 0 + Pass::call(design, stringf("write_verilog -noexpr -norename %s/%s", tempdir_name.c_str(), "output.v")); +#endif + log_header(design, "Re-integrating ABC9 results.\n"); RTLIL::Module *mapped_mod = design->module("$__abc9__"); if (mapped_mod == NULL) From 1423384367d4fa31f09c6c7b69c1b89edc3dd066 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 29 May 2019 15:24:09 -0700 Subject: [PATCH 121/213] Fix abc_test024 --- backends/aiger/xaiger.cc | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 2ffd460dd..bf696bfd6 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -152,10 +152,11 @@ struct XAigerWriter undriven_bits.insert(bit); unused_bits.insert(bit); - if (wire->port_input) - input_bits.insert(bit); - else if (keep) + if (wire->port_input || keep) { + if (bit != wirebit) + alias_map[bit] = wirebit; input_bits.insert(wirebit); + } if (wire->port_output || keep) { if (bit != wirebit) @@ -166,7 +167,7 @@ struct XAigerWriter } for (auto bit : input_bits) - undriven_bits.erase(bit); + undriven_bits.erase(sigmap(bit)); for (auto bit : output_bits) if (!bit.wire->port_input) From aa2380c17a7c97d4c3835cd6d78310cf4961c4f8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 29 May 2019 15:24:38 -0700 Subject: [PATCH 122/213] Add abc_test024 --- tests/simple_abc9/abc9.v | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index e666d1a6a..7af2ace01 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -230,10 +230,23 @@ module abc9_test022 input wire i, output wire [7:0] m_eth_payload_axis_tkeep ); - -reg [7:0] m_eth_payload_axis_tkeep_reg = 8'd0; -assign m_eth_payload_axis_tkeep = m_eth_payload_axis_tkeep_reg; -always @(posedge clk) - m_eth_payload_axis_tkeep_reg <= i ? 8'hff : 8'h0f; - + reg [7:0] m_eth_payload_axis_tkeep_reg = 8'd0; + assign m_eth_payload_axis_tkeep = m_eth_payload_axis_tkeep_reg; + always @(posedge clk) + m_eth_payload_axis_tkeep_reg <= i ? 8'hff : 8'h0f; +endmodule + +// Citation: https://github.com/riscv/riscv-bitmanip +// TODO: yosys -p "synth_xilinx -abc9 -top abc9_test024" abc9.v -q +// returns before 14233843 +// Warning: Wire abc9_test024.\dout [1] is used but has no driver. +module abc9_test024 #( + parameter integer N = 2, + parameter integer M = 2 +) ( + input [7:0] din, + output [M-1:0] dout +); + wire [2*M-1:0] mask = {M{1'b1}}; + assign dout = (mask << din[N-1:0]) >> M; endmodule From 25befbf5425458cf8cc5ee89635ad7e5f42d5778 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 29 May 2019 15:26:33 -0700 Subject: [PATCH 123/213] Rename to #23 --- tests/simple_abc9/abc9.v | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index 7af2ace01..2752ff8cc 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -237,10 +237,10 @@ module abc9_test022 endmodule // Citation: https://github.com/riscv/riscv-bitmanip -// TODO: yosys -p "synth_xilinx -abc9 -top abc9_test024" abc9.v -q +// TODO: yosys -p "synth_xilinx -abc9 -top abc9_test023" abc9.v -q // returns before 14233843 -// Warning: Wire abc9_test024.\dout [1] is used but has no driver. -module abc9_test024 #( +// Warning: Wire abc9_test023.\dout [1] is used but has no driver. +module abc9_test023 #( parameter integer N = 2, parameter integer M = 2 ) ( From 5e75abf8706971e115166cdc82435201d7a59b1e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 29 May 2019 16:34:43 -0700 Subject: [PATCH 124/213] Bump ABC --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 05b28f33d..377a5f6b5 100644 --- a/Makefile +++ b/Makefile @@ -118,7 +118,7 @@ OBJS = kernel/version_$(GIT_REV).o # is just a symlink to your actual ABC working directory, as 'make mrproper' # will remove the 'abc' directory and you do not want to accidentally # delete your work on ABC.. -ABCREV = 3709744 +ABCREV = 62487de ABCPULL = 1 ABCURL ?= https://github.com/berkeley-abc/abc ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 From b955344ecd01bdeb5d3e4fbb26f274e4bf9bc125 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 29 May 2019 16:34:52 -0700 Subject: [PATCH 125/213] Call &if with -W 250 --- passes/techmap/abc9.cc | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 41ab9abea..732fc59d7 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -25,7 +25,7 @@ #define ABC_COMMAND_LIB "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put" #define ABC_COMMAND_CTR "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put; buffer; upsize {D}; dnsize {D}; stime -p" //#define ABC_COMMAND_LUT "strash; ifraig; scorr; dc2; dretime; strash; dch -f; if; mfs2" -#define ABC_COMMAND_LUT "&st; &sweep; &scorr; "/*"&dc2; */"&retime; &dch -f; &ps -l; &if; &ps -l" +#define ABC_COMMAND_LUT "&st; &sweep; &scorr; "/*"&dc2; */"&retime; &dch -f; &ps -l; &if -W 250 -v; &ps -l" #define ABC_COMMAND_SOP "strash; ifraig; scorr; dc2; dretime; strash; dch -f; cover {I} {P}" #define ABC_COMMAND_DFL "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put" @@ -1172,6 +1172,11 @@ struct Abc9Pass : public Pass { vector lut_costs; markgroups = false; +#if 0 + cleanup = false; + show_tempdir = true; +#endif + map_mux4 = false; map_mux8 = false; map_mux16 = false; From 854557814ee2cd3902e5871cb0b559ee375e81c5 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 29 May 2019 19:17:36 -0700 Subject: [PATCH 126/213] Erase all boxes before stitching --- passes/techmap/abc9.cc | 57 ++++++++++++++++++++++-------------------- 1 file changed, 30 insertions(+), 27 deletions(-) diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 732fc59d7..2cd599edc 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -596,6 +596,33 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri } } + // Remove all AND, NOT, and ABC box instances + // in preparation for stitching mapped_mod in + pool erased_boxes; + for (auto it = module->cells_.begin(); it != module->cells_.end(); ) { + RTLIL::Cell* cell = it->second; + if (cell->type.in("$_AND_", "$_NOT_")) { + it = module->cells_.erase(it); + continue; + } + RTLIL::Module* box_module = design->module(cell->type); + if (box_module && box_module->attributes.count("\\abc_box_id")) { + erased_boxes.insert(it->first); + it = module->cells_.erase(it); + continue; + } + ++it; + } + // Do the same for module connections + for (auto &it : module->connections_) { + auto &signal = it.first; + auto bits = signal.bits(); + for (auto &b : bits) + if (output_bits.count(b)) + b = module->addWire(NEW_ID); + signal = std::move(bits); + } + std::map cell_stats; for (auto c : mapped_mod->cells()) { @@ -816,16 +843,11 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri module->connect(my_y, my_a); continue; } - else { - cell = module->addCell(remap_name(c->name), c->type); - } - } - else { - cell = module->cell(c->name); - log_assert(cell); - log_assert(c->type == cell->type); } + else + log_assert(erased_boxes.count(c->name)); + cell = module->addCell(remap_name(c->name), c->type); if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx; cell->parameters = c->parameters; for (auto &conn : c->connections()) { @@ -889,25 +911,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri // module->connect(conn); // } - // Remove all AND, NOT, instances - // in preparation for stitching mapped_mod in - for (auto it = module->cells_.begin(); it != module->cells_.end(); ) { - RTLIL::Cell* cell = it->second; - if (cell->type.in("$_AND_", "$_NOT_")) - it = module->cells_.erase(it); - else - ++it; - } - // Do the same for module connections - for (auto &it : module->connections_) { - auto &signal = it.first; - auto bits = signal.bits(); - for (auto &b : bits) - if (output_bits.count(b)) - b = module->addWire(NEW_ID); - signal = std::move(bits); - } - // Stitch in mapped_mod's inputs/outputs into module for (auto &it : mapped_mod->wires_) { RTLIL::Wire *w = it.second; From 276f5f8b811953e79923fe30e85bc34ced88b748 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 29 May 2019 22:55:34 -0700 Subject: [PATCH 127/213] Some more realistic delays... --- techlibs/xilinx/abc.lut | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/techlibs/xilinx/abc.lut b/techlibs/xilinx/abc.lut index 5550a4039..3a7dc268d 100644 --- a/techlibs/xilinx/abc.lut +++ b/techlibs/xilinx/abc.lut @@ -2,13 +2,13 @@ # K area delay 1 1 124 -2 2 124 248 -3 3 124 248 372 -4 3 124 248 372 496 -5 3 124 248 372 496 620 -6 5 124 248 372 496 620 744 +2 2 124 235 +3 3 124 235 399 +4 3 124 235 399 490 +5 3 124 235 399 490 620 +6 5 124 235 399 490 620 632 # F7BMUX -7 10 296 420 544 668 792 916 1040 +7 10 296 420 531 695 756 916 928 # F8MUX # F8MUX+F7BMUX -8 20 273 569 693 817 941 1065 1189 1313 +8 20 273 569 693 804 968 1029 1189 1201 From 2560f92f29af409d69297a3743ade368832e7bfd Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 29 May 2019 23:01:46 -0700 Subject: [PATCH 128/213] Reduce -W to 160 --- passes/techmap/abc9.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 2cd599edc..427aff1b8 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -25,7 +25,7 @@ #define ABC_COMMAND_LIB "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put" #define ABC_COMMAND_CTR "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put; buffer; upsize {D}; dnsize {D}; stime -p" //#define ABC_COMMAND_LUT "strash; ifraig; scorr; dc2; dretime; strash; dch -f; if; mfs2" -#define ABC_COMMAND_LUT "&st; &sweep; &scorr; "/*"&dc2; */"&retime; &dch -f; &ps -l; &if -W 250 -v; &ps -l" +#define ABC_COMMAND_LUT "&st; &sweep; &scorr; "/*"&dc2; */"&retime; &dch -f; &ps -l; &if -W 160 -v; &ps -l" #define ABC_COMMAND_SOP "strash; ifraig; scorr; dc2; dretime; strash; dch -f; cover {I} {P}" #define ABC_COMMAND_DFL "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put" From 8c58c728a79954603289abf3520139da0a9bbb26 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 30 May 2019 00:42:41 -0700 Subject: [PATCH 129/213] Re-enable &dc2 --- passes/techmap/abc9.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 427aff1b8..8966b5c27 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -25,7 +25,7 @@ #define ABC_COMMAND_LIB "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put" #define ABC_COMMAND_CTR "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put; buffer; upsize {D}; dnsize {D}; stime -p" //#define ABC_COMMAND_LUT "strash; ifraig; scorr; dc2; dretime; strash; dch -f; if; mfs2" -#define ABC_COMMAND_LUT "&st; &sweep; &scorr; "/*"&dc2; */"&retime; &dch -f; &ps -l; &if -W 160 -v; &ps -l" +#define ABC_COMMAND_LUT "&st; &sweep; &scorr; &dc2; &retime; &dch -f; &ps -l; &if -W 160 -v; &ps -l" #define ABC_COMMAND_SOP "strash; ifraig; scorr; dc2; dretime; strash; dch -f; cover {I} {P}" #define ABC_COMMAND_DFL "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put" From fdfc18be91123e2939f134dafc12e1e0c1a82f7b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 30 May 2019 01:23:36 -0700 Subject: [PATCH 130/213] Carry in/out to be the last input/output for chains to be preserved --- backends/aiger/xaiger.cc | 38 +++++++++++++++++++++++++++++++++++ frontends/aiger/aigerparse.cc | 38 +++++++++++++++++++++++++++++++++++ techlibs/xilinx/abc.box | 23 ++++++++++++--------- techlibs/xilinx/cells_sim.v | 4 ++-- 4 files changed, 91 insertions(+), 12 deletions(-) diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index bf696bfd6..25de7daba 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -298,6 +298,8 @@ struct XAigerWriter for (auto user_cell : it.second) toposort.edge(driver_cell, user_cell); + pool abc_carry_modules; + toposort.sort(); for (auto cell_name : toposort.sorted) { RTLIL::Cell *cell = module->cell(cell_name); @@ -305,6 +307,42 @@ struct XAigerWriter if (!box_module || !box_module->attributes.count("\\abc_box_id")) continue; + if (box_module->attributes.count("\\abc_carry") && !abc_carry_modules.count(box_module)) { + RTLIL::Wire* carry_in = nullptr, *carry_out = nullptr; + RTLIL::Wire* last_in = nullptr, *last_out = nullptr; + for (const auto &port_name : box_module->ports) { + RTLIL::Wire* w = box_module->wire(port_name); + log_assert(w); + if (w->port_input) { + if (w->attributes.count("\\abc_carry_in")) { + log_assert(!carry_in); + carry_in = w; + } + log_assert(!last_in || last_in->port_id < w->port_id); + last_in = w; + } + if (w->port_output) { + if (w->attributes.count("\\abc_carry_out")) { + log_assert(!carry_out); + carry_out = w; + } + log_assert(!last_out || last_out->port_id < w->port_id); + last_out = w; + } + } + + if (carry_in) { + log_assert(last_in); + std::swap(box_module->ports[carry_in->port_id-1], box_module->ports[last_in->port_id-1]); + std::swap(carry_in->port_id, last_in->port_id); + } + if (carry_out) { + log_assert(last_out); + std::swap(box_module->ports[carry_out->port_id-1], box_module->ports[last_out->port_id-1]); + std::swap(carry_out->port_id, last_out->port_id); + } + } + // Fully pad all unused input connections of this box cell with S0 // Fully pad all undriven output connections of this box cell with anonymous wires // NB: Assume box_module->ports are sorted alphabetically diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 8d7588f88..915c53a1b 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -549,6 +549,7 @@ void AigerReader::post_process() std::string type, symbol; int variable, index; int pi_count = 0, ci_count = 0, co_count = 0; + pool abc_carry_modules; while (mf >> type >> variable >> index >> symbol) { RTLIL::IdString escaped_s = RTLIL::escape_id(symbol); if (type == "input") { @@ -646,6 +647,43 @@ void AigerReader::post_process() module->rename(cell, escaped_s); RTLIL::Module* box_module = design->module(cell->type); log_assert(box_module); + + if (box_module->attributes.count("\\abc_carry") && !abc_carry_modules.count(box_module)) { + RTLIL::Wire* carry_in = nullptr, *carry_out = nullptr; + RTLIL::Wire* last_in = nullptr, *last_out = nullptr; + for (const auto &port_name : box_module->ports) { + RTLIL::Wire* w = box_module->wire(port_name); + log_assert(w); + if (w->port_input) { + if (w->attributes.count("\\abc_carry_in")) { + log_assert(!carry_in); + carry_in = w; + } + log_assert(!last_in || last_in->port_id < w->port_id); + last_in = w; + } + if (w->port_output) { + if (w->attributes.count("\\abc_carry_out")) { + log_assert(!carry_out); + carry_out = w; + } + log_assert(!last_out || last_out->port_id < w->port_id); + last_out = w; + } + } + + if (carry_in != last_in) { + std::swap(box_module->ports[carry_in->port_id], box_module->ports[last_in->port_id]); + std::swap(carry_in->port_id, last_in->port_id); + } + if (carry_out != last_out) { + log_assert(last_out); + std::swap(box_module->ports[carry_out->port_id], box_module->ports[last_out->port_id]); + std::swap(carry_out->port_id, last_out->port_id); + } + } + + // NB: Assume box_module->ports are sorted alphabetically // (as RTLIL::Module::fixup_ports() would do) for (auto port_name : box_module->ports) { diff --git a/techlibs/xilinx/abc.box b/techlibs/xilinx/abc.box index b3972ddb3..6e9e1faf6 100644 --- a/techlibs/xilinx/abc.box +++ b/techlibs/xilinx/abc.box @@ -12,17 +12,20 @@ MUXF8 2 1 3 1 104 94 273 # CARRY4 + CARRY4_[ABCD]X -# Inputs: CI CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 -# Outputs: CO0 CO1 CO2 CO3 O0 O1 O2 O3 +# Inputs: S0 S1 S2 S3 CYINIT DI0 DI1 DI2 DI3 CI +# Outputs: O0 O1 O2 O3 CO0 CO1 CO2 CO3 +# (NB: carry chain input/output must be last input/output, +# swapped with what normally would have been the last +# output, here: CI <-> S, CO <-> O CARRY4 3 1 10 8 -271 536 379 - - - 340 - - - -157 494 465 445 - - 433 469 - - -228 592 540 520 356 - 512 548 292 - -114 580 526 507 398 385 508 528 378 380 -222 482 - - - - 223 - - - -334 598 407 - - - 400 205 - - -239 584 556 537 - - 523 558 226 - -313 642 615 596 438 - 582 618 330 227 +223 - - - 482 - - - - 222 +400 205 - - 598 407 - - - 334 +523 558 226 - 584 556 537 - - 239 +582 618 330 227 642 615 596 438 - 313 +340 - - - 536 379 - - - 271 +433 469 - - 494 465 445 - - 157 +512 548 292 - 592 540 520 356 - 228 +508 528 378 380 580 526 507 398 385 114 # SLICEM/A6LUT # Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 29c79f689..120370860 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -173,8 +173,8 @@ module XORCY(output O, input CI, LI); assign O = CI ^ LI; endmodule -(* abc_box_id = 3, lib_whitebox *) -module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S); +(* abc_box_id = 3, lib_whitebox, abc_carry *) +module CARRY4((* abc_carry_out *) output [3:0] CO, output [3:0] O, (* abc_carry_in *) input CI, input CYINIT, input [3:0] DI, S); assign O = S ^ {CO[2:0], CI | CYINIT}; assign CO[0] = S[0] ? CI | CYINIT : DI[0]; assign CO[1] = S[1] ? CO[0] : DI[1]; From 0800846e73b6502cfaa2000ea433faa5f1f75a3a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 30 May 2019 11:32:14 -0700 Subject: [PATCH 131/213] Do not double count LUT1s --- passes/techmap/abc9.cc | 1 - 1 file changed, 1 deletion(-) diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 8966b5c27..b1bd167a4 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -670,7 +670,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset), driver_lut); } - cell_stats["$lut"]++; } else { cell = module->addCell(remap_name(c->name), "$_NOT_"); From a44fe3a632f6beafe0ba2831bba06bf855d7e89d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 30 May 2019 11:41:50 -0700 Subject: [PATCH 132/213] Revert "Re-enable &dc2" This reverts commit 8c58c728a79954603289abf3520139da0a9bbb26. --- passes/techmap/abc9.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index b1bd167a4..82f149c8c 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -25,7 +25,7 @@ #define ABC_COMMAND_LIB "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put" #define ABC_COMMAND_CTR "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put; buffer; upsize {D}; dnsize {D}; stime -p" //#define ABC_COMMAND_LUT "strash; ifraig; scorr; dc2; dretime; strash; dch -f; if; mfs2" -#define ABC_COMMAND_LUT "&st; &sweep; &scorr; &dc2; &retime; &dch -f; &ps -l; &if -W 160 -v; &ps -l" +#define ABC_COMMAND_LUT "&st; &sweep; &scorr; "/*"&dc2; */"&retime; &dch -f; &ps -l; &if -W 160 -v; &ps -l" #define ABC_COMMAND_SOP "strash; ifraig; scorr; dc2; dretime; strash; dch -f; cover {I} {P}" #define ABC_COMMAND_DFL "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put" From c6fa4faa371ad3dbefe4c57bd758942e461869da Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 30 May 2019 12:25:21 -0700 Subject: [PATCH 133/213] Remove whitespace --- frontends/aiger/aigerparse.cc | 1 - 1 file changed, 1 deletion(-) diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 915c53a1b..7adfacb53 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -683,7 +683,6 @@ void AigerReader::post_process() } } - // NB: Assume box_module->ports are sorted alphabetically // (as RTLIL::Module::fixup_ports() would do) for (auto port_name : box_module->ports) { From e3c8132d7acaae328adeb8d4db1857275b5e8323 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 30 May 2019 12:26:51 -0700 Subject: [PATCH 134/213] Do not re-sort box_module ports --- backends/aiger/xaiger.cc | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 25de7daba..efdd1844b 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -739,10 +739,12 @@ struct XAigerWriter if (box_module->get_bool_attribute("\\whitebox")) holes_cell = holes_module->addCell(cell->name, cell->type); - RTLIL::Wire *holes_wire; - // TODO: Only sort once - box_module->wires_.sort(RTLIL::sort_by_id_str()); - for (const auto w : box_module->wires()) { + // NB: Assume box_module->ports are sorted alphabetically + // (as RTLIL::Module::fixup_ports() would do) + for (const auto &port_name : box_module->ports) { + RTLIL::Wire *w = box_module->wire(port_name); + log_assert(w); + RTLIL::Wire *holes_wire; RTLIL::SigSpec port_wire; if (w->port_input) { for (int i = 0; i < GetSize(w); i++) { From 1ad33c3b5ac91fc4e6cb6e2ff4b606a693838c2b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 30 May 2019 13:07:29 -0700 Subject: [PATCH 135/213] Remove whitebox attribute from DRAMs for now --- techlibs/xilinx/cells_sim.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 120370860..7337e0ea7 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -281,7 +281,7 @@ module FDPE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, PRE); always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; endmodule -(* abc_box_id = 4, lib_whitebox *) +(* abc_box_id = 4 /*, lib_whitebox*/ *) module RAM64X1D ( output DPO, SPO, input D, WCLK, WE, @@ -301,7 +301,7 @@ module RAM64X1D ( `endif endmodule -(* abc_box_id = 5, lib_whitebox *) +(* abc_box_id = 5 /*, lib_whitebox*/ *) module RAM128X1D ( output DPO, SPO, input D, WCLK, WE, From 4a6b9af227cb22e89fd463c665016544060d2acd Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 30 May 2019 15:50:47 -0700 Subject: [PATCH 136/213] Fix spelling --- passes/techmap/abc9.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 82f149c8c..4bda388de 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -924,7 +924,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri else { // Attempt another wideports_split here because there // exists the possibility that different bits of a port - // could be an input and output, therefore parse_xiager() + // could be an input and output, therefore parse_xaiger() // could not combine it into a wideport auto r = wideports_split(w->name.str()); wire = module->wire(r.first); From a41553a86125d58a0811975aa8636388615ba239 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 30 May 2019 16:02:40 -0700 Subject: [PATCH 137/213] read_xaiger() to name box signals --- frontends/aiger/aigerparse.cc | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 7adfacb53..399e46737 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -689,23 +689,27 @@ void AigerReader::post_process() RTLIL::Wire* w = box_module->wire(port_name); log_assert(w); RTLIL::SigSpec rhs; + RTLIL::Wire* wire = nullptr; for (int i = 0; i < GetSize(w); i++) { if (w->port_input) { log_assert(static_cast(co_count) < outputs.size()); - RTLIL::Wire* wire = outputs[co_count++]; + wire = outputs[co_count++]; log_assert(wire); log_assert(wire->port_output); wire->port_output = false; - rhs.append(wire); } if (w->port_output) { log_assert(static_cast(pi_count + ci_count) < inputs.size()); - RTLIL::Wire* wire = inputs[pi_count + ci_count++]; + wire = inputs[pi_count + ci_count++]; log_assert(wire); log_assert(wire->port_input); wire->port_input = false; - rhs.append(wire); } + rhs.append(wire); + if (GetSize(w) == 1) + module->rename(wire, RTLIL::escape_id(stringf("%s.%s", log_id(cell), log_id(port_name)))); + else + module->rename(wire, RTLIL::escape_id(stringf("%s.%s[%d]", log_id(cell), log_id(port_name), i))); } cell->setPort(port_name, rhs); } From 887c31f33b82e5cb3f50523873d41ceb0cb8e7f4 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 30 May 2019 16:03:22 -0700 Subject: [PATCH 138/213] Fix issue where keep signal became PI, but also box was adding CI driver --- backends/aiger/xaiger.cc | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index efdd1844b..cd15b6160 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -392,6 +392,12 @@ struct XAigerWriter if (O != b) alias_map[O] = b; undriven_bits.erase(O); + + auto jt = input_bits.find(b); + if (jt != input_bits.end()) { + log_assert(b.wire->attributes.count("\\keep")); + input_bits.erase(b); + } } } } @@ -409,9 +415,10 @@ struct XAigerWriter if ((wire->port_input && wire->port_output && !undriven_bits.count(bit)) || wire->attributes.count("\\keep")) { log_assert(input_bits.count(bit) && output_bits.count(bit)); - RTLIL::Wire *new_wire = module->wire(wire->name.str() + "$inout.out"); + RTLIL::IdString wire_name = wire->name.str() + "$inout.out"; + RTLIL::Wire *new_wire = module->wire(wire_name); if (!new_wire) - new_wire = module->addWire(wire->name.str() + "$inout.out", GetSize(wire)); + new_wire = module->addWire(wire_name, GetSize(wire)); SigBit new_bit(new_wire, bit.offset); module->connect(new_bit, bit); if (not_map.count(bit)) @@ -468,12 +475,15 @@ struct XAigerWriter for (auto bit : input_bits) { aig_m++, aig_i++; + log_assert(!aig_map.count(bit)); aig_map[bit] = 2*aig_m; } for (auto &c : ci_bits) { + RTLIL::SigBit bit = std::get<0>(c); aig_m++, aig_i++; - aig_map[std::get<0>(c)] = 2*aig_m; + log_assert(!aig_map.count(bit)); + aig_map[bit] = 2*aig_m; } if (imode && input_bits.empty()) { @@ -538,8 +548,7 @@ struct XAigerWriter for (auto &c : co_bits) { RTLIL::SigBit bit = std::get<0>(c); - std::get<4>(c) = aig_o++; - ordered_outputs[bit] = std::get<4>(c); + std::get<4>(c) = ordered_outputs[bit] = aig_o++; aig_outputs.push_back(bit2aig(bit)); } @@ -720,10 +729,15 @@ struct XAigerWriter if (omode && num_outputs == 0) num_outputs = 1; write_h_buffer(1); + log_debug("ciNum = %zu\n", input_bits.size() + ci_bits.size()); write_h_buffer(input_bits.size() + ci_bits.size()); + log_debug("coNum = %zu\n", num_outputs + co_bits.size()); write_h_buffer(num_outputs + co_bits.size()); + log_debug("piNum = %zu\n", input_bits.size()); write_h_buffer(input_bits.size()); + log_debug("poNum = %d\n", num_outputs); write_h_buffer(num_outputs); + log_debug("boxNum = %zu\n", box_list.size()); write_h_buffer(box_list.size()); RTLIL::Module *holes_module = nullptr; From a379234f56753c3d72a6966c380ac6f83fde789c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 31 May 2019 12:50:11 -0700 Subject: [PATCH 139/213] Throw out unused code inherited from abc --- passes/techmap/abc9.cc | 215 +---------------------------------------- 1 file changed, 3 insertions(+), 212 deletions(-) diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 4bda388de..f14828745 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -467,48 +467,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri { log_header(design, "Executing ABC9.\n"); - std::string buffer = stringf("%s/stdcells.genlib", tempdir_name.c_str()); - f = fopen(buffer.c_str(), "wt"); - if (f == NULL) - log_error("Opening %s for writing failed: %s\n", buffer.c_str(), strerror(errno)); - fprintf(f, "GATE ZERO 1 Y=CONST0;\n"); - fprintf(f, "GATE ONE 1 Y=CONST1;\n"); - fprintf(f, "GATE BUF %d Y=A; PIN * NONINV 1 999 1 0 1 0\n", get_cell_cost("$_BUF_")); - fprintf(f, "GATE NOT %d Y=!A; PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_NOT_")); - if (enabled_gates.empty() || enabled_gates.count("AND")) - fprintf(f, "GATE AND %d Y=A*B; PIN * NONINV 1 999 1 0 1 0\n", get_cell_cost("$_AND_")); - if (enabled_gates.empty() || enabled_gates.count("NAND")) - fprintf(f, "GATE NAND %d Y=!(A*B); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_NAND_")); - if (enabled_gates.empty() || enabled_gates.count("OR")) - fprintf(f, "GATE OR %d Y=A+B; PIN * NONINV 1 999 1 0 1 0\n", get_cell_cost("$_OR_")); - if (enabled_gates.empty() || enabled_gates.count("NOR")) - fprintf(f, "GATE NOR %d Y=!(A+B); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_NOR_")); - if (enabled_gates.empty() || enabled_gates.count("XOR")) - fprintf(f, "GATE XOR %d Y=(A*!B)+(!A*B); PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_XOR_")); - if (enabled_gates.empty() || enabled_gates.count("XNOR")) - fprintf(f, "GATE XNOR %d Y=(A*B)+(!A*!B); PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_XNOR_")); - if (enabled_gates.empty() || enabled_gates.count("ANDNOT")) - fprintf(f, "GATE ANDNOT %d Y=A*!B; PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_ANDNOT_")); - if (enabled_gates.empty() || enabled_gates.count("ORNOT")) - fprintf(f, "GATE ORNOT %d Y=A+!B; PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_ORNOT_")); - if (enabled_gates.empty() || enabled_gates.count("AOI3")) - fprintf(f, "GATE AOI3 %d Y=!((A*B)+C); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_AOI3_")); - if (enabled_gates.empty() || enabled_gates.count("OAI3")) - fprintf(f, "GATE OAI3 %d Y=!((A+B)*C); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_OAI3_")); - if (enabled_gates.empty() || enabled_gates.count("AOI4")) - fprintf(f, "GATE AOI4 %d Y=!((A*B)+(C*D)); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_AOI4_")); - if (enabled_gates.empty() || enabled_gates.count("OAI4")) - fprintf(f, "GATE OAI4 %d Y=!((A+B)*(C+D)); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_OAI4_")); - if (enabled_gates.empty() || enabled_gates.count("MUX")) - fprintf(f, "GATE MUX %d Y=(A*B)+(S*B)+(!S*A); PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_MUX_")); - if (map_mux4) - fprintf(f, "GATE MUX4 %d Y=(!S*!T*A)+(S*!T*B)+(!S*T*C)+(S*T*D); PIN * UNKNOWN 1 999 1 0 1 0\n", 2*get_cell_cost("$_MUX_")); - if (map_mux8) - fprintf(f, "GATE MUX8 %d Y=(!S*!T*!U*A)+(S*!T*!U*B)+(!S*T*!U*C)+(S*T*!U*D)+(!S*!T*U*E)+(S*!T*U*F)+(!S*T*U*G)+(S*T*U*H); PIN * UNKNOWN 1 999 1 0 1 0\n", 4*get_cell_cost("$_MUX_")); - if (map_mux16) - fprintf(f, "GATE MUX16 %d Y=(!S*!T*!U*!V*A)+(S*!T*!U*!V*B)+(!S*T*!U*!V*C)+(S*T*!U*!V*D)+(!S*!T*U*!V*E)+(S*!T*U*!V*F)+(!S*T*U*!V*G)+(S*T*U*!V*H)+(!S*!T*!U*V*I)+(S*!T*!U*V*J)+(!S*T*!U*V*K)+(S*T*!U*V*L)+(!S*!T*U*V*M)+(S*!T*U*V*N)+(!S*T*U*V*O)+(S*T*U*V*P); PIN * UNKNOWN 1 999 1 0 1 0\n", 8*get_cell_cost("$_MUX_")); - fclose(f); - + std::string buffer; if (!lut_costs.empty()) { buffer = stringf("%s/lutdefs.txt", tempdir_name.c_str()); f = fopen(buffer.c_str(), "wt"); @@ -680,161 +639,9 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx; continue; } - - cell_stats[RTLIL::unescape_id(c->type)]++; - if (c->type == "\\ZERO" || c->type == "\\ONE") { - RTLIL::SigSig conn; - conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]); - conn.second = RTLIL::SigSpec(c->type == "\\ZERO" ? 0 : 1, 1); - module->connect(conn); - continue; - } - if (c->type == "\\BUF") { - RTLIL::SigSig conn; - conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)]); - conn.second = RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]); - module->connect(conn); - continue; - } - - if (c->type == "\\AND" || c->type == "\\OR" || c->type == "\\XOR" || c->type == "\\NAND" || c->type == "\\NOR" || - c->type == "\\XNOR" || c->type == "\\ANDNOT" || c->type == "\\ORNOT") { - RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_"); - if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx; - cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)])); - cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)])); - cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)])); - continue; - } - if (c->type == "\\MUX") { - RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX_"); - if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx; - cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)])); - cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)])); - cell->setPort("\\S", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\S").as_wire()->name)])); - cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)])); - continue; - } - if (c->type == "\\MUX4") { - RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX4_"); - if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx; - cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)])); - cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)])); - cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)])); - cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)])); - cell->setPort("\\S", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\S").as_wire()->name)])); - cell->setPort("\\T", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\T").as_wire()->name)])); - cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)])); - continue; - } - if (c->type == "\\MUX8") { - RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX8_"); - if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx; - cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)])); - cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)])); - cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)])); - cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)])); - cell->setPort("\\E", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\E").as_wire()->name)])); - cell->setPort("\\F", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\F").as_wire()->name)])); - cell->setPort("\\G", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\G").as_wire()->name)])); - cell->setPort("\\H", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\H").as_wire()->name)])); - cell->setPort("\\S", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\S").as_wire()->name)])); - cell->setPort("\\T", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\T").as_wire()->name)])); - cell->setPort("\\U", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\U").as_wire()->name)])); - cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)])); - continue; - } - if (c->type == "\\MUX16") { - RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_MUX16_"); - if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx; - cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)])); - cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)])); - cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)])); - cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)])); - cell->setPort("\\E", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\E").as_wire()->name)])); - cell->setPort("\\F", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\F").as_wire()->name)])); - cell->setPort("\\G", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\G").as_wire()->name)])); - cell->setPort("\\H", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\H").as_wire()->name)])); - cell->setPort("\\I", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\I").as_wire()->name)])); - cell->setPort("\\J", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\J").as_wire()->name)])); - cell->setPort("\\K", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\K").as_wire()->name)])); - cell->setPort("\\L", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\L").as_wire()->name)])); - cell->setPort("\\M", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\M").as_wire()->name)])); - cell->setPort("\\N", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\N").as_wire()->name)])); - cell->setPort("\\O", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\O").as_wire()->name)])); - cell->setPort("\\P", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\P").as_wire()->name)])); - cell->setPort("\\S", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\S").as_wire()->name)])); - cell->setPort("\\T", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\T").as_wire()->name)])); - cell->setPort("\\U", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\U").as_wire()->name)])); - cell->setPort("\\V", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\V").as_wire()->name)])); - cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)])); - continue; - } - if (c->type == "\\AOI3" || c->type == "\\OAI3") { - RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_"); - if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx; - cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)])); - cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)])); - cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)])); - cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)])); - continue; - } - if (c->type == "\\AOI4" || c->type == "\\OAI4") { - RTLIL::Cell *cell = module->addCell(remap_name(c->name), "$_" + c->type.substr(1) + "_"); - if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx; - cell->setPort("\\A", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\A").as_wire()->name)])); - cell->setPort("\\B", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\B").as_wire()->name)])); - cell->setPort("\\C", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\C").as_wire()->name)])); - cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)])); - cell->setPort("\\Y", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)])); - continue; - } - if (c->type == "\\DFF") { - log_assert(clk_sig.size() == 1); - RTLIL::Cell *cell; - if (en_sig.size() == 0) { - cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_"); - } else { - log_assert(en_sig.size() == 1); - cell = module->addCell(remap_name(c->name), stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N')); - cell->setPort("\\E", en_sig); - } - if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx; - cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)])); - cell->setPort("\\Q", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Q").as_wire()->name)])); - cell->setPort("\\C", clk_sig); - continue; - } } - else - cell_stats[RTLIL::unescape_id(c->type)]++; + cell_stats[RTLIL::unescape_id(c->type)]++; - if (c->type == "\\_const0_" || c->type == "\\_const1_") { - RTLIL::SigSig conn; - conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->connections().begin()->second.as_wire()->name)]); - conn.second = RTLIL::SigSpec(c->type == "\\_const0_" ? 0 : 1, 1); - module->connect(conn); - continue; - } - - if (c->type == "\\_dff_") { - log_assert(clk_sig.size() == 1); - RTLIL::Cell *cell; - if (en_sig.size() == 0) { - cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_"); - } else { - log_assert(en_sig.size() == 1); - cell = module->addCell(remap_name(c->name), stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N')); - cell->setPort("\\E", en_sig); - } - if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx; - cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)])); - cell->setPort("\\Q", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Q").as_wire()->name)])); - cell->setPort("\\C", clk_sig); - continue; - } - - RTLIL::Cell* cell; if (c->type == "$lut") { if (GetSize(c->getPort("\\A")) == 1 && c->getParam("\\LUT").as_int() == 2) { SigSpec my_a = module->wires_[remap_name(c->getPort("\\A").as_wire()->name)]; @@ -846,7 +653,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri else log_assert(erased_boxes.count(c->name)); - cell = module->addCell(remap_name(c->name), c->type); + RTLIL::Cell* cell = module->addCell(remap_name(c->name), c->type); if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx; cell->parameters = c->parameters; for (auto &conn : c->connections()) { @@ -893,22 +700,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri for (auto &it : cell_stats) log("ABC RESULTS: %15s cells: %8d\n", it.first.c_str(), it.second); int in_wires = 0, out_wires = 0; - //for (auto &si : signal_list) - // if (si.is_port) { - // char buffer[100]; - // snprintf(buffer, 100, "\\n%d", si.id); - // RTLIL::SigSig conn; - // if (si.type != G(NONE)) { - // conn.first = si.bit; - // conn.second = RTLIL::SigSpec(module->wires_[remap_name(buffer)]); - // out_wires++; - // } else { - // conn.first = RTLIL::SigSpec(module->wires_[remap_name(buffer)]); - // conn.second = si.bit; - // in_wires++; - // } - // module->connect(conn); - // } // Stitch in mapped_mod's inputs/outputs into module for (auto &it : mapped_mod->wires_) { From 4623177655892c4aaf68757efff89aa748090c58 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 31 May 2019 15:23:33 -0700 Subject: [PATCH 140/213] ABC9 to understand flops --- backends/aiger/xaiger.cc | 73 +++++++++++++++------------------------- 1 file changed, 27 insertions(+), 46 deletions(-) diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 7a139f68f..90fea2db1 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -181,7 +181,6 @@ struct XAigerWriter for (auto cell : module->cells()) { RTLIL::Module* inst_module = module->design->module(cell->type); - bool inst_flop = inst_module ? inst_module->attributes.count("\\abc_flop") : false; bool known_type = yosys_celltypes.cell_known(cell->type); if (!holes_mode) { @@ -258,22 +257,28 @@ struct XAigerWriter // continue; //} + bool inst_flop = inst_module ? inst_module->attributes.count("\\abc_flop") : false; if (inst_flop) { SigBit d, q; for (const auto &c : cell->connections()) { + auto is_input = cell->input(c.first); + auto is_output = cell->output(c.first); + log_assert(is_input || is_output); + RTLIL::Wire* port = inst_module->wire(c.first); for (auto b : c.second.bits()) { - auto is_input = cell->input(c.first); - auto is_output = cell->output(c.first); - log_assert(is_input || is_output); - if (is_input && inst_module->wire(c.first)->attributes.count("\\abc_flop_d")) { - SigBit I = sigmap(b); - if (I != b) - alias_map[b] = I; + if (is_input && port->attributes.count("\\abc_flop_d")) { d = b; + SigBit I = sigmap(d); + if (I != d) + alias_map[I] = d; + unused_bits.erase(d); } - if (is_output && inst_module->wire(c.first)->attributes.count("\\abc_flop_q")) { - SigBit O = sigmap(b); - q = O; + if (is_output && port->attributes.count("\\abc_flop_q")) { + q = b; + SigBit O = sigmap(q); + if (O != q) + alias_map[O] = q; + undriven_bits.erase(O); } } } @@ -281,7 +286,6 @@ struct XAigerWriter abc_box_seen = inst_module->attributes.count("\\abc_box_id"); ff_bits.emplace_back(d, q); - undriven_bits.erase(q); } else if (inst_module && inst_module->attributes.count("\\abc_box_id")) { abc_box_seen = true; @@ -507,8 +511,9 @@ struct XAigerWriter } for (auto &f : ff_bits) { - auto bit = f.second; + RTLIL::SigBit bit = f.second; aig_m++, aig_i++; + log_assert(!aig_map.count(bit)); aig_map[bit] = 2*aig_m; } @@ -516,12 +521,9 @@ struct XAigerWriter for (auto &c : ci_bits) { RTLIL::SigBit bit = std::get<0>(c); aig_m++, aig_i++; - log_assert(!aig_map.count(bit)); - aig_map[bit] = 2*aig_m; - //auto r = aig_map.insert(std::make_pair(c.first, c.second)); - //if (!r.second) { - // ff_aig_map[std::get<0>(c)] = 2*aig_m; - //} + auto r = aig_map.insert(std::make_pair(bit, 2*aig_m)); + if (!r.second) + ff_aig_map[bit] = 2*aig_m; } if (imode && input_bits.empty()) { @@ -597,7 +599,8 @@ struct XAigerWriter for (auto &f : ff_bits) { aig_o++; - aig_outputs.push_back(ff_aig_map.at(f.second)); + RTLIL::SigBit bit = f.second; + aig_outputs.push_back(ff_aig_map.at(bit)); } if (omode && output_bits.empty()) { @@ -778,8 +781,8 @@ struct XAigerWriter write_h_buffer(num_outputs + ff_bits.size()+ co_bits.size()); log_debug("piNum = %zu\n", input_bits.size() + ff_bits.size()); write_h_buffer(input_bits.size()+ ff_bits.size()); - log_debug("poNum = %d\n", num_outputs); - write_h_buffer(num_outputs); + log_debug("poNum = %zu\n", num_outputs + ff_bits.size()); + write_h_buffer(num_outputs + ff_bits.size()); log_debug("boxNum = %zu\n", box_list.size()); write_h_buffer(box_list.size()); @@ -856,7 +859,7 @@ struct XAigerWriter f.write(reinterpret_cast(&buffer_size_be), sizeof(buffer_size_be)); f.write(buffer_str.data(), buffer_str.size()); - if (!ff_bits.empty()) { + /*if (!ff_bits.empty())*/ { std::stringstream r_buffer; auto write_r_buffer = [&r_buffer](int i32) { // TODO: Don't assume we're on little endian @@ -867,6 +870,7 @@ struct XAigerWriter #endif r_buffer.write(reinterpret_cast(&i32_be), sizeof(i32_be)); }; + log_debug("flopNum = %zu\n", ff_bits.size()); write_r_buffer(ff_bits.size()); int mergeability_class = 1; for (auto cell : ff_bits) @@ -923,29 +927,6 @@ struct XAigerWriter f.write(buffer_str.data(), buffer_str.size()); holes_module->design->remove(holes_module); } - - std::stringstream r_buffer; - auto write_r_buffer = [&r_buffer](int i32) { - // TODO: Don't assume we're on little endian -#ifdef _WIN32 - int i32_be = _byteswap_ulong(i32); -#else - int i32_be = __builtin_bswap32(i32); -#endif - r_buffer.write(reinterpret_cast(&i32_be), sizeof(i32_be)); - }; - write_r_buffer(0); - - f << "r"; - buffer_str = r_buffer.str(); - // TODO: Don't assume we're on little endian -#ifdef _WIN32 - buffer_size_be = _byteswap_ulong(buffer_str.size()); -#else - buffer_size_be = __builtin_bswap32(buffer_str.size()); -#endif - f.write(reinterpret_cast(&buffer_size_be), sizeof(buffer_size_be)); - f.write(buffer_str.data(), buffer_str.size()); } f << stringf("Generated by %s\n", yosys_version_str); From e3d160a9cac9f134c40a03946dc97c957ebfa930 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 31 May 2019 18:06:36 -0700 Subject: [PATCH 141/213] parse_xaiger to cope with flops --- frontends/aiger/aigerparse.cc | 204 ++++++++++++++++++++-------------- frontends/aiger/aigerparse.h | 2 + 2 files changed, 123 insertions(+), 83 deletions(-) diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 69404b19d..0e210c456 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -75,6 +75,8 @@ end_of_header: log_debug("M=%u I=%u L=%u O=%u A=%u B=%u C=%u J=%u F=%u\n", M, I, L, O, A, B, C, J, F); line_count = 1; + piNum = 0; + flopNum = 0; if (header == "aag") parse_aiger_ascii(); @@ -184,6 +186,8 @@ void AigerReader::parse_xaiger() log_debug("M=%u I=%u L=%u O=%u A=%u\n", M, I, L, O, A); line_count = 1; + piNum = 0; + flopNum = 0; if (header == "aag") parse_aiger_ascii(); @@ -250,22 +254,10 @@ void AigerReader::parse_xaiger() } } else if (c == 'r') { - /*uint32_t dataSize =*/ parse_xaiger_literal(f); - uint32_t flopNum = parse_xaiger_literal(f); + uint32_t dataSize = parse_xaiger_literal(f); + flopNum = parse_xaiger_literal(f); + log_assert(dataSize == (flopNum+1) * sizeof(uint32_t)); f.ignore(flopNum * sizeof(uint32_t)); - log_assert(inputs.size() >= flopNum); - for (auto it = inputs.end() - flopNum; it != inputs.end(); ++it) { - log_assert((*it)->port_input); - (*it)->port_input = false; - } - inputs.erase(inputs.end() - flopNum, inputs.end()); - log_assert(outputs.size() >= flopNum); - for (auto it = outputs.end() - flopNum; it != outputs.end(); ++it) { - log_assert((*it)->port_output); - (*it)->port_output = false; - } - outputs.erase(outputs.end() - flopNum, outputs.end()); - module->fixup_ports(); } else if (c == 'n') { parse_xaiger_literal(f); @@ -276,14 +268,23 @@ void AigerReader::parse_xaiger() f.ignore(sizeof(uint32_t)); uint32_t version = parse_xaiger_literal(f); log_assert(version == 1); - f.ignore(4*sizeof(uint32_t)); + uint32_t ciNum = parse_xaiger_literal(f); + log_debug("ciNum = %u\n", ciNum); + uint32_t coNum = parse_xaiger_literal(f); + log_debug("coNum = %u\n", coNum); + piNum = parse_xaiger_literal(f); + log_debug("piNum = %u\n", piNum); + uint32_t poNum = parse_xaiger_literal(f); + log_debug("poNum = %u\n", poNum); uint32_t boxNum = parse_xaiger_literal(f); + log_debug("boxNum = %u\n", poNum); for (unsigned i = 0; i < boxNum; i++) { f.ignore(2*sizeof(uint32_t)); uint32_t boxUniqueId = parse_xaiger_literal(f); log_assert(boxUniqueId > 0); uint32_t oldBoxNum = parse_xaiger_literal(f); - module->addCell(stringf("$__box%u__", oldBoxNum), box_lookup.at(boxUniqueId)); + RTLIL::Cell* cell = module->addCell(stringf("$__box%u__", oldBoxNum), box_lookup.at(boxUniqueId)); + boxes.emplace_back(cell); } } else if (c == 'a' || c == 'i' || c == 'o') { @@ -560,14 +561,100 @@ void AigerReader::parse_aiger_binary() void AigerReader::post_process() { + pool abc_carry_modules; + unsigned ci_count = 0, co_count = 0, flop_count = 0; + for (auto cell : boxes) { + RTLIL::Module* box_module = design->module(cell->type); + log_assert(box_module); + + if (box_module->attributes.count("\\abc_carry") && !abc_carry_modules.count(box_module)) { + RTLIL::Wire* carry_in = nullptr, *carry_out = nullptr; + RTLIL::Wire* last_in = nullptr, *last_out = nullptr; + for (const auto &port_name : box_module->ports) { + RTLIL::Wire* w = box_module->wire(port_name); + log_assert(w); + if (w->port_input) { + if (w->attributes.count("\\abc_carry_in")) { + log_assert(!carry_in); + carry_in = w; + } + log_assert(!last_in || last_in->port_id < w->port_id); + last_in = w; + } + if (w->port_output) { + if (w->attributes.count("\\abc_carry_out")) { + log_assert(!carry_out); + carry_out = w; + } + log_assert(!last_out || last_out->port_id < w->port_id); + last_out = w; + } + } + + if (carry_in != last_in) { + std::swap(box_module->ports[carry_in->port_id], box_module->ports[last_in->port_id]); + std::swap(carry_in->port_id, last_in->port_id); + } + if (carry_out != last_out) { + log_assert(last_out); + std::swap(box_module->ports[carry_out->port_id], box_module->ports[last_out->port_id]); + std::swap(carry_out->port_id, last_out->port_id); + } + } + + bool flop = box_module->attributes.count("\\abc_flop"); + log_assert(!flop || flop_count < flopNum); + + // NB: Assume box_module->ports are sorted alphabetically + // (as RTLIL::Module::fixup_ports() would do) + for (auto port_name : box_module->ports) { + RTLIL::Wire* w = box_module->wire(port_name); + log_assert(w); + RTLIL::SigSpec rhs; + RTLIL::Wire* wire = nullptr; + for (int i = 0; i < GetSize(w); i++) { + if (w->port_input) { + log_assert(co_count < outputs.size()); + wire = outputs[co_count++]; + log_assert(wire); + log_assert(wire->port_output); + wire->port_output = false; + + if (flop && w->attributes.count("\\abc_flop_d")) { + RTLIL::Wire* d = outputs[outputs.size() - flopNum + flop_count]; + log_assert(d); + log_assert(d->port_output); + d->port_output = false; + } + } + if (w->port_output) { + log_assert((piNum + ci_count) < inputs.size()); + wire = inputs[piNum + ci_count++]; + log_assert(wire); + log_assert(wire->port_input); + wire->port_input = false; + + if (flop && w->attributes.count("\\abc_flop_q")) { + wire = inputs[piNum - flopNum + flop_count]; + log_assert(wire); + log_assert(wire->port_input); + wire->port_input = false; + } + } + rhs.append(wire); + } + cell->setPort(port_name, rhs); + } + + if (flop) flop_count++; + } + dict wideports_cache; if (!map_filename.empty()) { std::ifstream mf(map_filename); std::string type, symbol; int variable, index; - int pi_count = 0, ci_count = 0, co_count = 0; - pool abc_carry_modules; while (mf >> type >> variable >> index >> symbol) { RTLIL::IdString escaped_s = RTLIL::escape_id(symbol); if (type == "input") { @@ -575,7 +662,6 @@ void AigerReader::post_process() RTLIL::Wire* wire = inputs[variable]; log_assert(wire); log_assert(wire->port_input); - pi_count++; if (index == 0) { // Cope with the fact that a CI might be identical @@ -661,75 +747,27 @@ void AigerReader::post_process() } else if (type == "box") { RTLIL::Cell* cell = module->cell(stringf("$__box%d__", variable)); - if (cell) { + if (cell) { // ABC could have optimised this box away module->rename(cell, escaped_s); RTLIL::Module* box_module = design->module(cell->type); log_assert(box_module); - if (box_module->attributes.count("\\abc_carry") && !abc_carry_modules.count(box_module)) { - RTLIL::Wire* carry_in = nullptr, *carry_out = nullptr; - RTLIL::Wire* last_in = nullptr, *last_out = nullptr; - for (const auto &port_name : box_module->ports) { - RTLIL::Wire* w = box_module->wire(port_name); - log_assert(w); - if (w->port_input) { - if (w->attributes.count("\\abc_carry_in")) { - log_assert(!carry_in); - carry_in = w; - } - log_assert(!last_in || last_in->port_id < w->port_id); - last_in = w; - } - if (w->port_output) { - if (w->attributes.count("\\abc_carry_out")) { - log_assert(!carry_out); - carry_out = w; - } - log_assert(!last_out || last_out->port_id < w->port_id); - last_out = w; + for (const auto &i : cell->connections()) { + RTLIL::IdString port_name = i.first; + RTLIL::SigSpec rhs = i.second; + int index = 0; + for (auto bit : rhs.bits()) { + RTLIL::Wire* wire = bit.wire; + RTLIL::IdString escaped_s = RTLIL::escape_id(stringf("%s.%s", log_id(cell), log_id(port_name))); + if (index == 0) + module->rename(wire, escaped_s); + else if (index > 0) { + module->rename(wire, stringf("%s[%d]", escaped_s.c_str(), index)); + if (wideports) + wideports_cache[escaped_s] = std::max(wideports_cache[escaped_s], index); } + index++; } - - if (carry_in != last_in) { - std::swap(box_module->ports[carry_in->port_id], box_module->ports[last_in->port_id]); - std::swap(carry_in->port_id, last_in->port_id); - } - if (carry_out != last_out) { - log_assert(last_out); - std::swap(box_module->ports[carry_out->port_id], box_module->ports[last_out->port_id]); - std::swap(carry_out->port_id, last_out->port_id); - } - } - - // NB: Assume box_module->ports are sorted alphabetically - // (as RTLIL::Module::fixup_ports() would do) - for (auto port_name : box_module->ports) { - RTLIL::Wire* w = box_module->wire(port_name); - log_assert(w); - RTLIL::SigSpec rhs; - RTLIL::Wire* wire = nullptr; - for (int i = 0; i < GetSize(w); i++) { - if (w->port_input) { - log_assert(static_cast(co_count) < outputs.size()); - wire = outputs[co_count++]; - log_assert(wire); - log_assert(wire->port_output); - wire->port_output = false; - } - if (w->port_output) { - log_assert(static_cast(pi_count + ci_count) < inputs.size()); - wire = inputs[pi_count + ci_count++]; - log_assert(wire); - log_assert(wire->port_input); - wire->port_input = false; - } - rhs.append(wire); - if (GetSize(w) == 1) - module->rename(wire, RTLIL::escape_id(stringf("%s.%s", log_id(cell), log_id(port_name)))); - else - module->rename(wire, RTLIL::escape_id(stringf("%s.%s[%d]", log_id(cell), log_id(port_name), i))); - } - cell->setPort(port_name, rhs); } } } diff --git a/frontends/aiger/aigerparse.h b/frontends/aiger/aigerparse.h index 8c9f3a0c9..28f40279b 100644 --- a/frontends/aiger/aigerparse.h +++ b/frontends/aiger/aigerparse.h @@ -37,10 +37,12 @@ struct AigerReader unsigned M, I, L, O, A; unsigned B, C, J, F; // Optional in AIGER 1.9 unsigned line_count; + uint32_t piNum, flopNum; std::vector inputs; std::vector latches; std::vector outputs; + std::vector boxes; AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename, bool wideports); void parse_aiger(); From dea36d4366109441e84e2e84afcfd8eb0223c902 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 31 May 2019 18:10:25 -0700 Subject: [PATCH 142/213] Techmap flops before ABC again --- techlibs/xilinx/synth_xilinx.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index cc667b919..97464ffe4 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -282,7 +282,9 @@ struct SynthXilinxPass : public ScriptPass } if (check_label("map_cells")) { - run("techmap -map +/techmap.v -map +/xilinx/cells_map.v"); + run("techmap -map +/techmap.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v "); + run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " + "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT"); run("clean"); } @@ -299,9 +301,7 @@ struct SynthXilinxPass : public ScriptPass // has performed any necessary retiming if (!nosrl || help_mode) run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')"); - run("techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v"); - run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " - "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT"); + run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v"); run("clean"); } From 01f71085f281d4721386018c90d3f95b2864df5b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 31 May 2019 18:11:24 -0700 Subject: [PATCH 143/213] Add FD*E_1 -> FD*E techmap rules --- techlibs/xilinx/cells_sim.v | 36 +++++++++++++++++++++++++++++++----- 1 file changed, 31 insertions(+), 5 deletions(-) diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 7337e0ea7..cce03980d 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -173,7 +173,7 @@ module XORCY(output O, input CI, LI); assign O = CI ^ LI; endmodule -(* abc_box_id = 3, lib_whitebox, abc_carry *) +(* abc_box_id = 3, abc_carry, lib_whitebox *) module CARRY4((* abc_carry_out *) output [3:0] CO, output [3:0] O, (* abc_carry_in *) input CI, input CYINIT, input [3:0] DI, S); assign O = S ^ {CO[2:0], CI | CYINIT}; assign CO[0] = S[0] ? CI | CYINIT : DI[0]; @@ -205,56 +205,82 @@ endmodule `endif -module FDRE ((* abc_flop_q *) output reg Q, input C, CE, input D, R); +(* abc_box_id = 6, abc_flop /*, lib_whitebox */ *) +module FDRE ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input D, input R); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_R_INVERTED = 1'b0; initial Q <= INIT; +`ifndef _ABC generate case (|IS_C_INVERTED) 1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; 1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; endcase endgenerate +`else + always @* if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; +`endif endmodule -module FDSE ((* abc_flop_q *) output reg Q, input C, CE, D, S); +(* abc_box_id = 7, abc_flop /*, lib_whitebox*/ *) +module FDSE ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input D, input S); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_S_INVERTED = 1'b0; initial Q <= INIT; +`ifndef _ABC generate case (|IS_C_INVERTED) 1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; 1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; endcase endgenerate +`else + always @* if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; +`endif endmodule -module FDCE ((* abc_flop_q *) output reg Q, input C, CE, D, CLR); +(* abc_box_id = 8, abc_flop /*, lib_whitebox*/ *) +module FDCE ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input D, input CLR); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_CLR_INVERTED = 1'b0; initial Q <= INIT; generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED}) +`ifndef _ABC 2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; 2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; 2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; 2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; endcase endgenerate +`else + generate case (|IS_CLR_INVERTED) + 1'b0: always @* if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; + 1'b1: always @* if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; + endcase endgenerate +`endif endmodule -module FDPE ((* abc_flop_q *) output reg Q, input C, CE, D, PRE); +(* abc_box_id = 9, abc_flop /*, lib_whitebox*/ *) +module FDPE ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_q *) input D, input PRE); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_PRE_INVERTED = 1'b0; initial Q <= INIT; +`ifndef _ABC generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED}) 2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; 2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; 2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; 2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; endcase endgenerate +`else + generate case (|IS_PRE_INVERTED) + 1'b0: always @* if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; + 1'b1: always @* if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; + endcase endgenerate +`endif endmodule module FDRE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, R); From 2228cef62f8550f85b203752681e2abeef1197ea Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 31 May 2019 18:11:46 -0700 Subject: [PATCH 144/213] Add flops as blackboxes --- techlibs/xilinx/abc.box | 20 ++++++++++++++++++++ techlibs/xilinx/ff_map.v | 7 +++++++ 2 files changed, 27 insertions(+) diff --git a/techlibs/xilinx/abc.box b/techlibs/xilinx/abc.box index 6e9e1faf6..a4182ed63 100644 --- a/techlibs/xilinx/abc.box +++ b/techlibs/xilinx/abc.box @@ -40,3 +40,23 @@ RAM64X1D 4 0 15 2 RAM128X1D 5 0 17 2 - - - - - - - - 314 314 314 314 314 314 292 - - 347 347 347 347 347 347 296 - - - - - - - - - - + +# Inputs: C CE D R +# Outputs: Q +FDRE 6 0 4 1 +- - - - + +# Inputs: C CE D S +# Outputs: Q +FDSE 7 0 4 1 +- - - - + +# Inputs: C CE CLR D +# Outputs: Q +FDCE 8 0 4 1 +- - 404 - + +# Inputs: C CE D PRE +# Outputs: Q +FDPE 9 0 4 1 +- - - 404 diff --git a/techlibs/xilinx/ff_map.v b/techlibs/xilinx/ff_map.v index 13beaa6ae..7c837814a 100644 --- a/techlibs/xilinx/ff_map.v +++ b/techlibs/xilinx/ff_map.v @@ -38,5 +38,12 @@ module \$_DFF_NP1_ (input D, C, R, output Q); FDPE_1 #(.INIT(|0)) _TECHMAP_REPL module \$_DFF_PN1_ (input D, C, R, output Q); FDPE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); endmodule module \$_DFF_PP1_ (input D, C, R, output Q); FDPE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); endmodule +`ifndef DEPRECATED +module FDRE_1 (output reg Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; FDRE #(.INIT(INIT), .IS_CLK_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .R(R), .Q(Q)); endmodule +module FDSE_1 (output reg Q, input C, CE, D, S); parameter [0:0] INIT = 1'b0; FDSE #(.INIT(INIT), .IS_CLK_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .S(S), .Q(Q)); endmodule +module FDCE_1 (output reg Q, input C, CE, D, CLR); parameter [0:0] INIT = 1'b0; FDCE #(.INIT(INIT), .IS_CLK_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .CLR(CLR), .Q(Q)); endmodule +module FDPE_1 (output reg Q, input C, CE, D, PRE); parameter [0:0] INIT = 1'b0; FDPE #(.INIT(INIT), .IS_CLK_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .PRE(PRE), .Q(Q)); endmodule +`endif + `endif From 9f44a7171528b90e85b2f33ef8823660fbd95609 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 3 Jun 2019 09:23:43 -0700 Subject: [PATCH 145/213] Consistent with xilinx --- techlibs/ice40/abc_hx.box | 2 +- techlibs/ice40/cells_sim.v | 2 +- techlibs/ice40/synth_ice40.cc | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box index 994f3091d..9ebdae18b 100644 --- a/techlibs/ice40/abc_hx.box +++ b/techlibs/ice40/abc_hx.box @@ -4,7 +4,7 @@ # Inputs: C D # Outputs: Q -SB_DFF 1 1 2 1 +SB_DFF 1 0 2 1 - - # Inputs: C D E diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index b5e10fb20..6897aeeb4 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -145,7 +145,7 @@ endmodule (* abc_box_id = 1, abc_flop, lib_whitebox *) module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) input D); -`ifndef ABC_MODEL +`ifndef _ABC always @(posedge C) Q <= D; `else diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 168161a90..5afa042b0 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -240,7 +240,7 @@ struct SynthIce40Pass : public ScriptPass { if (check_label("begin")) { - run("read_verilog -lib -D ABC_MODEL +/ice40/cells_sim.v"); + run("read_verilog -lib -D_ABC +/ice40/cells_sim.v"); run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); run("proc"); } @@ -334,7 +334,7 @@ struct SynthIce40Pass : public ScriptPass if (abc == "abc9") run(abc + stringf(" -dress -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)"); else - run(abc + " -lut 4", "(skip if -noabc)"); + run(abc + " -dress -lut 4", "(skip if -noabc)"); } run("clean"); if (relut || help_mode) { From 4da25c76b365b7c90a368c36def81d1122434b95 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 3 Jun 2019 09:33:42 -0700 Subject: [PATCH 146/213] Ooopsie --- techlibs/ice40/cells_map.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/ice40/cells_map.v b/techlibs/ice40/cells_map.v index 287c48b11..759549e30 100644 --- a/techlibs/ice40/cells_map.v +++ b/techlibs/ice40/cells_map.v @@ -53,7 +53,7 @@ module \$lut (A, Y); end else if (WIDTH == 4) begin localparam [15:0] INIT = {LUT[15], LUT[7], LUT[11], LUT[3], LUT[13], LUT[5], LUT[9], LUT[1], LUT[14], LUT[6], LUT[10], LUT[2], LUT[12], LUT[4], LUT[8], LUT[0]}; - SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), + SB_LUT4 #(.LUT_INIT(INIT)) _TECHMAP_REPLACE_ (.O(Y), .I0(A[3]), .I1(A[2]), .I2(A[1]), .I3(A[0])); end else begin wire _TECHMAP_FAIL_ = 1; From 257f7ff5f63635f0a754f34cf8af93ed06632b5b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 3 Jun 2019 12:30:54 -0700 Subject: [PATCH 147/213] When creating new holes cell, inherit parameters too --- backends/aiger/xaiger.cc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 90fea2db1..818caebba 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -796,8 +796,10 @@ struct XAigerWriter RTLIL::Module* box_module = module->design->module(cell->type); int box_inputs = 0, box_outputs = 0; Cell *holes_cell = nullptr; - if (box_module->get_bool_attribute("\\whitebox")) + if (box_module->get_bool_attribute("\\whitebox")) { holes_cell = holes_module->addCell(cell->name, cell->type); + holes_cell->parameters = cell->parameters; + } // NB: Assume box_module->ports are sorted alphabetically // (as RTLIL::Module::fixup_ports() would do) From a54822b1bc02773168717f9c0e221344f570ac23 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 3 Jun 2019 12:31:23 -0700 Subject: [PATCH 148/213] Skip internal modules when generating box_unique_id --- frontends/aiger/aigerparse.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 0e210c456..c951e1fbb 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -198,6 +198,7 @@ void AigerReader::parse_xaiger() dict box_lookup; for (auto m : design->modules()) { + if (m->name[0] == '$') continue; auto it = m->attributes.find("\\abc_box_id"); if (it == m->attributes.end()) continue; From 295bd8d0bf81dcb4ad07b1798e021dddcb5dfdc4 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 3 Jun 2019 12:32:20 -0700 Subject: [PATCH 149/213] Remove dupe --- passes/techmap/abc9.cc | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 01842dbf2..06a638558 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -552,7 +552,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri // Remove all AND, NOT, and ABC box instances // in preparation for stitching mapped_mod in - pool erased_boxes; + dict erased_boxes; for (auto it = module->cells_.begin(); it != module->cells_.end(); ) { RTLIL::Cell* cell = it->second; if (cell->type.in("$_AND_", "$_NOT_")) { @@ -561,7 +561,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri } RTLIL::Module* box_module = design->module(cell->type); if (box_module && box_module->attributes.count("\\abc_box_id")) { - erased_boxes.insert(it->first); + erased_boxes.insert(std::make_pair(it->first, std::move(cell->parameters))); it = module->cells_.erase(it); continue; } @@ -645,8 +645,11 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri continue; } } - else - log_assert(erased_boxes.count(c->name)); + else { + auto it = erased_boxes.find(c->name); + log_assert(it != erased_boxes.end()); + c->parameters = std::move(it->second); + } RTLIL::Cell* cell = module->addCell(remap_name(c->name), c->type); if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx; @@ -1226,9 +1229,6 @@ struct Abc9Pass : public Pass { continue; } - if (mod->attributes.count("\\abc_box_id")) - continue; - assign_map.set(mod); signal_init.clear(); From d018cd9fe3f65187b7f8a878994dfbc37308d653 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 3 Jun 2019 12:33:47 -0700 Subject: [PATCH 150/213] Assert that box_unique_id is indeed unique --- frontends/aiger/aigerparse.cc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index c951e1fbb..95335a029 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -198,11 +198,12 @@ void AigerReader::parse_xaiger() dict box_lookup; for (auto m : design->modules()) { - if (m->name[0] == '$') continue; auto it = m->attributes.find("\\abc_box_id"); if (it == m->attributes.end()) continue; - box_lookup[it->second.as_int()] = m->name; + if (m->name[0] == '$') continue; + auto r = box_lookup.insert(std::make_pair(it->second.as_int(), m->name)); + log_assert(r.second); } // Parse footer (symbol table, comments, etc.) From 00927703177d01ad27559aad827b72068b80b12a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 3 Jun 2019 12:34:55 -0700 Subject: [PATCH 151/213] Make SB_LUT4 a whitebox, SB_DFF a blackbox (for now) --- techlibs/ice40/abc_hx.box | 2 +- techlibs/ice40/abc_lp.box | 4 ++-- techlibs/ice40/abc_u.box | 4 ++-- techlibs/ice40/cells_sim.v | 6 +++--- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/techlibs/ice40/abc_hx.box b/techlibs/ice40/abc_hx.box index 9ebdae18b..a0655643d 100644 --- a/techlibs/ice40/abc_hx.box +++ b/techlibs/ice40/abc_hx.box @@ -109,5 +109,5 @@ SB_CARRY 21 1 3 1 # Inputs: I0 I1 I2 I3 # Outputs: O -SB_LUT4 22 0 4 1 +SB_LUT4 22 1 4 1 449 400 379 316 diff --git a/techlibs/ice40/abc_lp.box b/techlibs/ice40/abc_lp.box index 002b7bba4..dbc98d0c4 100644 --- a/techlibs/ice40/abc_lp.box +++ b/techlibs/ice40/abc_lp.box @@ -4,7 +4,7 @@ # Inputs: C D # Outputs: Q -SB_DFF 1 1 2 1 +SB_DFF 1 0 2 1 - - # Inputs: C D E @@ -109,5 +109,5 @@ SB_CARRY 21 1 3 1 # Inputs: I0 I1 I2 I3 # Outputs: O -SB_LUT4 22 0 4 1 +SB_LUT4 22 1 4 1 465 558 589 661 diff --git a/techlibs/ice40/abc_u.box b/techlibs/ice40/abc_u.box index cb336181c..3b5834e40 100644 --- a/techlibs/ice40/abc_u.box +++ b/techlibs/ice40/abc_u.box @@ -4,7 +4,7 @@ # Inputs: C D # Outputs: Q -SB_DFF 1 1 2 1 +SB_DFF 1 0 2 1 - - # Inputs: C D E @@ -109,5 +109,5 @@ SB_CARRY 21 1 3 1 # Inputs: I0 I1 I2 I3 # Outputs: O -SB_LUT4 22 0 4 1 +SB_LUT4 22 1 4 1 1285 1231 1205 874 diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 6897aeeb4..b9f381266 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -127,7 +127,7 @@ endmodule // SiliconBlue Logic Cells -(* abc_box_id = 22 *) +(* abc_box_id = 22, lib_whitebox *) module SB_LUT4 (output O, input I0, I1, I2, I3); parameter [15:0] LUT_INIT = 0; wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0]; @@ -136,8 +136,8 @@ module SB_LUT4 (output O, input I0, I1, I2, I3); assign O = I0 ? s1[1] : s1[0]; endmodule -(* abc_box_id = 21, lib_whitebox *) -module SB_CARRY (output CO, input I0, I1, CI); +(* abc_box_id = 21, abc_carry, lib_whitebox *) +module SB_CARRY ((* abc_carry_out *) output CO, input I0, I1, (* abc_carry_in *) input CI); assign CO = (I0 && I1) || ((I0 || I1) && CI); endmodule From ebcc85b9b86267a25e9126aa3d82ef4a0bd9f6fd Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 3 Jun 2019 12:37:02 -0700 Subject: [PATCH 152/213] Fix `ifndef --- techlibs/xilinx/cells_sim.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index cce03980d..c8450f8d1 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -246,8 +246,8 @@ module FDCE ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_CLR_INVERTED = 1'b0; initial Q <= INIT; - generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED}) `ifndef _ABC + generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED}) 2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; 2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; 2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; From c9a0bac5413dff55e141deb4098b63ca4c62e5b1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 3 Jun 2019 19:45:56 -0700 Subject: [PATCH 153/213] IS_C_INVERTED --- techlibs/xilinx/ff_map.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/techlibs/xilinx/ff_map.v b/techlibs/xilinx/ff_map.v index 7c837814a..ce465130d 100644 --- a/techlibs/xilinx/ff_map.v +++ b/techlibs/xilinx/ff_map.v @@ -39,10 +39,10 @@ module \$_DFF_PN1_ (input D, C, R, output Q); FDPE #(.INIT(|0)) _TECHMAP_REPL module \$_DFF_PP1_ (input D, C, R, output Q); FDPE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); endmodule `ifndef DEPRECATED -module FDRE_1 (output reg Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; FDRE #(.INIT(INIT), .IS_CLK_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .R(R), .Q(Q)); endmodule -module FDSE_1 (output reg Q, input C, CE, D, S); parameter [0:0] INIT = 1'b0; FDSE #(.INIT(INIT), .IS_CLK_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .S(S), .Q(Q)); endmodule -module FDCE_1 (output reg Q, input C, CE, D, CLR); parameter [0:0] INIT = 1'b0; FDCE #(.INIT(INIT), .IS_CLK_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .CLR(CLR), .Q(Q)); endmodule -module FDPE_1 (output reg Q, input C, CE, D, PRE); parameter [0:0] INIT = 1'b0; FDPE #(.INIT(INIT), .IS_CLK_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .PRE(PRE), .Q(Q)); endmodule +module FDRE_1 (output reg Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; FDRE #(.INIT(INIT), .IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .R(R), .Q(Q)); endmodule +module FDSE_1 (output reg Q, input C, CE, D, S); parameter [0:0] INIT = 1'b0; FDSE #(.INIT(INIT), .IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .S(S), .Q(Q)); endmodule +module FDCE_1 (output reg Q, input C, CE, D, CLR); parameter [0:0] INIT = 1'b0; FDCE #(.INIT(INIT), .IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .CLR(CLR), .Q(Q)); endmodule +module FDPE_1 (output reg Q, input C, CE, D, PRE); parameter [0:0] INIT = 1'b0; FDPE #(.INIT(INIT), .IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .PRE(PRE), .Q(Q)); endmodule `endif `endif From b6e59741ae6e4ec57affb9ab168a9d08cdb6d04f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 3 Jun 2019 20:21:41 -0700 Subject: [PATCH 154/213] Typo --- techlibs/xilinx/cells_sim.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index c8450f8d1..16b8b4949 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -262,7 +262,7 @@ module FDCE ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input endmodule (* abc_box_id = 9, abc_flop /*, lib_whitebox*/ *) -module FDPE ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_q *) input D, input PRE); +module FDPE ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input D, input PRE); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; From 23a73ca6241381e7272f905d1dcbf01c49ad00a8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 3 Jun 2019 23:19:22 -0700 Subject: [PATCH 155/213] Merge mistake --- techlibs/xilinx/synth_xilinx.cc | 20 ++++++-------------- 1 file changed, 6 insertions(+), 14 deletions(-) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index e316c268e..4269870d7 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -259,13 +259,6 @@ struct SynthXilinxPass : public ScriptPass run("dff2dffe"); run("opt -full"); - if (vpr && !nocarry && !help_mode) - run("techmap -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY"); - else if (abc == "abc9" && !nocarry && !help_mode) - run("techmap -map +/xilinx/arith_map.v -D _CLB_CARRY", "(skip if '-nocarry')"); - else if (!nocarry || help_mode) - run("techmap -map +/xilinx/arith_map.v", "(skip if '-nocarry')"); - if (!nosrl || help_mode) { // shregmap operates on bit-level flops, not word-level, // so break those down here @@ -274,13 +267,12 @@ struct SynthXilinxPass : public ScriptPass run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')"); } - if (!nomux || help_mode) - run("techmap -map +/xilinx/cells_map.v"); - - if (!vpr || help_mode) - run("techmap -map +/techmap.v -map +/xilinx/arith_map.v"); - else - run("techmap -map +/techmap.v +/xilinx/arith_map.v -D _EXPLICIT_CARRY"); + if (vpr && !nocarry && !help_mode) + run("techmap -map +/techmap.v -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY"); + else if (abc == "abc9" && !nocarry && !help_mode) + run("techmap -map +/techmap.v -map +/xilinx/arith_map.v -D _CLB_CARRY", "(skip if '-nocarry')"); + else if (!nocarry || help_mode) + run("techmap -map +/techmap.v -map +/xilinx/arith_map.v", "(skip if '-nocarry')"); run("opt -fast"); } From 5afa42432f71443e69d1095d17066ae173b7883a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 3 Jun 2019 23:29:45 -0700 Subject: [PATCH 156/213] Fix pmux2shiftx logic --- techlibs/xilinx/synth_xilinx.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 4269870d7..19a19d14e 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -229,7 +229,7 @@ struct SynthXilinxPass : public ScriptPass // cells for identifying variable-length shift registers, // so attempt to convert $pmux-es to the former // Also: wide multiplexer inference benefits from this too - if ((!nosrl && !nomux) || help_mode) + if (!(nosrl && nomux) || help_mode) run("pmux2shiftx", "(skip if '-nosrl' and '-nomux')"); // Run a number of peephole optimisations, including one From 09b778744dc036d54209644884e9dc9138f95771 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 3 Jun 2019 23:42:30 -0700 Subject: [PATCH 157/213] Respect -nocarry --- techlibs/xilinx/synth_xilinx.cc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 19a19d14e..8ce552780 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -270,9 +270,11 @@ struct SynthXilinxPass : public ScriptPass if (vpr && !nocarry && !help_mode) run("techmap -map +/techmap.v -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY"); else if (abc == "abc9" && !nocarry && !help_mode) - run("techmap -map +/techmap.v -map +/xilinx/arith_map.v -D _CLB_CARRY", "(skip if '-nocarry')"); + run("techmap -map +/techmap.v -map +/xilinx/arith_map.v -D _CLB_CARRY"); else if (!nocarry || help_mode) run("techmap -map +/techmap.v -map +/xilinx/arith_map.v", "(skip if '-nocarry')"); + else + run("techmap -map +/techmap.v"); run("opt -fast"); } From 9b9bd4e19f3da363eb3c90ef27ace282716d2e06 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 3 Jun 2019 23:43:23 -0700 Subject: [PATCH 158/213] Move ff_map back after ABC for shregmap --- techlibs/xilinx/synth_xilinx.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 8ce552780..f45126dc5 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -280,9 +280,7 @@ struct SynthXilinxPass : public ScriptPass } if (check_label("map_cells")) { - run("techmap -map +/techmap.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v "); - run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " - "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT"); + run("techmap -map +/techmap.v -map +/xilinx/cells_map.v"); run("clean"); } @@ -299,7 +297,9 @@ struct SynthXilinxPass : public ScriptPass // has performed any necessary retiming if (!nosrl || help_mode) run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')"); - run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v"); + run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v"); + run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " + "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT"); run("clean"); } From e260150321f3410056da64f83783b470caa89384 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 4 Jun 2019 09:51:47 -0700 Subject: [PATCH 159/213] Add mux_map.v for wide mux --- techlibs/xilinx/Makefile.inc | 1 + techlibs/xilinx/cells_map.v | 35 +++++++++------------- techlibs/xilinx/mux_map.v | 52 +++++++++++++++++++++++++++++++++ techlibs/xilinx/synth_xilinx.cc | 24 +++++++++------ 4 files changed, 82 insertions(+), 30 deletions(-) create mode 100644 techlibs/xilinx/mux_map.v diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index 296edace9..2f3945167 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -30,6 +30,7 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/mux_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc.box)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc.lut)) diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index af6414667..120d610bb 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -2,6 +2,7 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf + * 2019 Eddie Hung * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -152,7 +153,7 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o endgenerate endmodule -module \$shiftx (A, B, Y); +module \$__XILINX_MUX_ (A, B, Y); parameter A_SIGNED = 0; parameter B_SIGNED = 0; parameter A_WIDTH = 1; @@ -184,18 +185,10 @@ module \$shiftx (A, B, Y); generate genvar i, j; - // TODO: Check if this opt still necessary - if (B_SIGNED) begin - if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && _TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0) - // Optimisation to remove B_SIGNED if sign bit of B is constant-0 - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B[B_WIDTH-2:0]), .Y(Y)); - else - wire _TECHMAP_FAIL_ = 1; - end // Bit-blast - else if (Y_WIDTH > 1) begin + if (Y_WIDTH > 1) begin for (i = 0; i < Y_WIDTH; i++) - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-Y_WIDTH+1), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A(A[A_WIDTH-Y_WIDTH+i:i]), .B(B), .Y(Y[i])); + \$__XILINX_MUX_ #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-Y_WIDTH+1), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A(A[A_WIDTH-Y_WIDTH+i:i]), .B(B), .Y(Y[i])); end // If the LSB of B is constant zero (and Y_WIDTH is 1) then // we can optimise by removing every other entry from A @@ -204,24 +197,24 @@ module \$shiftx (A, B, Y); wire [(A_WIDTH+1)/2-1:0] A_i; for (i = 0; i < (A_WIDTH+1)/2; i++) assign A_i[i] = A[i*2]; - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y)); + \$__XILINX_MUX_ #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y)); end // Trim off any leading 1'bx -es in A, and resize B accordingly else if (num_leading_X_in_A > 0) begin localparam A_WIDTH_new = A_WIDTH - num_leading_X_in_A; localparam B_WIDTH_new = $clog2(A_WIDTH_new); - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH_new), .B_WIDTH(B_WIDTH_new), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A[A_WIDTH_new-1:0]), .B(B[B_WIDTH_new-1:0]), .Y(Y)); + \$__XILINX_MUX_ #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH_new), .B_WIDTH(B_WIDTH_new), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A[A_WIDTH_new-1:0]), .B(B[B_WIDTH_new-1:0]), .Y(Y)); end else if (B_WIDTH < 3 || A_WIDTH <= 4) begin - wire _TECHMAP_FAIL_ = 1; + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y)); end else if (B_WIDTH == 3) begin localparam a_width0 = 2 ** 2; localparam a_widthN = A_WIDTH - a_width0; wire T0, T1; - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[a_width0-1:0]), .B(B[2-1:0]), .Y(T0)); + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2), .Y_WIDTH(Y_WIDTH)) fpga_mux (.A(A[a_width0-1:0]), .B(B[2-1:0]), .Y(T0)); if (a_widthN > 1) - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1)); + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_mux_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1)); else assign T1 = A[A_WIDTH-1]; MUXF7 fpga_mux (.I0(T0), .I1(T1), .S(B[B_WIDTH-1]), .O(Y)); @@ -234,10 +227,10 @@ module \$shiftx (A, B, Y); wire T0, T1; for (i = 0; i < 4; i++) if (i < num_mux8) - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[i*a_width0+:a_width0]), .B(B[2-1:0]), .Y(T[i])); + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2), .Y_WIDTH(Y_WIDTH)) fpga_mux (.A(A[i*a_width0+:a_width0]), .B(B[2-1:0]), .Y(T[i])); else if (i == num_mux8 && a_widthN > 0) begin if (a_widthN > 1) - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i])); + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_mux_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i])); else assign T[i] = A[A_WIDTH-1]; end @@ -254,16 +247,16 @@ module \$shiftx (A, B, Y); wire [(2**(B_WIDTH-4))-1:0] T; for (i = 0; i < 2 ** (B_WIDTH-4); i++) if (i < num_mux16) - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]), .Y(T[i])); + \$__XILINX_MUX_ #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4), .Y_WIDTH(Y_WIDTH)) fpga_mux (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]), .Y(T[i])); else if (i == num_mux16 && a_widthN > 0) begin if (a_widthN > 1) - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i])); + \$__XILINX_MUX_ #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_mux_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i])); else assign T[i] = A[A_WIDTH-1]; end else assign T[i] = 1'bx; - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(2**(B_WIDTH-4)), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y)); + \$__XILINX_MUX_ #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(2**(B_WIDTH-4)), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) fpga_mux (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y)); end endgenerate endmodule diff --git a/techlibs/xilinx/mux_map.v b/techlibs/xilinx/mux_map.v new file mode 100644 index 000000000..2ad7f7671 --- /dev/null +++ b/techlibs/xilinx/mux_map.v @@ -0,0 +1,52 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * 2019 Eddie Hung + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +module \$shiftx (A, B, Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 1; + parameter B_WIDTH = 1; + parameter Y_WIDTH = 1; + + input [A_WIDTH-1:0] A; + input [B_WIDTH-1:0] B; + output [Y_WIDTH-1:0] Y; + + parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0; + parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0; + + generate + genvar i, j; + // TODO: Check if this opt still necessary + if (B_SIGNED) begin + if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && _TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0) + // Optimisation to remove B_SIGNED if sign bit of B is constant-0 + \$__XILINX_MUX_ #(.A_SIGNED(A_SIGNED), .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B[B_WIDTH-2:0]), .Y(Y)); + else + wire _TECHMAP_FAIL_ = 1; + end + else if (B_WIDTH < 3 || A_WIDTH <= 4) begin + wire _TECHMAP_FAIL_ = 1; + end + else begin + \$__XILINX_MUX_ #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y)); + end + endgenerate +endmodule diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index f45126dc5..360418975 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -267,15 +267,21 @@ struct SynthXilinxPass : public ScriptPass run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')"); } - if (vpr && !nocarry && !help_mode) - run("techmap -map +/techmap.v -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY"); - else if (abc == "abc9" && !nocarry && !help_mode) - run("techmap -map +/techmap.v -map +/xilinx/arith_map.v -D _CLB_CARRY"); - else if (!nocarry || help_mode) - run("techmap -map +/techmap.v -map +/xilinx/arith_map.v", "(skip if '-nocarry')"); - else - run("techmap -map +/techmap.v"); - + std::string techmap_files = " -map +/techmap.v"; + if (help_mode) + techmap_files += " [-map +/xilinx/mux_map.v]"; + else if (!nomux) + techmap_files += " -map +/xilinx/mux_map.v"; + if (help_mode) + techmap_files += " [-map +/xilinx/arith_map.v]"; + else if (!nocarry) { + techmap_files += " -map +/xilinx/arith_map.v"; + if (vpr) + techmap_files += " -D _EXPLICIT_CARRY"; + else if (abc == "abc9") + techmap_files += " -D _CLB_CARRY"; + } + run("techmap " + techmap_files); run("opt -fast"); } From 6cf092641f3e39b466f1f36617a1474f9ae36901 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 4 Jun 2019 09:56:36 -0700 Subject: [PATCH 160/213] Fix name clash --- techlibs/xilinx/cells_map.v | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 120d610bb..f3422349f 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -212,12 +212,12 @@ module \$__XILINX_MUX_ (A, B, Y); localparam a_width0 = 2 ** 2; localparam a_widthN = A_WIDTH - a_width0; wire T0, T1; - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2), .Y_WIDTH(Y_WIDTH)) fpga_mux (.A(A[a_width0-1:0]), .B(B[2-1:0]), .Y(T0)); + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux (.A(A[a_width0-1:0]), .B(B[2-1:0]), .Y(T0)); if (a_widthN > 1) - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_mux_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1)); + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1)); else assign T1 = A[A_WIDTH-1]; - MUXF7 fpga_mux (.I0(T0), .I1(T1), .S(B[B_WIDTH-1]), .O(Y)); + MUXF7 fpga_hard_mux (.I0(T0), .I1(T1), .S(B[B_WIDTH-1]), .O(Y)); end else if (B_WIDTH == 4) begin localparam a_width0 = 2 ** 2; @@ -227,18 +227,18 @@ module \$__XILINX_MUX_ (A, B, Y); wire T0, T1; for (i = 0; i < 4; i++) if (i < num_mux8) - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2), .Y_WIDTH(Y_WIDTH)) fpga_mux (.A(A[i*a_width0+:a_width0]), .B(B[2-1:0]), .Y(T[i])); + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux (.A(A[i*a_width0+:a_width0]), .B(B[2-1:0]), .Y(T[i])); else if (i == num_mux8 && a_widthN > 0) begin if (a_widthN > 1) - \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_mux_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i])); + \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i])); else assign T[i] = A[A_WIDTH-1]; end else assign T[i] = 1'bx; - MUXF7 fpga_mux_0 (.I0(T[0]), .I1(T[1]), .S(B[2]), .O(T0)); - MUXF7 fpga_mux_1 (.I0(T[2]), .I1(T[3]), .S(B[2]), .O(T1)); - MUXF8 fpga_mux_2 (.I0(T0), .I1(T1), .S(B[3]), .O(Y)); + MUXF7 fpga_hard_mux_0 (.I0(T[0]), .I1(T[1]), .S(B[2]), .O(T0)); + MUXF7 fpga_hard_mux_1 (.I0(T[2]), .I1(T[3]), .S(B[2]), .O(T1)); + MUXF8 fpga_hard_mux_2 (.I0(T0), .I1(T1), .S(B[3]), .O(Y)); end else begin localparam a_width0 = 2 ** 4; @@ -247,16 +247,16 @@ module \$__XILINX_MUX_ (A, B, Y); wire [(2**(B_WIDTH-4))-1:0] T; for (i = 0; i < 2 ** (B_WIDTH-4); i++) if (i < num_mux16) - \$__XILINX_MUX_ #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4), .Y_WIDTH(Y_WIDTH)) fpga_mux (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]), .Y(T[i])); + \$__XILINX_MUX_ #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]), .Y(T[i])); else if (i == num_mux16 && a_widthN > 0) begin if (a_widthN > 1) - \$__XILINX_MUX_ #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_mux_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i])); + \$__XILINX_MUX_ #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i])); else assign T[i] = A[A_WIDTH-1]; end else assign T[i] = 1'bx; - \$__XILINX_MUX_ #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(2**(B_WIDTH-4)), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) fpga_mux (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y)); + \$__XILINX_MUX_ #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(2**(B_WIDTH-4)), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y)); end endgenerate endmodule From f0e93f33cf089a1c1924e569700792bf198b6810 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 4 Jun 2019 11:53:51 -0700 Subject: [PATCH 161/213] Add (* abc_flop_q *) to brams_bb.v --- techlibs/xilinx/brams_bb.v | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/techlibs/xilinx/brams_bb.v b/techlibs/xilinx/brams_bb.v index a682ba4a7..f540d299d 100644 --- a/techlibs/xilinx/brams_bb.v +++ b/techlibs/xilinx/brams_bb.v @@ -19,10 +19,10 @@ module RAMB18E1 ( input [1:0] WEA, input [3:0] WEBWE, - output [15:0] DOADO, - output [15:0] DOBDO, - output [1:0] DOPADOP, - output [1:0] DOPBDOP + (* abc_flop_q *) output [15:0] DOADO, + (* abc_flop_q *) output [15:0] DOBDO, + (* abc_flop_q *) output [1:0] DOPADOP, + (* abc_flop_q *) output [1:0] DOPBDOP ); parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; @@ -143,10 +143,10 @@ module RAMB36E1 ( input [3:0] WEA, input [7:0] WEBWE, - output [31:0] DOADO, - output [31:0] DOBDO, - output [3:0] DOPADOP, - output [3:0] DOPBDOP + (* abc_flop_q *) output [31:0] DOADO, + (* abc_flop_q *) output [31:0] DOBDO, + (* abc_flop_q *) output [3:0] DOPADOP, + (* abc_flop_q *) output [3:0] DOPBDOP ); parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; From 82d41bc2f2460a06e153eac4f3968ef29ce5a63d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 4 Jun 2019 11:54:08 -0700 Subject: [PATCH 162/213] Add space between -D and _ABC --- techlibs/xilinx/synth_xilinx.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 360418975..e9eccfc0e 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -203,9 +203,9 @@ struct SynthXilinxPass : public ScriptPass { if (check_label("begin")) { if (vpr) - run("read_verilog -lib -D_ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v"); + run("read_verilog -lib -D _ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v"); else - run("read_verilog -lib -D_ABC +/xilinx/cells_sim.v"); + run("read_verilog -lib -D _ABC +/xilinx/cells_sim.v"); run("read_verilog -lib +/xilinx/cells_xtra.v"); From 1b836c93bbaa3c85d4730b0251aed64cdf207422 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 4 Jun 2019 11:56:58 -0700 Subject: [PATCH 163/213] Only toposort builtin and abc types --- backends/aiger/xaiger.cc | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 818caebba..4d45bb650 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -181,14 +181,17 @@ struct XAigerWriter for (auto cell : module->cells()) { RTLIL::Module* inst_module = module->design->module(cell->type); - bool known_type = yosys_celltypes.cell_known(cell->type); + bool builtin_type = yosys_celltypes.cell_known(cell->type); + bool abc_type = inst_module && inst_module->attributes.count("\\abc_box_id"); if (!holes_mode) { toposort.node(cell->name); - for (const auto &conn : cell->connections()) - { + for (const auto &conn : cell->connections()) { + if (!builtin_type && !abc_type) + continue; + if (!cell->type.in("$_NOT_", "$_AND_")) { - if (known_type) { + if (builtin_type) { if (conn.first.in("\\Q", "\\CTRL_OUT", "\\RD_DATA")) continue; if (cell->type == "$memrd" && conn.first == "\\DATA") @@ -199,8 +202,8 @@ struct XAigerWriter RTLIL::Wire* inst_module_port = inst_module->wire(conn.first); log_assert(inst_module_port); - if (inst_module_port->attributes.count("\\abc_flop_q")) - continue; + if (inst_module_port->port_output && inst_module_port->attributes.count("\\abc_flop_q")) + continue; } } From 7b186740d33972612cfc9f2ebe31258edb0cca2b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 4 Jun 2019 12:01:25 -0700 Subject: [PATCH 164/213] Add log_assert to ensure no loops --- backends/aiger/xaiger.cc | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 4d45bb650..bf2f9f1bc 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -334,7 +334,21 @@ struct XAigerWriter pool abc_carry_modules; - toposort.sort(); +#if 0 + toposort.analyze_loops = true; +#endif + bool no_loops = toposort.sort(); +#if 0 + unsigned i = 0; + for (auto &it : toposort.loops) { + log(" loop %d", i++); + for (auto cell : it) + log(" %s", log_id(cell)); + log("\n"); + } +#endif + log_assert(no_loops); + for (auto cell_name : toposort.sorted) { RTLIL::Cell *cell = module->cell(cell_name); RTLIL::Module* box_module = module->design->module(cell->type); From 94a5f4e60985fc1e3fea75eec85638fa29874bea Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 4 Jun 2019 14:34:36 -0700 Subject: [PATCH 165/213] Rename shregmap -tech xilinx -> xilinx_dynamic --- passes/techmap/shregmap.cc | 8 ++++---- techlibs/xilinx/synth_xilinx.cc | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index 75eedfbcc..3e2c34c0d 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -93,12 +93,12 @@ struct ShregmapTechGreenpak4 : ShregmapTech } }; -struct ShregmapTechXilinx7 : ShregmapTech +struct ShregmapTechXilinx7Dynamic : ShregmapTech { dict> sigbit_to_shiftx_offset; const ShregmapOptions &opts; - ShregmapTechXilinx7(const ShregmapOptions &opts) : opts(opts) {} + ShregmapTechXilinx7Dynamic(const ShregmapOptions &opts) : opts(opts) {} virtual void init(const Module* module, const SigMap &sigmap) override { @@ -660,11 +660,11 @@ struct ShregmapPass : public Pass { opts.zinit = true; opts.tech = new ShregmapTechGreenpak4; } - else if (tech == "xilinx") { + else if (tech == "xilinx_dynamic") { opts.init = true; opts.params = true; enpol = "any_or_none"; - opts.tech = new ShregmapTechXilinx7(opts); + opts.tech = new ShregmapTechXilinx7Dynamic(opts); } else { argidx--; break; diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index e9eccfc0e..b2559d272 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -263,8 +263,8 @@ struct SynthXilinxPass : public ScriptPass // shregmap operates on bit-level flops, not word-level, // so break those down here run("simplemap t:$dff t:$dffe", "(skip if '-nosrl')"); - // shregmap with '-tech xilinx' infers variable length shift regs - run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')"); + // shregmap to infer variable length shift regs + run("shregmap -tech xilinx_dynamic -minlen 3", "(skip if '-nosrl')"); } std::string techmap_files = " -map +/techmap.v"; From 45d1bdf83ae6d51628e917b66f1b6043c8a3baee Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 5 Jun 2019 10:21:57 -0700 Subject: [PATCH 166/213] shregmap -tech xilinx_dynamic to work -params and -enpol --- passes/techmap/shregmap.cc | 32 ++++++++++++++++++++++++++------ 1 file changed, 26 insertions(+), 6 deletions(-) diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index 3e2c34c0d..3726f04fd 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -56,7 +56,7 @@ struct ShregmapOptions struct ShregmapTechGreenpak4 : ShregmapTech { - bool analyze(vector &taps, const vector &/*qbits*/) + virtual bool analyze(vector &taps, const vector &/*qbits*/) override { if (GetSize(taps) > 2 && taps[0] == 0 && taps[2] < 17) { taps.clear(); @@ -71,7 +71,7 @@ struct ShregmapTechGreenpak4 : ShregmapTech return true; } - bool fixup(Cell *cell, dict &taps) + virtual bool fixup(Cell *cell, dict &taps) override { auto D = cell->getPort("\\D"); auto C = cell->getPort("\\C"); @@ -212,8 +212,24 @@ struct ShregmapTechXilinx7Dynamic : ShregmapTech newcell->set_src_attribute(cell->get_src_attribute()); newcell->setParam("\\DEPTH", cell->getParam("\\DEPTH")); newcell->setParam("\\INIT", cell->getParam("\\INIT")); - newcell->setParam("\\CLKPOL", cell->getParam("\\CLKPOL")); - newcell->setParam("\\ENPOL", cell->getParam("\\ENPOL")); + + if (cell->type.in("$__SHREG_DFF_N_", "$__SHREG_DFF_P_", + "$__SHREG_DFFE_NN_", "$__SHREG_DFFE_NP_", "$__SHREG_DFFE_PN_", "$__SHREG_DFFE_PP_")) { + int param_clkpol = -1; + int param_enpol = 2; + if (cell->type == "$__SHREG_DFF_N_") param_clkpol = 0; + else if (cell->type == "$__SHREG_DFF_P_") param_clkpol = 1; + else if (cell->type == "$__SHREG_DFFE_NN_") param_clkpol = 0, param_enpol = 0; + else if (cell->type == "$__SHREG_DFFE_NP_") param_clkpol = 0, param_enpol = 1; + else if (cell->type == "$__SHREG_DFFE_PN_") param_clkpol = 1, param_enpol = 0; + else if (cell->type == "$__SHREG_DFFE_PP_") param_clkpol = 1, param_enpol = 1; + else log_abort(); + + log_assert(param_clkpol >= 0); + cell->setParam("\\CLKPOL", param_clkpol); + cell->setParam("\\ENPOL", param_enpol); + } + else log_abort(); newcell->setPort("\\C", cell->getPort("\\C")); newcell->setPort("\\D", cell->getPort("\\D")); @@ -662,8 +678,12 @@ struct ShregmapPass : public Pass { } else if (tech == "xilinx_dynamic") { opts.init = true; - opts.params = true; - enpol = "any_or_none"; + opts.ffcells["$_DFF_P_"] = make_pair(IdString("\\D"), IdString("\\Q")); + opts.ffcells["$_DFF_N_"] = make_pair(IdString("\\D"), IdString("\\Q")); + opts.ffcells["$_DFFE_PP_"] = make_pair(IdString("\\D"), IdString("\\Q")); + opts.ffcells["$_DFFE_PN_"] = make_pair(IdString("\\D"), IdString("\\Q")); + opts.ffcells["$_DFFE_NP_"] = make_pair(IdString("\\D"), IdString("\\Q")); + opts.ffcells["$_DFFE_NN_"] = make_pair(IdString("\\D"), IdString("\\Q")); opts.tech = new ShregmapTechXilinx7Dynamic(opts); } else { argidx--; From e1e37db86073e545269ff440da77f57135e8b155 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 5 Jun 2019 11:08:08 -0700 Subject: [PATCH 167/213] Refactor to ShregmapTechXilinx7Static --- passes/techmap/shregmap.cc | 132 ++++++++++++++++++++++++------------- 1 file changed, 86 insertions(+), 46 deletions(-) diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index 3726f04fd..add4e9e2f 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -29,7 +29,7 @@ struct ShregmapTech virtual void init(const Module * /*module*/, const SigMap &/*sigmap*/) {} virtual void non_chain_user(const SigBit &/*bit*/, const Cell* /*cell*/, IdString /*port*/) {} virtual bool analyze(vector &taps, const vector &qbits) = 0; - virtual bool fixup(Cell *cell, dict &taps) = 0; + virtual RTLIL::Cell* fixup(Cell *cell, dict &taps) = 0; }; struct ShregmapOptions @@ -71,7 +71,7 @@ struct ShregmapTechGreenpak4 : ShregmapTech return true; } - virtual bool fixup(Cell *cell, dict &taps) override + virtual RTLIL::Cell* fixup(Cell *cell, dict &taps) override { auto D = cell->getPort("\\D"); auto C = cell->getPort("\\C"); @@ -89,16 +89,84 @@ struct ShregmapTechGreenpak4 : ShregmapTech } cell->setParam("\\OUTA_INVERT", 0); - return false; + return newcell; } }; -struct ShregmapTechXilinx7Dynamic : ShregmapTech +struct ShregmapTechXilinx7Static : ShregmapTech { - dict> sigbit_to_shiftx_offset; const ShregmapOptions &opts; - ShregmapTechXilinx7Dynamic(const ShregmapOptions &opts) : opts(opts) {} + ShregmapTechXilinx7Static(const ShregmapOptions &opts) : opts(opts) {} + + virtual bool analyze(vector &taps, const vector &/*qbits*/) override + { + if (GetSize(taps) == 1) + return taps[0] >= opts.minlen-1; + + if (taps.back() < opts.minlen-1) + return false; + + return true; + } + + virtual RTLIL::Cell* fixup(Cell *cell, dict &/*taps*/) override + { + auto newcell = cell->module->addCell(NEW_ID, "$__SHREG_"); + newcell->set_src_attribute(cell->get_src_attribute()); + newcell->setParam("\\DEPTH", cell->getParam("\\DEPTH")); + newcell->setParam("\\INIT", cell->getParam("\\INIT")); + + if (cell->type.in("$__SHREG_DFF_N_", "$__SHREG_DFF_P_", + "$__SHREG_DFFE_NN_", "$__SHREG_DFFE_NP_", "$__SHREG_DFFE_PN_", "$__SHREG_DFFE_PP_")) { + int param_clkpol = -1; + int param_enpol = 2; + if (cell->type == "$__SHREG_DFF_N_") param_clkpol = 0; + else if (cell->type == "$__SHREG_DFF_P_") param_clkpol = 1; + else if (cell->type == "$__SHREG_DFFE_NN_") param_clkpol = 0, param_enpol = 0; + else if (cell->type == "$__SHREG_DFFE_NP_") param_clkpol = 0, param_enpol = 1; + else if (cell->type == "$__SHREG_DFFE_PN_") param_clkpol = 1, param_enpol = 0; + else if (cell->type == "$__SHREG_DFFE_PP_") param_clkpol = 1, param_enpol = 1; + else log_abort(); + + log_assert(param_clkpol >= 0); + newcell->setParam("\\CLKPOL", param_clkpol); + newcell->setParam("\\ENPOL", param_enpol); + + if (cell->hasPort("\\E")) + newcell->setPort("\\E", cell->getPort("\\E")); + } + else if (cell->type.in("$__SHREG_FDRE_", "$__SHREG_FDSE_", "$__SHREG_FDCE_", "$__SHREG_FDPE_")) { + if (cell->getParam("\\IS_C_INVERTED").as_bool()) + newcell->setParam("\\CLKPOL", 0); + else + newcell->setParam("\\CLKPOL", 1); + newcell->setParam("\\ENPOL", 1); + + newcell->setPort("\\E", cell->getPort("\\CE")); + } + else if (cell->type.in("$__SHREG_FDRE_1_", "$__SHREG_FDSE_1_", "$__SHREG_FDCE_1_", "$__SHREG_FDPE_1_")) { + newcell->setParam("\\CLKPOL", 0); + + newcell->setPort("\\E", cell->getPort("\\CE")); + } + else log_abort(); + + newcell->setParam("\\ENPOL", 1); + + newcell->setPort("\\C", cell->getPort("\\C")); + newcell->setPort("\\D", cell->getPort("\\D")); + newcell->setPort("\\Q", cell->getPort("\\Q")); + + return newcell; + } +}; + +struct ShregmapTechXilinx7Dynamic : ShregmapTechXilinx7Static +{ + dict> sigbit_to_shiftx_offset; + + ShregmapTechXilinx7Dynamic(const ShregmapOptions &opts) : ShregmapTechXilinx7Static(opts) {} virtual void init(const Module* module, const SigMap &sigmap) override { @@ -200,7 +268,7 @@ struct ShregmapTechXilinx7Dynamic : ShregmapTech return true; } - virtual bool fixup(Cell *cell, dict &taps) override + virtual RTLIL::Cell* fixup(Cell *cell, dict &taps) override { const auto &tap = *taps.begin(); auto bit = tap.second; @@ -208,52 +276,24 @@ struct ShregmapTechXilinx7Dynamic : ShregmapTech auto it = sigbit_to_shiftx_offset.find(bit); log_assert(it != sigbit_to_shiftx_offset.end()); - auto newcell = cell->module->addCell(NEW_ID, "$__XILINX_SHREG_"); - newcell->set_src_attribute(cell->get_src_attribute()); - newcell->setParam("\\DEPTH", cell->getParam("\\DEPTH")); - newcell->setParam("\\INIT", cell->getParam("\\INIT")); - - if (cell->type.in("$__SHREG_DFF_N_", "$__SHREG_DFF_P_", - "$__SHREG_DFFE_NN_", "$__SHREG_DFFE_NP_", "$__SHREG_DFFE_PN_", "$__SHREG_DFFE_PP_")) { - int param_clkpol = -1; - int param_enpol = 2; - if (cell->type == "$__SHREG_DFF_N_") param_clkpol = 0; - else if (cell->type == "$__SHREG_DFF_P_") param_clkpol = 1; - else if (cell->type == "$__SHREG_DFFE_NN_") param_clkpol = 0, param_enpol = 0; - else if (cell->type == "$__SHREG_DFFE_NP_") param_clkpol = 0, param_enpol = 1; - else if (cell->type == "$__SHREG_DFFE_PN_") param_clkpol = 1, param_enpol = 0; - else if (cell->type == "$__SHREG_DFFE_PP_") param_clkpol = 1, param_enpol = 1; - else log_abort(); - - log_assert(param_clkpol >= 0); - cell->setParam("\\CLKPOL", param_clkpol); - cell->setParam("\\ENPOL", param_enpol); - } - else log_abort(); - - newcell->setPort("\\C", cell->getPort("\\C")); - newcell->setPort("\\D", cell->getPort("\\D")); - if (cell->hasPort("\\E")) - newcell->setPort("\\E", cell->getPort("\\E")); + RTLIL::Cell* newcell = ShregmapTechXilinx7Static::fixup(cell, taps); + log_assert(newcell); + log_assert(newcell->type == "$__SHREG_"); + newcell->type = "$__XILINX_SHREG_"; Cell* shiftx = std::get<0>(it->second); - RTLIL::SigSpec l_wire, q_wire; - if (shiftx->type == "$shiftx") { + RTLIL::SigSpec l_wire; + if (shiftx->type == "$shiftx") l_wire = shiftx->getPort("\\B"); - q_wire = shiftx->getPort("\\Y"); - shiftx->setPort("\\Y", cell->module->addWire(NEW_ID)); - } - else if (shiftx->type == "$mux") { + else if (shiftx->type == "$mux") l_wire = shiftx->getPort("\\S"); - q_wire = shiftx->getPort("\\Y"); - shiftx->setPort("\\Y", cell->module->addWire(NEW_ID)); - } else log_abort(); - newcell->setPort("\\Q", q_wire); newcell->setPort("\\L", l_wire); + newcell->setPort("\\Q", shiftx->getPort("\\Y")); + shiftx->setPort("\\Y", cell->module->addWire(NEW_ID)); - return false; + return newcell; } }; @@ -509,7 +549,7 @@ struct ShregmapWorker first_cell->setPort(q_port, last_cell->getPort(q_port)); first_cell->setParam("\\DEPTH", depth); - if (opts.tech != nullptr && !opts.tech->fixup(first_cell, taps_dict)) + if (opts.tech != nullptr && opts.tech->fixup(first_cell, taps_dict)) remove_cells.insert(first_cell); for (int i = 1; i < depth; i++) From dfe9d95579ab98d7518d40e427af858243de4eb3 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 5 Jun 2019 11:14:14 -0700 Subject: [PATCH 168/213] Add -tech xilinx_static --- passes/techmap/shregmap.cc | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index add4e9e2f..ef285160f 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -716,7 +716,7 @@ struct ShregmapPass : public Pass { opts.zinit = true; opts.tech = new ShregmapTechGreenpak4; } - else if (tech == "xilinx_dynamic") { + else if (tech == "xilinx_static" || tech == "xilinx_dynamic") { opts.init = true; opts.ffcells["$_DFF_P_"] = make_pair(IdString("\\D"), IdString("\\Q")); opts.ffcells["$_DFF_N_"] = make_pair(IdString("\\D"), IdString("\\Q")); @@ -724,7 +724,18 @@ struct ShregmapPass : public Pass { opts.ffcells["$_DFFE_PN_"] = make_pair(IdString("\\D"), IdString("\\Q")); opts.ffcells["$_DFFE_NP_"] = make_pair(IdString("\\D"), IdString("\\Q")); opts.ffcells["$_DFFE_NN_"] = make_pair(IdString("\\D"), IdString("\\Q")); - opts.tech = new ShregmapTechXilinx7Dynamic(opts); + opts.ffcells["FDRE"] = make_pair(IdString("\\D"), IdString("\\Q")); + opts.ffcells["FDRE_1"] = make_pair(IdString("\\D"), IdString("\\Q")); + opts.ffcells["FDSE"] = make_pair(IdString("\\D"), IdString("\\Q")); + opts.ffcells["FDSE_1"] = make_pair(IdString("\\D"), IdString("\\Q")); + opts.ffcells["FDCE"] = make_pair(IdString("\\D"), IdString("\\Q")); + opts.ffcells["FDCE_1"] = make_pair(IdString("\\D"), IdString("\\Q")); + opts.ffcells["FDPE"] = make_pair(IdString("\\D"), IdString("\\Q")); + opts.ffcells["FDPE_1"] = make_pair(IdString("\\D"), IdString("\\Q")); + if (tech == "xilinx_static") + opts.tech = new ShregmapTechXilinx7Dynamic(opts); + else if (tech == "xilinx_dynamic") + opts.tech = new ShregmapTechXilinx7Dynamic(opts); } else { argidx--; break; From e473e7456545d702c011ee7872956f94a8522865 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 5 Jun 2019 11:53:06 -0700 Subject: [PATCH 169/213] Revert "Move ff_map back after ABC for shregmap" This reverts commit 9b9bd4e19f3da363eb3c90ef27ace282716d2e06. --- techlibs/xilinx/synth_xilinx.cc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index b2559d272..e825a032c 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -286,7 +286,9 @@ struct SynthXilinxPass : public ScriptPass } if (check_label("map_cells")) { - run("techmap -map +/techmap.v -map +/xilinx/cells_map.v"); + run("techmap -map +/techmap.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v "); + run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " + "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT"); run("clean"); } @@ -303,9 +305,7 @@ struct SynthXilinxPass : public ScriptPass // has performed any necessary retiming if (!nosrl || help_mode) run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')"); - run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v"); - run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " - "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT"); + run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v"); run("clean"); } From 2c18d530ea69094e7ed46dcf781d8f2517d4c61e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 5 Jun 2019 12:28:26 -0700 Subject: [PATCH 170/213] Call shregmap -tech xilinx_static --- techlibs/xilinx/synth_xilinx.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index e825a032c..7686f2cbc 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -304,7 +304,7 @@ struct SynthXilinxPass : public ScriptPass // This shregmap call infers fixed length shift registers after abc // has performed any necessary retiming if (!nosrl || help_mode) - run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')"); + run("shregmap -tech xilinx_static -minlen 3", "(skip if '-nosrl')"); run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v"); run("clean"); } From 67f744d428b5385fbddc859c8e02f3e1ccfc17eb Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 5 Jun 2019 12:28:46 -0700 Subject: [PATCH 171/213] Cleanup --- techlibs/xilinx/cells_map.v | 10 ---------- techlibs/xilinx/ff_map.v | 7 ------- 2 files changed, 17 deletions(-) diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index f3422349f..4acf04744 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -18,16 +18,6 @@ * */ -// Convert negative-polarity reset to positive-polarity -(* techmap_celltype = "$_DFF_NN0_" *) -module _90_dff_nn0_to_np0 (input D, C, R, output Q); \$_DFF_NP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule -(* techmap_celltype = "$_DFF_PN0_" *) -module _90_dff_pn0_to_pp0 (input D, C, R, output Q); \$_DFF_PP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule -(* techmap_celltype = "$_DFF_NN1_" *) -module _90_dff_nn1_to_np1 (input D, C, R, output Q); \$_DFF_NP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule -(* techmap_celltype = "$_DFF_PN1_" *) -module _90_dff_pn1_to_pp1 (input D, C, R, output Q); \$_DFF_PP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule - module \$__SHREG_ (input C, input D, input E, output Q); parameter DEPTH = 0; parameter [DEPTH-1:0] INIT = 0; diff --git a/techlibs/xilinx/ff_map.v b/techlibs/xilinx/ff_map.v index ce465130d..13beaa6ae 100644 --- a/techlibs/xilinx/ff_map.v +++ b/techlibs/xilinx/ff_map.v @@ -38,12 +38,5 @@ module \$_DFF_NP1_ (input D, C, R, output Q); FDPE_1 #(.INIT(|0)) _TECHMAP_REPL module \$_DFF_PN1_ (input D, C, R, output Q); FDPE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); endmodule module \$_DFF_PP1_ (input D, C, R, output Q); FDPE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); endmodule -`ifndef DEPRECATED -module FDRE_1 (output reg Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; FDRE #(.INIT(INIT), .IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .R(R), .Q(Q)); endmodule -module FDSE_1 (output reg Q, input C, CE, D, S); parameter [0:0] INIT = 1'b0; FDSE #(.INIT(INIT), .IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .S(S), .Q(Q)); endmodule -module FDCE_1 (output reg Q, input C, CE, D, CLR); parameter [0:0] INIT = 1'b0; FDCE #(.INIT(INIT), .IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .CLR(CLR), .Q(Q)); endmodule -module FDPE_1 (output reg Q, input C, CE, D, PRE); parameter [0:0] INIT = 1'b0; FDPE #(.INIT(INIT), .IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.C(C), .CE(CE), .D(D), .PRE(PRE), .Q(Q)); endmodule -`endif - `endif From 6ed15b7890091d358b7715413a844a01e9b2adf6 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 5 Jun 2019 12:33:40 -0700 Subject: [PATCH 172/213] Update abc attributes on FD*E_1 --- techlibs/xilinx/cells_sim.v | 32 ++++++++++++++++++++++++++------ 1 file changed, 26 insertions(+), 6 deletions(-) diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 16b8b4949..e00992bb7 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -283,28 +283,48 @@ module FDPE ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input `endif endmodule -module FDRE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, R); +(* abc_box_id = 6, abc_flop /*, lib_whitebox */ *) +module FDRE_1 ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input D, input R); parameter [0:0] INIT = 1'b0; initial Q <= INIT; - always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D; +`ifndef _ABC + always @(negedge C) if (R) Q <= 1'b0; else if (CE) Q <= D; +`else + always @* if (R) Q <= 1'b0; else if (CE) Q <= D; +`endif endmodule -module FDSE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, S); +(* abc_box_id = 7, abc_flop /*, lib_whitebox */ *) +module FDSE_1 ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input D, input S); parameter [0:0] INIT = 1'b1; initial Q <= INIT; - always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D; +`ifndef _ABC + always @(negedge C) if (S) Q <= 1'b1; else if (CE) Q <= D; +`else + always @* if (S) Q <= 1'b1; else if (CE) Q <= D; + `endif endmodule -module FDCE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, CLR); +(* abc_box_id = 8, abc_flop /*, lib_whitebox */ *) +module FDCE_1 ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input D, input CLR); parameter [0:0] INIT = 1'b0; initial Q <= INIT; +`ifndef _ABC always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D; +`else + always @* if (CLR) Q <= 1'b0; else if (CE) Q <= D; +`endif endmodule -module FDPE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, PRE); +(* abc_box_id = 9, abc_flop /*, lib_whitebox */ *) +module FDPE_1 ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input D, input PRE); parameter [0:0] INIT = 1'b1; initial Q <= INIT; +`ifndef _ABC always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; +`else + always @* if (PRE) Q <= 1'b1; else if (CE) Q <= D; +`endif endmodule (* abc_box_id = 4 /*, lib_whitebox*/ *) From 72eda94a66c8c4938a713c9ae49d560e6b33574f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 5 Jun 2019 12:33:55 -0700 Subject: [PATCH 173/213] Continue support for ShregmapTechXilinx7Static --- passes/techmap/shregmap.cc | 111 +++++++++++++++++++++++++++---------- 1 file changed, 81 insertions(+), 30 deletions(-) diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index ef285160f..325db081b 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -28,8 +28,9 @@ struct ShregmapTech virtual ~ShregmapTech() { } virtual void init(const Module * /*module*/, const SigMap &/*sigmap*/) {} virtual void non_chain_user(const SigBit &/*bit*/, const Cell* /*cell*/, IdString /*port*/) {} + virtual bool analyze_first(const Cell* /*first_cell*/, const SigMap &/*sigmap*/) { return true; } virtual bool analyze(vector &taps, const vector &qbits) = 0; - virtual RTLIL::Cell* fixup(Cell *cell, dict &taps) = 0; + virtual Cell* fixup(Cell *cell, dict &taps) = 0; }; struct ShregmapOptions @@ -71,7 +72,7 @@ struct ShregmapTechGreenpak4 : ShregmapTech return true; } - virtual RTLIL::Cell* fixup(Cell *cell, dict &taps) override + virtual Cell* fixup(Cell *cell, dict &taps) override { auto D = cell->getPort("\\D"); auto C = cell->getPort("\\C"); @@ -99,18 +100,61 @@ struct ShregmapTechXilinx7Static : ShregmapTech ShregmapTechXilinx7Static(const ShregmapOptions &opts) : opts(opts) {} - virtual bool analyze(vector &taps, const vector &/*qbits*/) override + virtual bool analyze_first(const Cell* first_cell, const SigMap &sigmap) override { - if (GetSize(taps) == 1) - return taps[0] >= opts.minlen-1; - - if (taps.back() < opts.minlen-1) - return false; - + if (first_cell->type.in("\\FDRE", "\\FDRE_1")) { + bool is_R_inverted = false; + if (first_cell->hasParam("\\IS_R_INVERTED")) + is_R_inverted = first_cell->getParam("\\IS_R_INVERTED").as_bool(); + SigBit R = sigmap(first_cell->getPort("\\R")); + if (R != RTLIL::S0 && R != RTLIL::S1) + return false; + if ((!is_R_inverted && R != RTLIL::S0) || (is_R_inverted && R != RTLIL::S1)) + return false; + return true; + } + if (first_cell->type.in("\\FDSE", "\\FDSE_1")) { + bool is_S_inverted = false; + if (first_cell->hasParam("\\IS_S_INVERTED")) + is_S_inverted = first_cell->getParam("\\IS_S_INVERTED").as_bool(); + SigBit S = sigmap(first_cell->getPort("\\S")); + if (S != RTLIL::S0 && S != RTLIL::S1) + return false; + if ((!is_S_inverted && S != RTLIL::S0) || (is_S_inverted && S != RTLIL::S1)) + return false; + return true; + } + if (first_cell->type.in("\\FDCE", "\\FDCE_1")) { + bool is_CLR_inverted = false; + if (first_cell->hasParam("\\IS_CLR_INVERTED")) + is_CLR_inverted = first_cell->getParam("\\IS_CLR_INVERTED").as_bool(); + SigBit CLR = sigmap(first_cell->getPort("\\CLR")); + if (CLR != RTLIL::S0 && CLR != RTLIL::S1) + return false; + if ((!is_CLR_inverted && CLR != RTLIL::S0) || (is_CLR_inverted && CLR != RTLIL::S1)) + return false; + return true; + } + if (first_cell->type.in("\\FDPE", "\\FDPE_1")) { + bool is_PRE_inverted = false; + if (first_cell->hasParam("\\IS_PRE_INVERTED")) + is_PRE_inverted = first_cell->getParam("\\IS_PRE_INVERTED").as_bool(); + SigBit PRE = sigmap(first_cell->getPort("\\PRE")); + if (PRE != RTLIL::S0 && PRE != RTLIL::S1) + return false; + if ((!is_PRE_inverted && PRE != RTLIL::S0) || (is_PRE_inverted && PRE != RTLIL::S1)) + return false; + return true; + } return true; } - virtual RTLIL::Cell* fixup(Cell *cell, dict &/*taps*/) override + virtual bool analyze(vector &taps, const vector &/*qbits*/) override + { + return GetSize(taps) == 1 && taps[0] >= opts.minlen-1; + } + + virtual Cell* fixup(Cell *cell, dict &/*taps*/) override { auto newcell = cell->module->addCell(NEW_ID, "$__SHREG_"); newcell->set_src_attribute(cell->get_src_attribute()); @@ -136,16 +180,17 @@ struct ShregmapTechXilinx7Static : ShregmapTech if (cell->hasPort("\\E")) newcell->setPort("\\E", cell->getPort("\\E")); } - else if (cell->type.in("$__SHREG_FDRE_", "$__SHREG_FDSE_", "$__SHREG_FDCE_", "$__SHREG_FDPE_")) { - if (cell->getParam("\\IS_C_INVERTED").as_bool()) - newcell->setParam("\\CLKPOL", 0); - else - newcell->setParam("\\CLKPOL", 1); + else if (cell->type.in("$__SHREG_FDRE", "$__SHREG_FDRE_1","$__SHREG_FDSE", "$__SHREG_FDSE_1", + "$__SHREG_FDCE", "$__SHREG_FDCE_1", "$__SHREG_FDPE", "$__SHREG_FDPE_1")) { + int param_clkpol = 1; + if (cell->hasParam("\\IS_C_INVERTED") && cell->getParam("\\IS_C_INVERTED").as_bool()) + param_clkpol = 0; + newcell->setParam("\\CLKPOL", param_clkpol); newcell->setParam("\\ENPOL", 1); newcell->setPort("\\E", cell->getPort("\\CE")); } - else if (cell->type.in("$__SHREG_FDRE_1_", "$__SHREG_FDSE_1_", "$__SHREG_FDCE_1_", "$__SHREG_FDPE_1_")) { + else if (cell->type.in("$__SHREG_FDRE_1", "$__SHREG_FDSE_1", "$__SHREG_FDCE_1", "$__SHREG_FDPE_1")) { newcell->setParam("\\CLKPOL", 0); newcell->setPort("\\E", cell->getPort("\\CE")); @@ -215,13 +260,14 @@ struct ShregmapTechXilinx7Dynamic : ShregmapTechXilinx7Static Cell *shiftx = nullptr; int group = 0; for (int i = 0; i < GetSize(taps); ++i) { + // Check taps are sequential + if (i != taps[i]) + return false; + auto it = sigbit_to_shiftx_offset.find(qbits[i]); if (it == sigbit_to_shiftx_offset.end()) return false; - // Check taps are sequential - if (i != taps[i]) - return false; // Check taps are not connected to a shift register, // or sequential to the same shift register if (i == 0) { @@ -268,7 +314,7 @@ struct ShregmapTechXilinx7Dynamic : ShregmapTechXilinx7Static return true; } - virtual RTLIL::Cell* fixup(Cell *cell, dict &taps) override + virtual Cell* fixup(Cell *cell, dict &taps) override { const auto &tap = *taps.begin(); auto bit = tap.second; @@ -276,7 +322,7 @@ struct ShregmapTechXilinx7Dynamic : ShregmapTechXilinx7Static auto it = sigbit_to_shiftx_offset.find(bit); log_assert(it != sigbit_to_shiftx_offset.end()); - RTLIL::Cell* newcell = ShregmapTechXilinx7Static::fixup(cell, taps); + Cell* newcell = ShregmapTechXilinx7Static::fixup(cell, taps); log_assert(newcell); log_assert(newcell->type == "$__SHREG_"); newcell->type = "$__XILINX_SHREG_"; @@ -451,6 +497,11 @@ struct ShregmapWorker if (opts.tech) { + if (!opts.tech->analyze_first(first_cell, sigmap)) { + cursor += depth; + continue; + } + vector qbits; vector taps; @@ -724,16 +775,16 @@ struct ShregmapPass : public Pass { opts.ffcells["$_DFFE_PN_"] = make_pair(IdString("\\D"), IdString("\\Q")); opts.ffcells["$_DFFE_NP_"] = make_pair(IdString("\\D"), IdString("\\Q")); opts.ffcells["$_DFFE_NN_"] = make_pair(IdString("\\D"), IdString("\\Q")); - opts.ffcells["FDRE"] = make_pair(IdString("\\D"), IdString("\\Q")); - opts.ffcells["FDRE_1"] = make_pair(IdString("\\D"), IdString("\\Q")); - opts.ffcells["FDSE"] = make_pair(IdString("\\D"), IdString("\\Q")); - opts.ffcells["FDSE_1"] = make_pair(IdString("\\D"), IdString("\\Q")); - opts.ffcells["FDCE"] = make_pair(IdString("\\D"), IdString("\\Q")); - opts.ffcells["FDCE_1"] = make_pair(IdString("\\D"), IdString("\\Q")); - opts.ffcells["FDPE"] = make_pair(IdString("\\D"), IdString("\\Q")); - opts.ffcells["FDPE_1"] = make_pair(IdString("\\D"), IdString("\\Q")); + opts.ffcells["\\FDRE"] = make_pair(IdString("\\D"), IdString("\\Q")); + opts.ffcells["\\FDRE_1"] = make_pair(IdString("\\D"), IdString("\\Q")); + opts.ffcells["\\FDSE"] = make_pair(IdString("\\D"), IdString("\\Q")); + opts.ffcells["\\FDSE_1"] = make_pair(IdString("\\D"), IdString("\\Q")); + opts.ffcells["\\FDCE"] = make_pair(IdString("\\D"), IdString("\\Q")); + opts.ffcells["\\FDCE_1"] = make_pair(IdString("\\D"), IdString("\\Q")); + opts.ffcells["\\FDPE"] = make_pair(IdString("\\D"), IdString("\\Q")); + opts.ffcells["\\FDPE_1"] = make_pair(IdString("\\D"), IdString("\\Q")); if (tech == "xilinx_static") - opts.tech = new ShregmapTechXilinx7Dynamic(opts); + opts.tech = new ShregmapTechXilinx7Static(opts); else if (tech == "xilinx_dynamic") opts.tech = new ShregmapTechXilinx7Dynamic(opts); } else { From 935df3569b4677ac38041ff01a2f67185681f4e3 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 5 Jun 2019 12:55:59 -0700 Subject: [PATCH 174/213] shregmap -tech xilinx_static to handle INIT --- passes/techmap/shregmap.cc | 54 ++++++++++++++++++++++---------------- 1 file changed, 32 insertions(+), 22 deletions(-) diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index 325db081b..3868bbb89 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -30,7 +30,7 @@ struct ShregmapTech virtual void non_chain_user(const SigBit &/*bit*/, const Cell* /*cell*/, IdString /*port*/) {} virtual bool analyze_first(const Cell* /*first_cell*/, const SigMap &/*sigmap*/) { return true; } virtual bool analyze(vector &taps, const vector &qbits) = 0; - virtual Cell* fixup(Cell *cell, dict &taps) = 0; + virtual Cell* fixup(Cell *cell, const vector &taps, const vector &qbits) = 0; }; struct ShregmapOptions @@ -72,7 +72,7 @@ struct ShregmapTechGreenpak4 : ShregmapTech return true; } - virtual Cell* fixup(Cell *cell, dict &taps) override + virtual Cell* fixup(Cell *cell, const vector &taps, const vector &qbits) override { auto D = cell->getPort("\\D"); auto C = cell->getPort("\\C"); @@ -84,8 +84,8 @@ struct ShregmapTechGreenpak4 : ShregmapTech int i = 0; for (auto tap : taps) { - newcell->setPort(i ? "\\OUTB" : "\\OUTA", tap.second); - newcell->setParam(i ? "\\OUTB_TAP" : "\\OUTA_TAP", tap.first + 1); + newcell->setPort(i ? "\\OUTB" : "\\OUTA", qbits[tap]); + newcell->setParam(i ? "\\OUTB_TAP" : "\\OUTA_TAP", tap + 1); i++; } @@ -96,8 +96,21 @@ struct ShregmapTechGreenpak4 : ShregmapTech struct ShregmapTechXilinx7Static : ShregmapTech { + dict sigbit_to_cell; const ShregmapOptions &opts; + virtual void init(const Module* module, const SigMap &sigmap) override + { + for (const auto &i : module->cells_) { + auto cell = i.second; + if (!cell->type.in("\\FDRE", "\\FDRE_1","\\FDSE", "\\FDSE_1", + "\\FDCE", "\\FDCE_1", "\\FDPE", "\\FDPE_1")) + continue; + + sigbit_to_cell[sigmap(cell->getPort("\\Q"))] = cell; + } + } + ShregmapTechXilinx7Static(const ShregmapOptions &opts) : opts(opts) {} virtual bool analyze_first(const Cell* first_cell, const SigMap &sigmap) override @@ -154,15 +167,14 @@ struct ShregmapTechXilinx7Static : ShregmapTech return GetSize(taps) == 1 && taps[0] >= opts.minlen-1; } - virtual Cell* fixup(Cell *cell, dict &/*taps*/) override + virtual Cell* fixup(Cell *cell, const vector &/*taps*/, const vector &qbits) override { auto newcell = cell->module->addCell(NEW_ID, "$__SHREG_"); newcell->set_src_attribute(cell->get_src_attribute()); newcell->setParam("\\DEPTH", cell->getParam("\\DEPTH")); - newcell->setParam("\\INIT", cell->getParam("\\INIT")); if (cell->type.in("$__SHREG_DFF_N_", "$__SHREG_DFF_P_", - "$__SHREG_DFFE_NN_", "$__SHREG_DFFE_NP_", "$__SHREG_DFFE_PN_", "$__SHREG_DFFE_PP_")) { + "$__SHREG_DFFE_NN_", "$__SHREG_DFFE_NP_", "$__SHREG_DFFE_PN_", "$__SHREG_DFFE_PP_")) { int param_clkpol = -1; int param_enpol = 2; if (cell->type == "$__SHREG_DFF_N_") param_clkpol = 0; @@ -176,6 +188,7 @@ struct ShregmapTechXilinx7Static : ShregmapTech log_assert(param_clkpol >= 0); newcell->setParam("\\CLKPOL", param_clkpol); newcell->setParam("\\ENPOL", param_enpol); + newcell->setParam("\\INIT", cell->getParam("\\INIT")); if (cell->hasPort("\\E")) newcell->setPort("\\E", cell->getPort("\\E")); @@ -187,11 +200,12 @@ struct ShregmapTechXilinx7Static : ShregmapTech param_clkpol = 0; newcell->setParam("\\CLKPOL", param_clkpol); newcell->setParam("\\ENPOL", 1); - - newcell->setPort("\\E", cell->getPort("\\CE")); - } - else if (cell->type.in("$__SHREG_FDRE_1", "$__SHREG_FDSE_1", "$__SHREG_FDCE_1", "$__SHREG_FDPE_1")) { - newcell->setParam("\\CLKPOL", 0); + log_assert(cell->getParam("\\INIT").is_fully_undef()); + SigSpec INIT; + for (auto q : qbits) { + Cell* reg = sigbit_to_cell.at(q); + INIT.append(SigBit(reg->getParam("\\INIT").as_bool())); + } newcell->setPort("\\E", cell->getPort("\\CE")); } @@ -314,15 +328,14 @@ struct ShregmapTechXilinx7Dynamic : ShregmapTechXilinx7Static return true; } - virtual Cell* fixup(Cell *cell, dict &taps) override + virtual Cell* fixup(Cell *cell, const vector &taps, const vector &qbits) override { - const auto &tap = *taps.begin(); - auto bit = tap.second; + auto bit = qbits[taps.front()]; auto it = sigbit_to_shiftx_offset.find(bit); log_assert(it != sigbit_to_shiftx_offset.end()); - Cell* newcell = ShregmapTechXilinx7Static::fixup(cell, taps); + Cell* newcell = ShregmapTechXilinx7Static::fixup(cell, taps, qbits); log_assert(newcell); log_assert(newcell->type == "$__SHREG_"); newcell->type = "$__XILINX_SHREG_"; @@ -493,7 +506,8 @@ struct ShregmapWorker Cell *first_cell = chain[cursor]; IdString q_port = opts.ffcells.at(first_cell->type).second; - dict taps_dict; + vector qbits; + vector taps; if (opts.tech) { @@ -502,9 +516,6 @@ struct ShregmapWorker continue; } - vector qbits; - vector taps; - for (int i = 0; i < depth; i++) { Cell *cell = chain[cursor+i]; @@ -529,7 +540,6 @@ struct ShregmapWorker depth = 0; for (auto tap : taps) { - taps_dict[tap] = qbits.at(tap); log_assert(depth < tap+1); depth = tap+1; } @@ -600,7 +610,7 @@ struct ShregmapWorker first_cell->setPort(q_port, last_cell->getPort(q_port)); first_cell->setParam("\\DEPTH", depth); - if (opts.tech != nullptr && opts.tech->fixup(first_cell, taps_dict)) + if (opts.tech != nullptr && opts.tech->fixup(first_cell, taps, qbits)) remove_cells.insert(first_cell); for (int i = 1; i < depth; i++) From 7bd1c664a6f0d9a20a2f3f0c0f136403918afacf Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 6 Jun 2019 10:51:02 -0700 Subject: [PATCH 175/213] Initial adaptation of muxpack from shregmap --- passes/techmap/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc index cf9e198ad..561636080 100644 --- a/passes/techmap/Makefile.inc +++ b/passes/techmap/Makefile.inc @@ -37,6 +37,7 @@ OBJS += passes/techmap/attrmap.o OBJS += passes/techmap/zinit.o OBJS += passes/techmap/dff2dffs.o OBJS += passes/techmap/flowmap.o +OBJS += passes/techmap/muxpack.o endif GENFILES += passes/techmap/techmap.inc From 543dd11c7e46f9c88bd1f0d21474bac95d1ab6d1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 6 Jun 2019 11:03:45 -0700 Subject: [PATCH 176/213] Missing file --- passes/techmap/muxpack.cc | 232 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 232 insertions(+) create mode 100644 passes/techmap/muxpack.cc diff --git a/passes/techmap/muxpack.cc b/passes/techmap/muxpack.cc new file mode 100644 index 000000000..4945affb0 --- /dev/null +++ b/passes/techmap/muxpack.cc @@ -0,0 +1,232 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * 2019 Eddie Hung + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" +#include "kernel/sigtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct MuxpackWorker +{ + Module *module; + SigMap sigmap; + + int mux_count, pmux_count; + + pool remove_cells; + + dict sig_chain_next; + dict sig_chain_prev; + pool sigbit_with_non_chain_users; + pool chain_start_cells; + + void make_sig_chain_next_prev() + { + for (auto wire : module->wires()) + { + if (wire->port_output || wire->get_bool_attribute("\\keep")) { + for (auto bit : sigmap(wire)) { + sigbit_with_non_chain_users.insert(bit); + } + } + } + + for (auto cell : module->cells()) + { + if (cell->type.in("$mux") && !cell->get_bool_attribute("\\keep")) + { + SigSpec a_sig = sigmap(cell->getPort("\\A")); + SigSpec y_sig = sigmap(cell->getPort("\\Y")); + + if (sig_chain_next.count(a_sig)) + for (auto a_bit : a_sig.bits()) + sigbit_with_non_chain_users.insert(a_bit); + else + sig_chain_next[a_sig] = cell; + + sig_chain_prev[y_sig] = cell; + continue; + } + + for (auto conn : cell->connections()) + if (cell->input(conn.first)) + for (auto bit : sigmap(conn.second)) + sigbit_with_non_chain_users.insert(bit); + } + } + + void find_chain_start_cells() + { + for (auto it : sig_chain_next) + { + for (auto bit : it.first.bits()) + if (sigbit_with_non_chain_users.count(bit)) + goto start_cell; + + if (sig_chain_prev.count(it.first) != 0) + { + Cell *c1 = sig_chain_prev.at(it.first); + Cell *c2 = it.second; + + if (c1->type != c2->type) + goto start_cell; + + if (c1->parameters != c2->parameters) + goto start_cell; + + continue; + } + + start_cell: + chain_start_cells.insert(it.second); + } + } + + vector create_chain(Cell *start_cell) + { + vector chain; + + Cell *c = start_cell; + while (c != nullptr) + { + chain.push_back(c); + + SigSpec y_sig = sigmap(c->getPort("\\Y")); + + if (sig_chain_next.count(y_sig) == 0) + break; + + c = sig_chain_next.at(y_sig); + if (chain_start_cells.count(c) != 0) + break; + } + + return chain; + } + + void process_chain(vector &chain) + { + if (GetSize(chain) < 2) + return; + + int cursor = 0; + while (cursor < GetSize(chain)) + { + int cases = GetSize(chain) - cursor; + + Cell *first_cell = chain[cursor]; + dict taps_dict; + + if (cases < 2) { + cursor++; + continue; + } + + Cell *last_cell = chain[cursor+cases-1]; + + log("Converting %s.%s ... %s.%s to a pmux with %d cases.\n", + log_id(module), log_id(first_cell), log_id(module), log_id(last_cell), cases); + + mux_count += cases; + pmux_count += 1; + + first_cell->type = "$pmux"; + SigSpec b_sig = first_cell->getPort("\\B"); + SigSpec s_sig = first_cell->getPort("\\S"); + + for (int i = 1; i < cases; i++) { + Cell* cursor_cell = chain[cursor+i]; + b_sig.append(cursor_cell->getPort("\\B")); + s_sig.append(cursor_cell->getPort("\\S")); + remove_cells.insert(cursor_cell); + } + + first_cell->setPort("\\B", b_sig); + first_cell->setPort("\\S", s_sig); + first_cell->setParam("\\S_WIDTH", GetSize(s_sig)); + first_cell->setPort("\\Y", last_cell->getPort("\\Y")); + + cursor += cases; + } + } + + void cleanup() + { + for (auto cell : remove_cells) + module->remove(cell); + + remove_cells.clear(); + sig_chain_next.clear(); + sig_chain_prev.clear(); + chain_start_cells.clear(); + } + + MuxpackWorker(Module *module) : + module(module), sigmap(module), mux_count(0), pmux_count(0) + { + make_sig_chain_next_prev(); + find_chain_start_cells(); + + for (auto c : chain_start_cells) { + vector chain = create_chain(c); + process_chain(chain); + } + + cleanup(); + } +}; + +struct MuxpackPass : public Pass { + MuxpackPass() : Pass("muxpack", "TODO") { } + void help() YS_OVERRIDE + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" muxpack [options] [selection]\n"); + log("\n"); + log("TODO"); + log("\n"); + } + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + { + log_header(design, "Executing MUXPACK pass (TODO).\n"); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + break; + } + extra_args(args, argidx, design); + + int mux_count = 0; + int pmux_count = 0; + + for (auto module : design->selected_modules()) { + MuxpackWorker worker(module); + mux_count += worker.mux_count; + pmux_count += worker.pmux_count; + } + + log("Converted %d (p)mux cells into %d pmux cells.\n", mux_count, pmux_count); + } +} MuxpackPass; + +PRIVATE_NAMESPACE_END From 3e76e3a6fa4355e7223b10bba394f986d6821551 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 6 Jun 2019 11:54:38 -0700 Subject: [PATCH 177/213] Add tests, fix for != --- passes/techmap/muxpack.cc | 41 +++++++++++++++++++++++++++++--------- tests/various/muxpack.v | 36 +++++++++++++++++++++++++++++++++ tests/various/muxpack.ys | 42 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 110 insertions(+), 9 deletions(-) create mode 100644 tests/various/muxpack.v create mode 100644 tests/various/muxpack.ys diff --git a/passes/techmap/muxpack.cc b/passes/techmap/muxpack.cc index 4945affb0..54c52150a 100644 --- a/passes/techmap/muxpack.cc +++ b/passes/techmap/muxpack.cc @@ -54,14 +54,21 @@ struct MuxpackWorker if (cell->type.in("$mux") && !cell->get_bool_attribute("\\keep")) { SigSpec a_sig = sigmap(cell->getPort("\\A")); + SigSpec b_sig = sigmap(cell->getPort("\\B")); SigSpec y_sig = sigmap(cell->getPort("\\Y")); if (sig_chain_next.count(a_sig)) for (auto a_bit : a_sig.bits()) sigbit_with_non_chain_users.insert(a_bit); - else + else sig_chain_next[a_sig] = cell; + if (sig_chain_next.count(b_sig)) + for (auto b_bit : b_sig.bits()) + sigbit_with_non_chain_users.insert(b_bit); + else + sig_chain_next[b_sig] = cell; + sig_chain_prev[y_sig] = cell; continue; } @@ -77,13 +84,22 @@ struct MuxpackWorker { for (auto it : sig_chain_next) { + SigSpec next_sig; + for (auto bit : it.first.bits()) if (sigbit_with_non_chain_users.count(bit)) goto start_cell; - if (sig_chain_prev.count(it.first) != 0) + next_sig = it.second->getPort("\\A"); + if (sig_chain_prev.count(next_sig) == 0) { + next_sig = it.second->getPort("\\B"); + if (sig_chain_prev.count(next_sig) == 0) + next_sig = SigSpec(); + } + + if (!next_sig.empty()) { - Cell *c1 = sig_chain_prev.at(it.first); + Cell *c1 = sig_chain_prev.at(next_sig); Cell *c2 = it.second; if (c1->type != c2->type) @@ -149,15 +165,22 @@ struct MuxpackWorker pmux_count += 1; first_cell->type = "$pmux"; - SigSpec b_sig = first_cell->getPort("\\B"); - SigSpec s_sig = first_cell->getPort("\\S"); + SigSpec b_sig = first_cell->getPort("\\B"); + SigSpec s_sig = first_cell->getPort("\\S"); for (int i = 1; i < cases; i++) { - Cell* cursor_cell = chain[cursor+i]; - b_sig.append(cursor_cell->getPort("\\B")); - s_sig.append(cursor_cell->getPort("\\S")); + Cell* prev_cell = chain[cursor+i-1]; + Cell* cursor_cell = chain[cursor+i]; + if (sigmap(prev_cell->getPort("\\Y")) == sigmap(cursor_cell->getPort("\\A"))) { + b_sig.append(cursor_cell->getPort("\\B")); + s_sig.append(cursor_cell->getPort("\\S")); + } + else { + b_sig.append(cursor_cell->getPort("\\A")); + s_sig.append(module->LogicNot(NEW_ID, cursor_cell->getPort("\\S"))); + } remove_cells.insert(cursor_cell); - } + } first_cell->setPort("\\B", b_sig); first_cell->setPort("\\S", s_sig); diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v new file mode 100644 index 000000000..abc87ba44 --- /dev/null +++ b/tests/various/muxpack.v @@ -0,0 +1,36 @@ +module mux_if_unbal_4_1 #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); +always @* + if (s == 0) o <= i[0*W+:W]; + else if (s == 1) o <= i[1*W+:W]; + else if (s == 2) o <= i[2*W+:W]; + else if (s == 3) o <= i[3*W+:W]; + else o <= {W{1'bx}}; + +endmodule + +module mux_if_unbal_5_3 #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); +always @* begin + o <= {W{1'bx}}; + if (s == 0) o <= i[0*W+:W]; + if (s == 1) o <= i[1*W+:W]; + if (s == 2) o <= i[2*W+:W]; + if (s == 3) o <= i[3*W+:W]; + if (s == 4) o <= i[4*W+:W]; +end + +endmodule + +module mux_if_unbal_5_3_invert #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); +always @* + if (s != 0) + if (s != 1) + if (s != 2) + if (s != 3) + if (s != 4) o <= i[4*W+:W]; + else o <= i[0*W+:W]; + else o <= i[3*W+:W]; + else o <= i[2*W+:W]; + else o <= i[1*W+:W]; + else o <= {W{1'bx}}; + +endmodule diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys new file mode 100644 index 000000000..58c01cf05 --- /dev/null +++ b/tests/various/muxpack.ys @@ -0,0 +1,42 @@ +read_verilog muxpack.v +design -save read +hierarchy -top mux_if_unbal_4_1 +prep +design -save gold +muxpack +opt +stat +select -assert-count 1 t:$pmux +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter + +design -load read +hierarchy -top mux_if_unbal_5_3 +prep +design -save gold +muxpack +opt +stat +select -assert-count 1 t:$pmux +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter + +design -load read +hierarchy -top mux_if_unbal_5_3_invert +prep +design -save gold +muxpack +opt +stat +select -assert-count 1 t:$pmux +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter From 5d4eca5a298d2f98de220cfd0efe5452ab4052d8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 6 Jun 2019 11:59:41 -0700 Subject: [PATCH 178/213] Add a few more special case tests --- tests/various/muxpack.v | 23 +++++++++++++++++++++++ tests/various/muxpack.ys | 28 ++++++++++++++++++++++++++++ 2 files changed, 51 insertions(+) diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v index abc87ba44..333908fcb 100644 --- a/tests/various/muxpack.v +++ b/tests/various/muxpack.v @@ -34,3 +34,26 @@ always @* else o <= {W{1'bx}}; endmodule + +module mux_if_unbal_5_3_width_mismatch #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); +always @* begin + o <= {W{1'bx}}; + if (s == 0) o <= i[0*W+:W]; + if (s == 1) o <= i[1*W+:W]; + if (s == 2) o[W-2:0] <= i[2*W+:W-1]; + if (s == 3) o <= i[3*W+:W]; + if (s == 4) o <= i[4*W+:W]; +end + +endmodule + +module mux_if_unbal_5_3_missing #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); +always @* begin + if (s == 0) o <= i[0*W+:W]; +// else if (s == 1) o <= i[1*W+:W]; +// else if (s == 2) o <= i[2*W+:W]; + else if (s == 3) o <= i[3*W+:W]; + else o <= {W{1'bx}}; +end + +endmodule diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys index 58c01cf05..174eea74b 100644 --- a/tests/various/muxpack.ys +++ b/tests/various/muxpack.ys @@ -40,3 +40,31 @@ design -import gold -as gold design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter + +design -load read +hierarchy -top mux_if_unbal_5_3_width_mismatch +prep +design -save gold +muxpack +opt +stat +select -assert-count 2 t:$pmux +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter + +design -load read +hierarchy -top mux_if_unbal_5_3_missing +prep +design -save gold +muxpack +opt +stat +select -assert-count 1 t:$pmux +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter From b8620f7b3dde4460e5a8ed3ea7fd7aef54aa7da1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 6 Jun 2019 12:03:44 -0700 Subject: [PATCH 179/213] One more and tidy up --- tests/various/muxpack.v | 20 ++++++++++++++------ tests/various/muxpack.ys | 16 +++++++++++++++- 2 files changed, 29 insertions(+), 7 deletions(-) diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v index 333908fcb..c2c2537a0 100644 --- a/tests/various/muxpack.v +++ b/tests/various/muxpack.v @@ -5,7 +5,6 @@ always @* else if (s == 2) o <= i[2*W+:W]; else if (s == 3) o <= i[3*W+:W]; else o <= {W{1'bx}}; - endmodule module mux_if_unbal_5_3 #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); @@ -17,7 +16,6 @@ always @* begin if (s == 3) o <= i[3*W+:W]; if (s == 4) o <= i[4*W+:W]; end - endmodule module mux_if_unbal_5_3_invert #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); @@ -32,7 +30,6 @@ always @* else o <= i[2*W+:W]; else o <= i[1*W+:W]; else o <= {W{1'bx}}; - endmodule module mux_if_unbal_5_3_width_mismatch #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); @@ -44,10 +41,9 @@ always @* begin if (s == 3) o <= i[3*W+:W]; if (s == 4) o <= i[4*W+:W]; end - endmodule -module mux_if_unbal_5_3_missing #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); +module mux_if_unbal_4_1_missing #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); always @* begin if (s == 0) o <= i[0*W+:W]; // else if (s == 1) o <= i[1*W+:W]; @@ -55,5 +51,17 @@ always @* begin else if (s == 3) o <= i[3*W+:W]; else o <= {W{1'bx}}; end - endmodule + +module mux_if_unbal_5_3_order #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); +always @* begin + o <= {W{1'bx}}; + if (s == 3) o <= i[3*W+:W]; + if (s == 2) o <= i[2*W+:W]; + if (s == 1) o <= i[1*W+:W]; + if (s == 4) o <= i[4*W+:W]; + if (s == 0) o <= i[0*W+:W]; +end +endmodule + + diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys index 174eea74b..a967ddfef 100644 --- a/tests/various/muxpack.ys +++ b/tests/various/muxpack.ys @@ -56,7 +56,21 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter design -load read -hierarchy -top mux_if_unbal_5_3_missing +hierarchy -top mux_if_unbal_4_1_missing +prep +design -save gold +muxpack +opt +stat +select -assert-count 1 t:$pmux +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter + +design -load read +hierarchy -top mux_if_unbal_5_3_order prep design -save gold muxpack From 030f1d30e9cd04b4412114bdc93a15a39a4597c4 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 6 Jun 2019 12:04:42 -0700 Subject: [PATCH 180/213] Add to CHANGELOG --- CHANGELOG | 1 + 1 file changed, 1 insertion(+) diff --git a/CHANGELOG b/CHANGELOG index 36b64e111..e67d9c903 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -16,6 +16,7 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "gate2lut.v" techmap rule - Added "rename -src" - Added "equiv_opt" pass + - Added "muxpack" pass - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx" From 3dd0682f298cec18f60c2d9da6417e287a385dd4 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 6 Jun 2019 12:11:59 -0700 Subject: [PATCH 181/213] Update doc --- passes/techmap/muxpack.cc | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/passes/techmap/muxpack.cc b/passes/techmap/muxpack.cc index 54c52150a..9668b0d43 100644 --- a/passes/techmap/muxpack.cc +++ b/passes/techmap/muxpack.cc @@ -218,19 +218,20 @@ struct MuxpackWorker }; struct MuxpackPass : public Pass { - MuxpackPass() : Pass("muxpack", "TODO") { } + MuxpackPass() : Pass("muxpack", "$mux cell cascades to $pmux") { } void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); - log(" muxpack [options] [selection]\n"); + log(" muxpack [selection]\n"); log("\n"); - log("TODO"); + log("This pass converts cascaded chains of $mux cells (e.g. those created by if-else\n"); + log("constructs) into $pmux cells.\n"); log("\n"); } void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { - log_header(design, "Executing MUXPACK pass (TODO).\n"); + log_header(design, "Executing MUXPACK pass ($mux cell cascades to $pmux).\n"); size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) From 83450a94898321a239f67f92e05fb9a246f4dd6d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 6 Jun 2019 12:15:13 -0700 Subject: [PATCH 182/213] Move muxpack from passes/techmap to passes/opt --- passes/opt/Makefile.inc | 1 + passes/{techmap => opt}/muxpack.cc | 0 passes/techmap/Makefile.inc | 1 - 3 files changed, 1 insertion(+), 1 deletion(-) rename passes/{techmap => opt}/muxpack.cc (100%) diff --git a/passes/opt/Makefile.inc b/passes/opt/Makefile.inc index 337fee9e4..ea3646330 100644 --- a/passes/opt/Makefile.inc +++ b/passes/opt/Makefile.inc @@ -14,5 +14,6 @@ OBJS += passes/opt/opt_demorgan.o OBJS += passes/opt/rmports.o OBJS += passes/opt/opt_lut.o OBJS += passes/opt/pmux2shiftx.o +OBJS += passes/opt/muxpack.o endif diff --git a/passes/techmap/muxpack.cc b/passes/opt/muxpack.cc similarity index 100% rename from passes/techmap/muxpack.cc rename to passes/opt/muxpack.cc diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc index 561636080..cf9e198ad 100644 --- a/passes/techmap/Makefile.inc +++ b/passes/techmap/Makefile.inc @@ -37,7 +37,6 @@ OBJS += passes/techmap/attrmap.o OBJS += passes/techmap/zinit.o OBJS += passes/techmap/dff2dffs.o OBJS += passes/techmap/flowmap.o -OBJS += passes/techmap/muxpack.o endif GENFILES += passes/techmap/techmap.inc From 705388eb24022d2a310ae72cd81e67a2f0ce7586 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 6 Jun 2019 12:44:06 -0700 Subject: [PATCH 183/213] Add non exclusive test --- tests/various/muxpack.v | 20 ++++++++++++++++++++ tests/various/muxpack.ys | 36 ++++++++++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+) diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v index c2c2537a0..e847fef27 100644 --- a/tests/various/muxpack.v +++ b/tests/various/muxpack.v @@ -64,4 +64,24 @@ always @* begin end endmodule +module mux_if_unbal_4_1_nonexcl #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); +always @* + if (s == 0) o <= i[0*W+:W]; + else if (s == 1) o <= i[1*W+:W]; + else if (s == 2) o <= i[2*W+:W]; + else if (s == 3) o <= i[3*W+:W]; + else if (s == 0) o <= {W{1'b0}}; + else o <= {W{1'bx}}; +endmodule +module mux_if_unbal_5_3_nonexcl #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); +always @* begin + o <= {W{1'bx}}; + if (s == 0) o <= i[0*W+:W]; + if (s == 1) o <= i[1*W+:W]; + if (s == 2) o <= i[2*W+:W]; + if (s == 3) o <= i[3*W+:W]; + if (s == 4) o <= i[4*W+:W]; + if (s == 0) o <= i[2*W+:W]; +end +endmodule diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys index a967ddfef..178860b88 100644 --- a/tests/various/muxpack.ys +++ b/tests/various/muxpack.ys @@ -6,6 +6,7 @@ design -save gold muxpack opt stat +select -assert-count 0 t:$mux select -assert-count 1 t:$pmux design -stash gate design -import gold -as gold @@ -20,6 +21,7 @@ design -save gold muxpack opt stat +select -assert-count 0 t:$mux select -assert-count 1 t:$pmux design -stash gate design -import gold -as gold @@ -34,6 +36,7 @@ design -save gold muxpack opt stat +select -assert-count 0 t:$mux select -assert-count 1 t:$pmux design -stash gate design -import gold -as gold @@ -48,6 +51,7 @@ design -save gold muxpack opt stat +select -assert-count 0 t:$mux select -assert-count 2 t:$pmux design -stash gate design -import gold -as gold @@ -62,6 +66,7 @@ design -save gold muxpack opt stat +select -assert-count 0 t:$mux select -assert-count 1 t:$pmux design -stash gate design -import gold -as gold @@ -76,6 +81,37 @@ design -save gold muxpack opt stat +select -assert-count 0 t:$mux +select -assert-count 1 t:$pmux +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter + +design -load read +hierarchy -top mux_if_unbal_4_1_nonexcl +prep +design -save gold +muxpack +opt +stat +select -assert-count 0 t:$mux +select -assert-count 1 t:$pmux +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter + +design -load read +hierarchy -top mux_if_unbal_5_3_nonexcl +prep +design -save gold +muxpack +opt +stat +select -assert-count 0 t:$mux select -assert-count 1 t:$pmux design -stash gate design -import gold -as gold From d2172c6846f710e9a362708e3308dd302110deb2 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 6 Jun 2019 12:44:50 -0700 Subject: [PATCH 184/213] Non chain user check using next_sig --- passes/opt/muxpack.cc | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/passes/opt/muxpack.cc b/passes/opt/muxpack.cc index 9668b0d43..963083107 100644 --- a/passes/opt/muxpack.cc +++ b/passes/opt/muxpack.cc @@ -84,19 +84,17 @@ struct MuxpackWorker { for (auto it : sig_chain_next) { - SigSpec next_sig; - - for (auto bit : it.first.bits()) - if (sigbit_with_non_chain_users.count(bit)) - goto start_cell; - - next_sig = it.second->getPort("\\A"); + SigSpec next_sig = it.second->getPort("\\A"); if (sig_chain_prev.count(next_sig) == 0) { next_sig = it.second->getPort("\\B"); if (sig_chain_prev.count(next_sig) == 0) next_sig = SigSpec(); } + for (auto bit : next_sig.bits()) + if (sigbit_with_non_chain_users.count(bit)) + goto start_cell; + if (!next_sig.empty()) { Cell *c1 = sig_chain_prev.at(next_sig); From 978fda94f684185a7d583a3865b7a68459344e46 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 6 Jun 2019 12:46:42 -0700 Subject: [PATCH 185/213] Fix spacing --- passes/opt/muxpack.cc | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/passes/opt/muxpack.cc b/passes/opt/muxpack.cc index 963083107..cb13a45b0 100644 --- a/passes/opt/muxpack.cc +++ b/passes/opt/muxpack.cc @@ -43,9 +43,8 @@ struct MuxpackWorker for (auto wire : module->wires()) { if (wire->port_output || wire->get_bool_attribute("\\keep")) { - for (auto bit : sigmap(wire)) { + for (auto bit : sigmap(wire)) sigbit_with_non_chain_users.insert(bit); - } } } @@ -58,8 +57,8 @@ struct MuxpackWorker SigSpec y_sig = sigmap(cell->getPort("\\Y")); if (sig_chain_next.count(a_sig)) - for (auto a_bit : a_sig.bits()) - sigbit_with_non_chain_users.insert(a_bit); + for (auto a_bit : a_sig.bits()) + sigbit_with_non_chain_users.insert(a_bit); else sig_chain_next[a_sig] = cell; @@ -70,7 +69,7 @@ struct MuxpackWorker sig_chain_next[b_sig] = cell; sig_chain_prev[y_sig] = cell; - continue; + continue; } for (auto conn : cell->connections()) @@ -182,7 +181,7 @@ struct MuxpackWorker first_cell->setPort("\\B", b_sig); first_cell->setPort("\\S", s_sig); - first_cell->setParam("\\S_WIDTH", GetSize(s_sig)); + first_cell->setParam("\\S_WIDTH", GetSize(s_sig)); first_cell->setPort("\\Y", last_cell->getPort("\\Y")); cursor += cases; From dc7b8c4b942f9d9bc61a87a81291244d0b73843b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 6 Jun 2019 12:56:34 -0700 Subject: [PATCH 186/213] More cleanup --- passes/opt/muxpack.cc | 35 ++++++++++++++++++++--------------- 1 file changed, 20 insertions(+), 15 deletions(-) diff --git a/passes/opt/muxpack.cc b/passes/opt/muxpack.cc index cb13a45b0..ae4b67db2 100644 --- a/passes/opt/muxpack.cc +++ b/passes/opt/muxpack.cc @@ -37,6 +37,7 @@ struct MuxpackWorker dict sig_chain_prev; pool sigbit_with_non_chain_users; pool chain_start_cells; + pool candidate_cells; void make_sig_chain_next_prev() { @@ -59,14 +60,18 @@ struct MuxpackWorker if (sig_chain_next.count(a_sig)) for (auto a_bit : a_sig.bits()) sigbit_with_non_chain_users.insert(a_bit); - else + else { sig_chain_next[a_sig] = cell; + candidate_cells.insert(cell); + } if (sig_chain_next.count(b_sig)) for (auto b_bit : b_sig.bits()) sigbit_with_non_chain_users.insert(b_bit); - else + else { sig_chain_next[b_sig] = cell; + candidate_cells.insert(cell); + } sig_chain_prev[y_sig] = cell; continue; @@ -81,35 +86,34 @@ struct MuxpackWorker void find_chain_start_cells() { - for (auto it : sig_chain_next) + for (auto cell : candidate_cells) { - SigSpec next_sig = it.second->getPort("\\A"); + SigSpec next_sig = cell->getPort("\\A"); if (sig_chain_prev.count(next_sig) == 0) { - next_sig = it.second->getPort("\\B"); + next_sig = cell->getPort("\\B"); if (sig_chain_prev.count(next_sig) == 0) - next_sig = SigSpec(); + goto start_cell; } - for (auto bit : next_sig.bits()) - if (sigbit_with_non_chain_users.count(bit)) - goto start_cell; - - if (!next_sig.empty()) { + for (auto bit : next_sig.bits()) + if (sigbit_with_non_chain_users.count(bit)) + goto start_cell; + Cell *c1 = sig_chain_prev.at(next_sig); - Cell *c2 = it.second; + Cell *c2 = cell; if (c1->type != c2->type) goto start_cell; if (c1->parameters != c2->parameters) goto start_cell; - - continue; } + continue; + start_cell: - chain_start_cells.insert(it.second); + chain_start_cells.insert(cell); } } @@ -197,6 +201,7 @@ struct MuxpackWorker sig_chain_next.clear(); sig_chain_prev.clear(); chain_start_cells.clear(); + candidate_cells.clear(); } MuxpackWorker(Module *module) : From ccdf989025e57da7dfd5ab609676ebe3cfb2c2d6 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 6 Jun 2019 13:51:22 -0700 Subject: [PATCH 187/213] Support cascading $pmux.A with $mux.A and $mux.B --- passes/opt/muxpack.cc | 42 ++++++++++++++++++++++++---------------- tests/various/muxpack.v | 25 ++++++++++++++++++++++++ tests/various/muxpack.ys | 15 ++++++++++++++ 3 files changed, 65 insertions(+), 17 deletions(-) diff --git a/passes/opt/muxpack.cc b/passes/opt/muxpack.cc index ae4b67db2..f9e5c8f09 100644 --- a/passes/opt/muxpack.cc +++ b/passes/opt/muxpack.cc @@ -51,10 +51,12 @@ struct MuxpackWorker for (auto cell : module->cells()) { - if (cell->type.in("$mux") && !cell->get_bool_attribute("\\keep")) + if (cell->type.in("$mux", "$pmux") && !cell->get_bool_attribute("\\keep")) { SigSpec a_sig = sigmap(cell->getPort("\\A")); - SigSpec b_sig = sigmap(cell->getPort("\\B")); + SigSpec b_sig; + if (cell->type == "$mux") + b_sig = sigmap(cell->getPort("\\B")); SigSpec y_sig = sigmap(cell->getPort("\\Y")); if (sig_chain_next.count(a_sig)) @@ -65,12 +67,14 @@ struct MuxpackWorker candidate_cells.insert(cell); } - if (sig_chain_next.count(b_sig)) - for (auto b_bit : b_sig.bits()) - sigbit_with_non_chain_users.insert(b_bit); - else { - sig_chain_next[b_sig] = cell; - candidate_cells.insert(cell); + if (!b_sig.empty()) { + if (sig_chain_next.count(b_sig)) + for (auto b_bit : b_sig.bits()) + sigbit_with_non_chain_users.insert(b_bit); + else { + sig_chain_next[b_sig] = cell; + candidate_cells.insert(cell); + } } sig_chain_prev[y_sig] = cell; @@ -88,10 +92,16 @@ struct MuxpackWorker { for (auto cell : candidate_cells) { + log_debug("Considering %s (%s)\n", log_id(cell), log_id(cell->type)); + SigSpec next_sig = cell->getPort("\\A"); if (sig_chain_prev.count(next_sig) == 0) { - next_sig = cell->getPort("\\B"); - if (sig_chain_prev.count(next_sig) == 0) + if (cell->type == "$mux") { + next_sig = cell->getPort("\\B"); + if (sig_chain_prev.count(next_sig) == 0) + goto start_cell; + } + else goto start_cell; } @@ -103,10 +113,7 @@ struct MuxpackWorker Cell *c1 = sig_chain_prev.at(next_sig); Cell *c2 = cell; - if (c1->type != c2->type) - goto start_cell; - - if (c1->parameters != c2->parameters) + if (c1->getParam("\\WIDTH") != c2->getParam("\\WIDTH")) goto start_cell; } @@ -220,15 +227,16 @@ struct MuxpackWorker }; struct MuxpackPass : public Pass { - MuxpackPass() : Pass("muxpack", "$mux cell cascades to $pmux") { } + MuxpackPass() : Pass("muxpack", "$mux/$pmux cascades to $pmux") { } void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); log(" muxpack [selection]\n"); log("\n"); - log("This pass converts cascaded chains of $mux cells (e.g. those created by if-else\n"); - log("constructs) into $pmux cells.\n"); + log("This pass converts cascaded chains of $pmux cells (e.g. those create from case\n"); + log("constructs) and $mux cells (e.g. those created by if-else constructs) into \n"); + log("into $pmux cells.\n"); log("\n"); } void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v index e847fef27..fe0150532 100644 --- a/tests/various/muxpack.v +++ b/tests/various/muxpack.v @@ -85,3 +85,28 @@ always @* begin if (s == 0) o <= i[2*W+:W]; end endmodule + +module mux_case_unbal_7_7#(parameter N=7, parameter W=7) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); +always @* begin + o <= {W{1'bx}}; + case (s) + 0: o <= i[0*W+:W]; + default: + case (s) + 1: o <= i[1*W+:W]; + 2: o <= i[2*W+:W]; + default: + case (s) + 3: o <= i[3*W+:W]; + 4: o <= i[4*W+:W]; + 5: o <= i[5*W+:W]; + default: + case (s) + 6: o <= i[6*W+:W]; + default: o <= i[7*W+:W]; + endcase + endcase + endcase + endcase +end +endmodule diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys index 178860b88..4dcb9ed89 100644 --- a/tests/various/muxpack.ys +++ b/tests/various/muxpack.ys @@ -118,3 +118,18 @@ design -import gold -as gold design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter + +design -load read +hierarchy -top mux_case_unbal_7_7 +prep +design -save gold +muxpack +opt +stat +select -assert-count 0 t:$mux +select -assert-count 1 t:$pmux +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter From 0a66720f6f67b087fe6342d01d45944506240942 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 6 Jun 2019 14:01:42 -0700 Subject: [PATCH 188/213] Fix warnings --- tests/various/muxpack.v | 4 ++-- tests/various/muxpack.ys | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v index fe0150532..7c189fff8 100644 --- a/tests/various/muxpack.v +++ b/tests/various/muxpack.v @@ -74,7 +74,7 @@ always @* else o <= {W{1'bx}}; endmodule -module mux_if_unbal_5_3_nonexcl #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); +module mux_if_unbal_5_3_nonexcl #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); always @* begin o <= {W{1'bx}}; if (s == 0) o <= i[0*W+:W]; @@ -86,7 +86,7 @@ always @* begin end endmodule -module mux_case_unbal_7_7#(parameter N=7, parameter W=7) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); +module mux_case_unbal_8_7#(parameter N=8, parameter W=7) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); always @* begin o <= {W{1'bx}}; case (s) diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys index 4dcb9ed89..0c5b82818 100644 --- a/tests/various/muxpack.ys +++ b/tests/various/muxpack.ys @@ -120,7 +120,7 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter design -load read -hierarchy -top mux_case_unbal_7_7 +hierarchy -top mux_case_unbal_8_7 prep design -save gold muxpack From 5c277c6325b78bfe18cf294b63ea69ff272e69c5 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 6 Jun 2019 14:21:34 -0700 Subject: [PATCH 189/213] Fix and test for balanced case --- passes/opt/muxpack.cc | 24 ++++++++++++++---------- tests/various/muxpack.v | 26 ++++++++++++++++++++++++++ tests/various/muxpack.ys | 15 +++++++++++++++ 3 files changed, 55 insertions(+), 10 deletions(-) diff --git a/passes/opt/muxpack.cc b/passes/opt/muxpack.cc index f9e5c8f09..8c4db4e4d 100644 --- a/passes/opt/muxpack.cc +++ b/passes/opt/muxpack.cc @@ -94,23 +94,27 @@ struct MuxpackWorker { log_debug("Considering %s (%s)\n", log_id(cell), log_id(cell->type)); - SigSpec next_sig = cell->getPort("\\A"); - if (sig_chain_prev.count(next_sig) == 0) { - if (cell->type == "$mux") { - next_sig = cell->getPort("\\B"); - if (sig_chain_prev.count(next_sig) == 0) - goto start_cell; - } - else + SigSpec a_sig = cell->getPort("\\A"); + if (cell->type == "$mux") { + SigSpec b_sig = cell->getPort("\\B"); + if (sig_chain_prev.count(a_sig) + sig_chain_prev.count(b_sig) != 1) + goto start_cell; + + if (!sig_chain_prev.count(a_sig)) + a_sig = b_sig; + } + else if (cell->type == "$pmux") { + if (!sig_chain_prev.count(a_sig)) goto start_cell; } + else log_abort(); { - for (auto bit : next_sig.bits()) + for (auto bit : a_sig.bits()) if (sigbit_with_non_chain_users.count(bit)) goto start_cell; - Cell *c1 = sig_chain_prev.at(next_sig); + Cell *c1 = sig_chain_prev.at(a_sig); Cell *c2 = cell; if (c1->getParam("\\WIDTH") != c2->getParam("\\WIDTH")) diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v index 7c189fff8..f1bd5ea8e 100644 --- a/tests/various/muxpack.v +++ b/tests/various/muxpack.v @@ -110,3 +110,29 @@ always @* begin endcase end endmodule + +module mux_if_bal_8_2 #(parameter N=8, parameter W=2) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); +always @* + if (s[0] == 1'b0) + if (s[1] == 1'b0) + if (s[2] == 1'b0) + o <= i[0*W+:W]; + else + o <= i[1*W+:W]; + else + if (s[2] == 1'b0) + o <= i[2*W+:W]; + else + o <= i[3*W+:W]; + else + if (s[1] == 1'b0) + if (s[2] == 1'b0) + o <= i[4*W+:W]; + else + o <= i[5*W+:W]; + else + if (s[2] == 1'b0) + o <= i[6*W+:W]; + else + o <= i[7*W+:W]; +endmodule diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys index 0c5b82818..9ea743b9f 100644 --- a/tests/various/muxpack.ys +++ b/tests/various/muxpack.ys @@ -133,3 +133,18 @@ design -import gold -as gold design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter + +design -load read +hierarchy -top mux_if_bal_8_2 +prep +design -save gold +muxpack +opt +stat +select -assert-count 7 t:$mux +select -assert-count 0 t:$pmux +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter From 7166dbe418420bf8f0696b21bff22d5f66a4cc8e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 6 Jun 2019 14:35:38 -0700 Subject: [PATCH 190/213] Remove abc_flop attributes for now --- techlibs/xilinx/cells_sim.v | 66 ++++++------------------------------- 1 file changed, 10 insertions(+), 56 deletions(-) diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index e00992bb7..88967b068 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -205,126 +205,80 @@ endmodule `endif -(* abc_box_id = 6, abc_flop /*, lib_whitebox */ *) -module FDRE ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input D, input R); +module FDRE ((* abc_flop_q *) output reg Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_R_INVERTED = 1'b0; initial Q <= INIT; -`ifndef _ABC generate case (|IS_C_INVERTED) 1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; 1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; endcase endgenerate -`else - always @* if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; -`endif endmodule -(* abc_box_id = 7, abc_flop /*, lib_whitebox*/ *) -module FDSE ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input D, input S); +module FDSE ((* abc_flop_q *) output reg Q, input C, CE, D, S); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_S_INVERTED = 1'b0; initial Q <= INIT; -`ifndef _ABC generate case (|IS_C_INVERTED) 1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; 1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; endcase endgenerate -`else - always @* if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; -`endif endmodule -(* abc_box_id = 8, abc_flop /*, lib_whitebox*/ *) -module FDCE ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input D, input CLR); +module FDCE ((* abc_flop_q *) output reg Q, input C, CE, D, CLR); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_CLR_INVERTED = 1'b0; initial Q <= INIT; -`ifndef _ABC generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED}) 2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; 2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; 2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; 2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; endcase endgenerate -`else - generate case (|IS_CLR_INVERTED) - 1'b0: always @* if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; - 1'b1: always @* if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED; - endcase endgenerate -`endif endmodule -(* abc_box_id = 9, abc_flop /*, lib_whitebox*/ *) -module FDPE ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input D, input PRE); +module FDPE ((* abc_flop_q *) output reg Q, input C, CE, D, PRE); parameter [0:0] INIT = 1'b0; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_PRE_INVERTED = 1'b0; initial Q <= INIT; -`ifndef _ABC generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED}) 2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; 2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; 2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; 2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; endcase endgenerate -`else - generate case (|IS_PRE_INVERTED) - 1'b0: always @* if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; - 1'b1: always @* if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED; - endcase endgenerate -`endif endmodule -(* abc_box_id = 6, abc_flop /*, lib_whitebox */ *) -module FDRE_1 ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input D, input R); +module FDRE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; initial Q <= INIT; -`ifndef _ABC - always @(negedge C) if (R) Q <= 1'b0; else if (CE) Q <= D; -`else - always @* if (R) Q <= 1'b0; else if (CE) Q <= D; -`endif + always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D; endmodule -(* abc_box_id = 7, abc_flop /*, lib_whitebox */ *) -module FDSE_1 ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input D, input S); +module FDSE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, S); parameter [0:0] INIT = 1'b1; initial Q <= INIT; -`ifndef _ABC - always @(negedge C) if (S) Q <= 1'b1; else if (CE) Q <= D; -`else - always @* if (S) Q <= 1'b1; else if (CE) Q <= D; - `endif + always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D; endmodule -(* abc_box_id = 8, abc_flop /*, lib_whitebox */ *) -module FDCE_1 ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input D, input CLR); +module FDCE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, CLR); parameter [0:0] INIT = 1'b0; initial Q <= INIT; -`ifndef _ABC always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D; -`else - always @* if (CLR) Q <= 1'b0; else if (CE) Q <= D; -`endif endmodule -(* abc_box_id = 9, abc_flop /*, lib_whitebox */ *) -module FDPE_1 ((* abc_flop_q *) output reg Q, input C, CE, (* abc_flop_d *) input D, input PRE); +module FDPE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, PRE); parameter [0:0] INIT = 1'b1; initial Q <= INIT; -`ifndef _ABC always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; -`else - always @* if (PRE) Q <= 1'b1; else if (CE) Q <= D; -`endif endmodule (* abc_box_id = 4 /*, lib_whitebox*/ *) From a8c49168fb1e5e665e126c65dc454183a6d7826b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 6 Jun 2019 14:43:08 -0700 Subject: [PATCH 191/213] Run muxpack and muxcover in synth_xilinx --- techlibs/xilinx/cells_map.v | 12 ++++++++++++ techlibs/xilinx/synth_xilinx.cc | 7 ++++++- 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 4acf04744..8537dc479 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -250,3 +250,15 @@ module \$__XILINX_MUX_ (A, B, Y); end endgenerate endmodule + +module \$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y); +input A, B, C, D, E, F, G, H, S, T, U; +output Y; + \$__XILINX_MUX_ #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(3), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({A,B,C,D,E,F,G,H}), .B({U,T,S}), .Y(Y)); +endmodule + +module \$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y); +input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V; +output Y; + \$__XILINX_MUX_ #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(16), .B_WIDTH(3), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P}), .B({V,U,T,S}), .Y(Y)); +endmodule diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 7686f2cbc..a70bb23f1 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -225,6 +225,9 @@ struct SynthXilinxPass : public ScriptPass if (check_label("coarse")) { run("synth -run coarse"); + if (!nomux || help_mode) + run("muxpack", "(skip if '-nomux')"); + // shregmap -tech xilinx can cope with $shiftx and $mux // cells for identifying variable-length shift registers, // so attempt to convert $pmux-es to the former @@ -286,7 +289,9 @@ struct SynthXilinxPass : public ScriptPass } if (check_label("map_cells")) { - run("techmap -map +/techmap.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v "); + if (!nomux || help_mode) + run("muxcover", "(skip if '-nomux')"); + run("techmap -map +/techmap.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v"); run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT"); run("clean"); From d3b7ae218bd7641a40adfba7809cf0f8bdff31e6 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 6 Jun 2019 15:31:18 -0700 Subject: [PATCH 192/213] Fix muxcover and its techmapping --- techlibs/xilinx/cells_map.v | 4 ++-- techlibs/xilinx/synth_xilinx.cc | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 8537dc479..f0d3ebbac 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -254,11 +254,11 @@ endmodule module \$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y); input A, B, C, D, E, F, G, H, S, T, U; output Y; - \$__XILINX_MUX_ #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(3), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({A,B,C,D,E,F,G,H}), .B({U,T,S}), .Y(Y)); + \$__XILINX_MUX_ #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(3), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({H,G,F,E,D,C,B,A}), .B({U,T,S}), .Y(Y)); endmodule module \$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y); input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V; output Y; - \$__XILINX_MUX_ #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(16), .B_WIDTH(3), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({A,B,C,D,E,F,G,H,I,J,K,L,M,N,O,P}), .B({V,U,T,S}), .Y(Y)); + \$__XILINX_MUX_ #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(16), .B_WIDTH(4), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({P,O,N,M,L,K,J,I,H,G,F,E,D,C,B,A}), .B({V,U,T,S}), .Y(Y)); endmodule diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index a70bb23f1..a0c2c781d 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -290,7 +290,7 @@ struct SynthXilinxPass : public ScriptPass if (check_label("map_cells")) { if (!nomux || help_mode) - run("muxcover", "(skip if '-nomux')"); + run("muxcover -mux8 -mux16", "(skip if '-nomux')"); run("techmap -map +/techmap.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v"); run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT"); From 88ae13e6a55a36eb66de2424a6138b984ffb6a9e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 6 Jun 2019 15:32:36 -0700 Subject: [PATCH 193/213] $__XILINX_MUX_ -> $__XILINX_SHIFTX --- techlibs/xilinx/cells_map.v | 18 +++++++++--------- techlibs/xilinx/mux_map.v | 4 ++-- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index f0d3ebbac..f8f9356bc 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -143,7 +143,7 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o endgenerate endmodule -module \$__XILINX_MUX_ (A, B, Y); +module \$__XILINX_SHIFTX (A, B, Y); parameter A_SIGNED = 0; parameter B_SIGNED = 0; parameter A_WIDTH = 1; @@ -178,7 +178,7 @@ module \$__XILINX_MUX_ (A, B, Y); // Bit-blast if (Y_WIDTH > 1) begin for (i = 0; i < Y_WIDTH; i++) - \$__XILINX_MUX_ #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-Y_WIDTH+1), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A(A[A_WIDTH-Y_WIDTH+i:i]), .B(B), .Y(Y[i])); + \$__XILINX_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-Y_WIDTH+1), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A(A[A_WIDTH-Y_WIDTH+i:i]), .B(B), .Y(Y[i])); end // If the LSB of B is constant zero (and Y_WIDTH is 1) then // we can optimise by removing every other entry from A @@ -187,13 +187,13 @@ module \$__XILINX_MUX_ (A, B, Y); wire [(A_WIDTH+1)/2-1:0] A_i; for (i = 0; i < (A_WIDTH+1)/2; i++) assign A_i[i] = A[i*2]; - \$__XILINX_MUX_ #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y)); + \$__XILINX_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y)); end // Trim off any leading 1'bx -es in A, and resize B accordingly else if (num_leading_X_in_A > 0) begin localparam A_WIDTH_new = A_WIDTH - num_leading_X_in_A; localparam B_WIDTH_new = $clog2(A_WIDTH_new); - \$__XILINX_MUX_ #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH_new), .B_WIDTH(B_WIDTH_new), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A[A_WIDTH_new-1:0]), .B(B[B_WIDTH_new-1:0]), .Y(Y)); + \$__XILINX_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH_new), .B_WIDTH(B_WIDTH_new), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A[A_WIDTH_new-1:0]), .B(B[B_WIDTH_new-1:0]), .Y(Y)); end else if (B_WIDTH < 3 || A_WIDTH <= 4) begin \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y)); @@ -237,16 +237,16 @@ module \$__XILINX_MUX_ (A, B, Y); wire [(2**(B_WIDTH-4))-1:0] T; for (i = 0; i < 2 ** (B_WIDTH-4); i++) if (i < num_mux16) - \$__XILINX_MUX_ #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]), .Y(T[i])); + \$__XILINX_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]), .Y(T[i])); else if (i == num_mux16 && a_widthN > 0) begin if (a_widthN > 1) - \$__XILINX_MUX_ #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i])); + \$__XILINX_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_soft_mux_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i])); else assign T[i] = A[A_WIDTH-1]; end else assign T[i] = 1'bx; - \$__XILINX_MUX_ #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(2**(B_WIDTH-4)), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y)); + \$__XILINX_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(2**(B_WIDTH-4)), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y)); end endgenerate endmodule @@ -254,11 +254,11 @@ endmodule module \$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y); input A, B, C, D, E, F, G, H, S, T, U; output Y; - \$__XILINX_MUX_ #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(3), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({H,G,F,E,D,C,B,A}), .B({U,T,S}), .Y(Y)); + \$__XILINX_SHIFTX #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(3), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({H,G,F,E,D,C,B,A}), .B({U,T,S}), .Y(Y)); endmodule module \$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y); input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V; output Y; - \$__XILINX_MUX_ #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(16), .B_WIDTH(4), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({P,O,N,M,L,K,J,I,H,G,F,E,D,C,B,A}), .B({V,U,T,S}), .Y(Y)); + \$__XILINX_SHIFTX #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(16), .B_WIDTH(4), .Y_WIDTH(1)) _TECHMAP_REPLACE_ (.A({P,O,N,M,L,K,J,I,H,G,F,E,D,C,B,A}), .B({V,U,T,S}), .Y(Y)); endmodule diff --git a/techlibs/xilinx/mux_map.v b/techlibs/xilinx/mux_map.v index 2ad7f7671..0fa8db736 100644 --- a/techlibs/xilinx/mux_map.v +++ b/techlibs/xilinx/mux_map.v @@ -38,7 +38,7 @@ module \$shiftx (A, B, Y); if (B_SIGNED) begin if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && _TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0) // Optimisation to remove B_SIGNED if sign bit of B is constant-0 - \$__XILINX_MUX_ #(.A_SIGNED(A_SIGNED), .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B[B_WIDTH-2:0]), .Y(Y)); + \$__XILINX_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B[B_WIDTH-2:0]), .Y(Y)); else wire _TECHMAP_FAIL_ = 1; end @@ -46,7 +46,7 @@ module \$shiftx (A, B, Y); wire _TECHMAP_FAIL_ = 1; end else begin - \$__XILINX_MUX_ #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y)); + \$__XILINX_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y)); end endgenerate endmodule From fe4394fb9aacfaee840d2c72b88c5da666fbcb28 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 7 Jun 2019 08:30:39 -0700 Subject: [PATCH 194/213] Allow muxcover costs to be changed --- passes/techmap/muxcover.cc | 54 +++++++++++++++++++++++++++++--------- 1 file changed, 42 insertions(+), 12 deletions(-) diff --git a/passes/techmap/muxcover.cc b/passes/techmap/muxcover.cc index 12da9ed0c..32102436d 100644 --- a/passes/techmap/muxcover.cc +++ b/passes/techmap/muxcover.cc @@ -58,12 +58,21 @@ struct MuxcoverWorker bool use_mux16; bool nodecode; + int cost_mux2; + int cost_mux4; + int cost_mux8; + int cost_mux16; + MuxcoverWorker(Module *module) : module(module), sigmap(module) { use_mux4 = false; use_mux8 = false; use_mux16 = false; nodecode = false; + cost_mux2 = COST_MUX2; + cost_mux4 = COST_MUX4; + cost_mux8 = COST_MUX8; + cost_mux16 = COST_MUX16; decode_mux_counter = 0; } @@ -157,7 +166,7 @@ struct MuxcoverWorker if (std::get<2>(entry)) return 0; - return COST_MUX2 / GetSize(std::get<1>(entry)); + return cost_mux2 / GetSize(std::get<1>(entry)); } void implement_decode_mux(SigBit ctrl_bit) @@ -209,7 +218,7 @@ struct MuxcoverWorker mux.inputs.push_back(B); mux.selects.push_back(S1); - mux.cost += COST_MUX2; + mux.cost += cost_mux2; mux.cost += find_best_cover(tree, A); mux.cost += find_best_cover(tree, B); @@ -247,7 +256,7 @@ struct MuxcoverWorker mux.selects.push_back(S1); mux.selects.push_back(T1); - mux.cost += COST_MUX4; + mux.cost += cost_mux4; mux.cost += find_best_cover(tree, A); mux.cost += find_best_cover(tree, B); mux.cost += find_best_cover(tree, C); @@ -310,7 +319,7 @@ struct MuxcoverWorker mux.selects.push_back(T1); mux.selects.push_back(U1); - mux.cost += COST_MUX8; + mux.cost += cost_mux8; mux.cost += find_best_cover(tree, A); mux.cost += find_best_cover(tree, B); mux.cost += find_best_cover(tree, C); @@ -414,7 +423,7 @@ struct MuxcoverWorker mux.selects.push_back(U1); mux.selects.push_back(V1); - mux.cost += COST_MUX16; + mux.cost += cost_mux16; mux.cost += find_best_cover(tree, A); mux.cost += find_best_cover(tree, B); mux.cost += find_best_cover(tree, C); @@ -569,9 +578,11 @@ struct MuxcoverPass : public Pass { log("\n"); log("Cover trees of $_MUX_ cells with $_MUX{4,8,16}_ cells\n"); log("\n"); - log(" -mux4, -mux8, -mux16\n"); - log(" Use the specified types of MUXes. If none of those options are used,\n"); - log(" the effect is the same as if all of them where used.\n"); + log(" -mux4[=cost], -mux8[=cost], -mux16[=cost]\n"); + log(" Use the specified types of MUXes (with optional integer costs). If none\n"); + log(" of these options are given, the effect is the same as if all of them are.\n"); + log(" Default costs: $_MUX_ = %d, $_MUX4_ = %d,\n", COST_MUX2, COST_MUX4); + log(" $_MUX8_ = %d, $_MUX16_ = %d\n", COST_MUX8, COST_MUX16); log("\n"); log(" -nodecode\n"); log(" Do not insert decoder logic. This reduces the number of possible\n"); @@ -587,23 +598,39 @@ struct MuxcoverPass : public Pass { bool use_mux8 = false; bool use_mux16 = false; bool nodecode = false; + int cost_mux4 = COST_MUX4; + int cost_mux8 = COST_MUX8; + int cost_mux16 = COST_MUX16; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { - if (args[argidx] == "-mux4") { + const auto &arg = args[argidx]; + if (arg.size() >= 5 && arg.substr(0,5) == "-mux4") { use_mux4 = true; + if (arg.size() > 5) { + if (arg[5] != '=') break; + cost_mux4 = atoi(arg.substr(5).c_str()); + } continue; } - if (args[argidx] == "-mux8") { + if (arg.size() >= 5 && arg.substr(0,5) == "-mux8") { use_mux8 = true; + if (arg.size() > 5) { + if (arg[5] != '=') break; + cost_mux8 = atoi(arg.substr(5).c_str()); + } continue; } - if (args[argidx] == "-mux16") { + if (arg.size() >= 6 && arg.substr(0,6) == "-mux16") { use_mux16 = true; + if (arg.size() > 6) { + if (arg[6] != '=') break; + cost_mux16 = atoi(arg.substr(6).c_str()); + } continue; } - if (args[argidx] == "-nodecode") { + if (arg == "-nodecode") { nodecode = true; continue; } @@ -623,6 +650,9 @@ struct MuxcoverPass : public Pass { worker.use_mux4 = use_mux4; worker.use_mux8 = use_mux8; worker.use_mux16 = use_mux16; + worker.cost_mux4 = cost_mux4; + worker.cost_mux8 = cost_mux8; + worker.cost_mux16 = cost_mux16; worker.nodecode = nodecode; worker.run(); } From 5a46a0b38584014c3644cc434458638874bd4d75 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 7 Jun 2019 16:57:32 -0700 Subject: [PATCH 195/213] Fine tune aigerparse --- frontends/aiger/aigerparse.cc | 89 +++++++++++------------------------ passes/techmap/abc9.cc | 6 ++- 2 files changed, 32 insertions(+), 63 deletions(-) diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 20b43c3d3..4c19ec171 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -85,21 +85,10 @@ end_of_header: else log_abort(); - RTLIL::Wire* n0 = module->wire("\\n0"); + RTLIL::Wire* n0 = module->wire("\\__0__"); if (n0) module->connect(n0, RTLIL::S0); - for (unsigned i = 0; i < outputs.size(); ++i) { - RTLIL::Wire *wire = outputs[i]; - if (wire->port_input) { - RTLIL::Wire *o_wire = module->addWire(wire->name.str() + "_o"); - o_wire->port_output = true; - wire->port_output = false; - module->connect(o_wire, wire); - outputs[i] = o_wire; - } - } - // Parse footer (symbol table, comments, etc.) unsigned l1; std::string s; @@ -212,6 +201,10 @@ void AigerReader::parse_xaiger() else log_abort(); + RTLIL::Wire* n0 = module->wire("\\__0__"); + if (n0) + module->connect(n0, RTLIL::S0); + dict box_lookup; for (auto m : design->modules()) { auto it = m->attributes.find("\\abc_box_id"); @@ -386,31 +379,17 @@ void AigerReader::parse_aiger_ascii() if (!(f >> l1)) log_error("Line %u cannot be interpreted as an output!\n", line_count); - RTLIL::Wire *wire; - if (l1 == 0 || l1 == 1) { - wire = module->addWire(NEW_ID); - if (l1 == 0) - module->connect(wire, RTLIL::State::S0); - else if (l1 == 1) - module->connect(wire, RTLIL::State::S1); - else - log_abort(); - } - else { - log_debug("%d is an output\n", l1); - const unsigned variable = l1 >> 1; - const bool invert = l1 & 1; - RTLIL::IdString wire_name(stringf("\\__%d%s__", variable, invert ? "b" : "")); // FIXME: is "b" the right suffix? - wire = module->wire(wire_name); - if (!wire) - wire = createWireIfNotExists(module, l1); - else { - if (wire->port_input || wire->port_output) { - RTLIL::Wire *new_wire = module->addWire(NEW_ID); - module->connect(new_wire, wire); - wire = new_wire; - } - } + log_debug("%d is an output\n", l1); + const unsigned variable = l1 >> 1; + const bool invert = l1 & 1; + RTLIL::IdString wire_name(stringf("\\__%d%s__", variable, invert ? "b" : "")); // FIXME: is "b" the right suffix? + RTLIL::Wire *wire = module->wire(wire_name); + if (!wire) + wire = createWireIfNotExists(module, l1); + else if (wire->port_input || wire->port_output) { + RTLIL::Wire *new_wire = module->addWire(NEW_ID); + module->connect(new_wire, wire); + wire = new_wire; } wire->port_output = true; outputs.push_back(wire); @@ -525,31 +504,17 @@ void AigerReader::parse_aiger_binary() if (!(f >> l1)) log_error("Line %u cannot be interpreted as an output!\n", line_count); - RTLIL::Wire *wire; - if (l1 == 0 || l1 == 1) { - wire = module->addWire(NEW_ID); - if (l1 == 0) - module->connect(wire, RTLIL::State::S0); - else if (l1 == 1) - module->connect(wire, RTLIL::State::S1); - else - log_abort(); - } - else { - log_debug("%d is an output\n", l1); - const unsigned variable = l1 >> 1; - const bool invert = l1 & 1; - RTLIL::IdString wire_name(stringf("\\__%d%s__", variable, invert ? "b" : "")); // FIXME: is "_b" the right suffix? - wire = module->wire(wire_name); - if (!wire) - wire = createWireIfNotExists(module, l1); - else { - if (wire->port_input || wire->port_output) { - RTLIL::Wire *new_wire = module->addWire(NEW_ID); - module->connect(new_wire, wire); - wire = new_wire; - } - } + log_debug("%d is an output\n", l1); + const unsigned variable = l1 >> 1; + const bool invert = l1 & 1; + RTLIL::IdString wire_name(stringf("\\__%d%s__", variable, invert ? "b" : "")); // FIXME: is "_b" the right suffix? + RTLIL::Wire *wire = module->wire(wire_name); + if (!wire) + wire = createWireIfNotExists(module, l1); + else if (wire->port_input || wire->port_output) { + RTLIL::Wire *new_wire = module->addWire(NEW_ID); + module->connect(new_wire, wire); + wire = new_wire; } wire->port_output = true; outputs.push_back(wire); diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 06a638558..af9439e41 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -586,7 +586,11 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri RTLIL::Cell *cell; RTLIL::SigBit a_bit = c->getPort("\\A").as_bit(); RTLIL::SigBit y_bit = c->getPort("\\Y").as_bit(); - if (!lut_costs.empty() || !lut_file.empty()) { + if (!a_bit.wire) { + c->setPort("\\Y", module->addWire(NEW_ID)); + module->connect(module->wires_[remap_name(y_bit.wire->name)], RTLIL::S1); + } + else if (!lut_costs.empty() || !lut_file.empty()) { RTLIL::Cell* driving_lut = nullptr; // ABC can return NOT gates that drive POs if (!a_bit.wire->port_input) { From 816b5f5891adfa71586991824e9db24e7e73604a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 7 Jun 2019 16:58:57 -0700 Subject: [PATCH 196/213] Comment out muxpack (currently broken) --- techlibs/xilinx/synth_xilinx.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index a0c2c781d..ffdb22960 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -225,8 +225,8 @@ struct SynthXilinxPass : public ScriptPass if (check_label("coarse")) { run("synth -run coarse"); - if (!nomux || help_mode) - run("muxpack", "(skip if '-nomux')"); + //if (!nomux || help_mode) + // run("muxpack", "(skip if '-nomux')"); // shregmap -tech xilinx can cope with $shiftx and $mux // cells for identifying variable-length shift registers, From d5f0b73fd9ff3a5d015faf566adcebdc29bab2b2 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 7 Jun 2019 17:00:36 -0700 Subject: [PATCH 197/213] Update CHANGELOG --- CHANGELOG | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 149443c74..c1b548aeb 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -16,12 +16,10 @@ Yosys 0.8 .. Yosys 0.8-dev - Added "gate2lut.v" techmap rule - Added "rename -src" - Added "equiv_opt" pass -<<<<<<< HEAD - - Added "muxpack" pass -======= - Added "read_aiger" frontend ->>>>>>> origin/master + - Added "muxpack" pass - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx" + - "synth_xilinx" to now infer wide multiplexers Yosys 0.7 .. Yosys 0.8 From 9d8563178e930fe30bf4dd35b4a0306a1bd85d92 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 10 Jun 2019 14:34:12 -0700 Subject: [PATCH 198/213] Revert "shregmap -tech xilinx_static to handle INIT" This reverts commit 935df3569b4677ac38041ff01a2f67185681f4e3. --- passes/techmap/shregmap.cc | 54 ++++++++++++++++---------------------- 1 file changed, 22 insertions(+), 32 deletions(-) diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index e4c811cfb..3fe383b86 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -30,7 +30,7 @@ struct ShregmapTech virtual void non_chain_user(const SigBit &/*bit*/, const Cell* /*cell*/, IdString /*port*/) {} virtual bool analyze_first(const Cell* /*first_cell*/, const SigMap &/*sigmap*/) { return true; } virtual bool analyze(vector &taps, const vector &qbits) = 0; - virtual Cell* fixup(Cell *cell, const vector &taps, const vector &qbits) = 0; + virtual Cell* fixup(Cell *cell, dict &taps) = 0; }; struct ShregmapOptions @@ -72,7 +72,7 @@ struct ShregmapTechGreenpak4 : ShregmapTech return true; } - virtual Cell* fixup(Cell *cell, const vector &taps, const vector &qbits) override + virtual Cell* fixup(Cell *cell, dict &taps) override { auto D = cell->getPort("\\D"); auto C = cell->getPort("\\C"); @@ -84,8 +84,8 @@ struct ShregmapTechGreenpak4 : ShregmapTech int i = 0; for (auto tap : taps) { - newcell->setPort(i ? "\\OUTB" : "\\OUTA", qbits[tap]); - newcell->setParam(i ? "\\OUTB_TAP" : "\\OUTA_TAP", tap + 1); + newcell->setPort(i ? "\\OUTB" : "\\OUTA", tap.second); + newcell->setParam(i ? "\\OUTB_TAP" : "\\OUTA_TAP", tap.first + 1); i++; } @@ -96,21 +96,8 @@ struct ShregmapTechGreenpak4 : ShregmapTech struct ShregmapTechXilinx7Static : ShregmapTech { - dict sigbit_to_cell; const ShregmapOptions &opts; - virtual void init(const Module* module, const SigMap &sigmap) override - { - for (const auto &i : module->cells_) { - auto cell = i.second; - if (!cell->type.in("\\FDRE", "\\FDRE_1","\\FDSE", "\\FDSE_1", - "\\FDCE", "\\FDCE_1", "\\FDPE", "\\FDPE_1")) - continue; - - sigbit_to_cell[sigmap(cell->getPort("\\Q"))] = cell; - } - } - ShregmapTechXilinx7Static(const ShregmapOptions &opts) : opts(opts) {} virtual bool analyze_first(const Cell* first_cell, const SigMap &sigmap) override @@ -167,14 +154,15 @@ struct ShregmapTechXilinx7Static : ShregmapTech return GetSize(taps) == 1 && taps[0] >= opts.minlen-1; } - virtual Cell* fixup(Cell *cell, const vector &/*taps*/, const vector &qbits) override + virtual Cell* fixup(Cell *cell, dict &/*taps*/) override { auto newcell = cell->module->addCell(NEW_ID, "$__SHREG_"); newcell->set_src_attribute(cell->get_src_attribute()); newcell->setParam("\\DEPTH", cell->getParam("\\DEPTH")); + newcell->setParam("\\INIT", cell->getParam("\\INIT")); if (cell->type.in("$__SHREG_DFF_N_", "$__SHREG_DFF_P_", - "$__SHREG_DFFE_NN_", "$__SHREG_DFFE_NP_", "$__SHREG_DFFE_PN_", "$__SHREG_DFFE_PP_")) { + "$__SHREG_DFFE_NN_", "$__SHREG_DFFE_NP_", "$__SHREG_DFFE_PN_", "$__SHREG_DFFE_PP_")) { int param_clkpol = -1; int param_enpol = 2; if (cell->type == "$__SHREG_DFF_N_") param_clkpol = 0; @@ -188,7 +176,6 @@ struct ShregmapTechXilinx7Static : ShregmapTech log_assert(param_clkpol >= 0); newcell->setParam("\\CLKPOL", param_clkpol); newcell->setParam("\\ENPOL", param_enpol); - newcell->setParam("\\INIT", cell->getParam("\\INIT")); if (cell->hasPort("\\E")) newcell->setPort("\\E", cell->getPort("\\E")); @@ -200,12 +187,11 @@ struct ShregmapTechXilinx7Static : ShregmapTech param_clkpol = 0; newcell->setParam("\\CLKPOL", param_clkpol); newcell->setParam("\\ENPOL", 1); - log_assert(cell->getParam("\\INIT").is_fully_undef()); - SigSpec INIT; - for (auto q : qbits) { - Cell* reg = sigbit_to_cell.at(q); - INIT.append(SigBit(reg->getParam("\\INIT").as_bool())); - } + + newcell->setPort("\\E", cell->getPort("\\CE")); + } + else if (cell->type.in("$__SHREG_FDRE_1", "$__SHREG_FDSE_1", "$__SHREG_FDCE_1", "$__SHREG_FDPE_1")) { + newcell->setParam("\\CLKPOL", 0); newcell->setPort("\\E", cell->getPort("\\CE")); } @@ -328,14 +314,15 @@ struct ShregmapTechXilinx7Dynamic : ShregmapTechXilinx7Static return true; } - virtual Cell* fixup(Cell *cell, const vector &taps, const vector &qbits) override + virtual Cell* fixup(Cell *cell, dict &taps) override { - auto bit = qbits[taps.front()]; + const auto &tap = *taps.begin(); + auto bit = tap.second; auto it = sigbit_to_shiftx_offset.find(bit); log_assert(it != sigbit_to_shiftx_offset.end()); - Cell* newcell = ShregmapTechXilinx7Static::fixup(cell, taps, qbits); + Cell* newcell = ShregmapTechXilinx7Static::fixup(cell, taps); log_assert(newcell); log_assert(newcell->type == "$__SHREG_"); newcell->type = "$__XILINX_SHREG_"; @@ -506,8 +493,7 @@ struct ShregmapWorker Cell *first_cell = chain[cursor]; IdString q_port = opts.ffcells.at(first_cell->type).second; - vector qbits; - vector taps; + dict taps_dict; if (opts.tech) { @@ -516,6 +502,9 @@ struct ShregmapWorker continue; } + vector qbits; + vector taps; + for (int i = 0; i < depth; i++) { Cell *cell = chain[cursor+i]; @@ -540,6 +529,7 @@ struct ShregmapWorker depth = 0; for (auto tap : taps) { + taps_dict[tap] = qbits.at(tap); log_assert(depth < tap+1); depth = tap+1; } @@ -610,7 +600,7 @@ struct ShregmapWorker first_cell->setPort(q_port, last_cell->getPort(q_port)); first_cell->setParam("\\DEPTH", depth); - if (opts.tech != nullptr && opts.tech->fixup(first_cell, taps, qbits)) + if (opts.tech != nullptr && opts.tech->fixup(first_cell, taps_dict)) remove_cells.insert(first_cell); for (int i = 1; i < depth; i++) From e1dbeb3004873ae6914bd84e2020a34f8867477b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 10 Jun 2019 14:34:14 -0700 Subject: [PATCH 199/213] Revert "Continue support for ShregmapTechXilinx7Static" This reverts commit 72eda94a66c8c4938a713c9ae49d560e6b33574f. --- passes/techmap/shregmap.cc | 111 ++++++++++--------------------------- 1 file changed, 30 insertions(+), 81 deletions(-) diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index 3fe383b86..a1483fab5 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -28,9 +28,8 @@ struct ShregmapTech virtual ~ShregmapTech() { } virtual void init(const Module * /*module*/, const SigMap &/*sigmap*/) {} virtual void non_chain_user(const SigBit &/*bit*/, const Cell* /*cell*/, IdString /*port*/) {} - virtual bool analyze_first(const Cell* /*first_cell*/, const SigMap &/*sigmap*/) { return true; } virtual bool analyze(vector &taps, const vector &qbits) = 0; - virtual Cell* fixup(Cell *cell, dict &taps) = 0; + virtual RTLIL::Cell* fixup(Cell *cell, dict &taps) = 0; }; struct ShregmapOptions @@ -72,7 +71,7 @@ struct ShregmapTechGreenpak4 : ShregmapTech return true; } - virtual Cell* fixup(Cell *cell, dict &taps) override + virtual RTLIL::Cell* fixup(Cell *cell, dict &taps) override { auto D = cell->getPort("\\D"); auto C = cell->getPort("\\C"); @@ -100,61 +99,18 @@ struct ShregmapTechXilinx7Static : ShregmapTech ShregmapTechXilinx7Static(const ShregmapOptions &opts) : opts(opts) {} - virtual bool analyze_first(const Cell* first_cell, const SigMap &sigmap) override + virtual bool analyze(vector &taps, const vector &/*qbits*/) override { - if (first_cell->type.in("\\FDRE", "\\FDRE_1")) { - bool is_R_inverted = false; - if (first_cell->hasParam("\\IS_R_INVERTED")) - is_R_inverted = first_cell->getParam("\\IS_R_INVERTED").as_bool(); - SigBit R = sigmap(first_cell->getPort("\\R")); - if (R != RTLIL::S0 && R != RTLIL::S1) - return false; - if ((!is_R_inverted && R != RTLIL::S0) || (is_R_inverted && R != RTLIL::S1)) - return false; - return true; - } - if (first_cell->type.in("\\FDSE", "\\FDSE_1")) { - bool is_S_inverted = false; - if (first_cell->hasParam("\\IS_S_INVERTED")) - is_S_inverted = first_cell->getParam("\\IS_S_INVERTED").as_bool(); - SigBit S = sigmap(first_cell->getPort("\\S")); - if (S != RTLIL::S0 && S != RTLIL::S1) - return false; - if ((!is_S_inverted && S != RTLIL::S0) || (is_S_inverted && S != RTLIL::S1)) - return false; - return true; - } - if (first_cell->type.in("\\FDCE", "\\FDCE_1")) { - bool is_CLR_inverted = false; - if (first_cell->hasParam("\\IS_CLR_INVERTED")) - is_CLR_inverted = first_cell->getParam("\\IS_CLR_INVERTED").as_bool(); - SigBit CLR = sigmap(first_cell->getPort("\\CLR")); - if (CLR != RTLIL::S0 && CLR != RTLIL::S1) - return false; - if ((!is_CLR_inverted && CLR != RTLIL::S0) || (is_CLR_inverted && CLR != RTLIL::S1)) - return false; - return true; - } - if (first_cell->type.in("\\FDPE", "\\FDPE_1")) { - bool is_PRE_inverted = false; - if (first_cell->hasParam("\\IS_PRE_INVERTED")) - is_PRE_inverted = first_cell->getParam("\\IS_PRE_INVERTED").as_bool(); - SigBit PRE = sigmap(first_cell->getPort("\\PRE")); - if (PRE != RTLIL::S0 && PRE != RTLIL::S1) - return false; - if ((!is_PRE_inverted && PRE != RTLIL::S0) || (is_PRE_inverted && PRE != RTLIL::S1)) - return false; - return true; - } + if (GetSize(taps) == 1) + return taps[0] >= opts.minlen-1; + + if (taps.back() < opts.minlen-1) + return false; + return true; } - virtual bool analyze(vector &taps, const vector &/*qbits*/) override - { - return GetSize(taps) == 1 && taps[0] >= opts.minlen-1; - } - - virtual Cell* fixup(Cell *cell, dict &/*taps*/) override + virtual RTLIL::Cell* fixup(Cell *cell, dict &/*taps*/) override { auto newcell = cell->module->addCell(NEW_ID, "$__SHREG_"); newcell->set_src_attribute(cell->get_src_attribute()); @@ -180,17 +136,16 @@ struct ShregmapTechXilinx7Static : ShregmapTech if (cell->hasPort("\\E")) newcell->setPort("\\E", cell->getPort("\\E")); } - else if (cell->type.in("$__SHREG_FDRE", "$__SHREG_FDRE_1","$__SHREG_FDSE", "$__SHREG_FDSE_1", - "$__SHREG_FDCE", "$__SHREG_FDCE_1", "$__SHREG_FDPE", "$__SHREG_FDPE_1")) { - int param_clkpol = 1; - if (cell->hasParam("\\IS_C_INVERTED") && cell->getParam("\\IS_C_INVERTED").as_bool()) - param_clkpol = 0; - newcell->setParam("\\CLKPOL", param_clkpol); + else if (cell->type.in("$__SHREG_FDRE_", "$__SHREG_FDSE_", "$__SHREG_FDCE_", "$__SHREG_FDPE_")) { + if (cell->getParam("\\IS_C_INVERTED").as_bool()) + newcell->setParam("\\CLKPOL", 0); + else + newcell->setParam("\\CLKPOL", 1); newcell->setParam("\\ENPOL", 1); newcell->setPort("\\E", cell->getPort("\\CE")); } - else if (cell->type.in("$__SHREG_FDRE_1", "$__SHREG_FDSE_1", "$__SHREG_FDCE_1", "$__SHREG_FDPE_1")) { + else if (cell->type.in("$__SHREG_FDRE_1_", "$__SHREG_FDSE_1_", "$__SHREG_FDCE_1_", "$__SHREG_FDPE_1_")) { newcell->setParam("\\CLKPOL", 0); newcell->setPort("\\E", cell->getPort("\\CE")); @@ -260,14 +215,13 @@ struct ShregmapTechXilinx7Dynamic : ShregmapTechXilinx7Static Cell *shiftx = nullptr; int group = 0; for (int i = 0; i < GetSize(taps); ++i) { - // Check taps are sequential - if (i != taps[i]) - return false; - auto it = sigbit_to_shiftx_offset.find(qbits[i]); if (it == sigbit_to_shiftx_offset.end()) return false; + // Check taps are sequential + if (i != taps[i]) + return false; // Check taps are not connected to a shift register, // or sequential to the same shift register if (i == 0) { @@ -314,7 +268,7 @@ struct ShregmapTechXilinx7Dynamic : ShregmapTechXilinx7Static return true; } - virtual Cell* fixup(Cell *cell, dict &taps) override + virtual RTLIL::Cell* fixup(Cell *cell, dict &taps) override { const auto &tap = *taps.begin(); auto bit = tap.second; @@ -322,7 +276,7 @@ struct ShregmapTechXilinx7Dynamic : ShregmapTechXilinx7Static auto it = sigbit_to_shiftx_offset.find(bit); log_assert(it != sigbit_to_shiftx_offset.end()); - Cell* newcell = ShregmapTechXilinx7Static::fixup(cell, taps); + RTLIL::Cell* newcell = ShregmapTechXilinx7Static::fixup(cell, taps); log_assert(newcell); log_assert(newcell->type == "$__SHREG_"); newcell->type = "$__XILINX_SHREG_"; @@ -497,11 +451,6 @@ struct ShregmapWorker if (opts.tech) { - if (!opts.tech->analyze_first(first_cell, sigmap)) { - cursor += depth; - continue; - } - vector qbits; vector taps; @@ -778,16 +727,16 @@ struct ShregmapPass : public Pass { opts.ffcells["$_DFFE_PN_"] = make_pair(IdString("\\D"), IdString("\\Q")); opts.ffcells["$_DFFE_NP_"] = make_pair(IdString("\\D"), IdString("\\Q")); opts.ffcells["$_DFFE_NN_"] = make_pair(IdString("\\D"), IdString("\\Q")); - opts.ffcells["\\FDRE"] = make_pair(IdString("\\D"), IdString("\\Q")); - opts.ffcells["\\FDRE_1"] = make_pair(IdString("\\D"), IdString("\\Q")); - opts.ffcells["\\FDSE"] = make_pair(IdString("\\D"), IdString("\\Q")); - opts.ffcells["\\FDSE_1"] = make_pair(IdString("\\D"), IdString("\\Q")); - opts.ffcells["\\FDCE"] = make_pair(IdString("\\D"), IdString("\\Q")); - opts.ffcells["\\FDCE_1"] = make_pair(IdString("\\D"), IdString("\\Q")); - opts.ffcells["\\FDPE"] = make_pair(IdString("\\D"), IdString("\\Q")); - opts.ffcells["\\FDPE_1"] = make_pair(IdString("\\D"), IdString("\\Q")); + opts.ffcells["FDRE"] = make_pair(IdString("\\D"), IdString("\\Q")); + opts.ffcells["FDRE_1"] = make_pair(IdString("\\D"), IdString("\\Q")); + opts.ffcells["FDSE"] = make_pair(IdString("\\D"), IdString("\\Q")); + opts.ffcells["FDSE_1"] = make_pair(IdString("\\D"), IdString("\\Q")); + opts.ffcells["FDCE"] = make_pair(IdString("\\D"), IdString("\\Q")); + opts.ffcells["FDCE_1"] = make_pair(IdString("\\D"), IdString("\\Q")); + opts.ffcells["FDPE"] = make_pair(IdString("\\D"), IdString("\\Q")); + opts.ffcells["FDPE_1"] = make_pair(IdString("\\D"), IdString("\\Q")); if (tech == "xilinx_static") - opts.tech = new ShregmapTechXilinx7Static(opts); + opts.tech = new ShregmapTechXilinx7Dynamic(opts); else if (tech == "xilinx_dynamic") opts.tech = new ShregmapTechXilinx7Dynamic(opts); } else { From b6a39351f4e82ee00f95d3168fe26a62090166b2 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 10 Jun 2019 14:34:14 -0700 Subject: [PATCH 200/213] Revert "Add -tech xilinx_static" This reverts commit dfe9d95579ab98d7518d40e427af858243de4eb3. --- passes/techmap/shregmap.cc | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index a1483fab5..c8971170a 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -719,7 +719,7 @@ struct ShregmapPass : public Pass { opts.zinit = true; opts.tech = new ShregmapTechGreenpak4; } - else if (tech == "xilinx_static" || tech == "xilinx_dynamic") { + else if (tech == "xilinx_dynamic") { opts.init = true; opts.ffcells["$_DFF_P_"] = make_pair(IdString("\\D"), IdString("\\Q")); opts.ffcells["$_DFF_N_"] = make_pair(IdString("\\D"), IdString("\\Q")); @@ -727,18 +727,7 @@ struct ShregmapPass : public Pass { opts.ffcells["$_DFFE_PN_"] = make_pair(IdString("\\D"), IdString("\\Q")); opts.ffcells["$_DFFE_NP_"] = make_pair(IdString("\\D"), IdString("\\Q")); opts.ffcells["$_DFFE_NN_"] = make_pair(IdString("\\D"), IdString("\\Q")); - opts.ffcells["FDRE"] = make_pair(IdString("\\D"), IdString("\\Q")); - opts.ffcells["FDRE_1"] = make_pair(IdString("\\D"), IdString("\\Q")); - opts.ffcells["FDSE"] = make_pair(IdString("\\D"), IdString("\\Q")); - opts.ffcells["FDSE_1"] = make_pair(IdString("\\D"), IdString("\\Q")); - opts.ffcells["FDCE"] = make_pair(IdString("\\D"), IdString("\\Q")); - opts.ffcells["FDCE_1"] = make_pair(IdString("\\D"), IdString("\\Q")); - opts.ffcells["FDPE"] = make_pair(IdString("\\D"), IdString("\\Q")); - opts.ffcells["FDPE_1"] = make_pair(IdString("\\D"), IdString("\\Q")); - if (tech == "xilinx_static") - opts.tech = new ShregmapTechXilinx7Dynamic(opts); - else if (tech == "xilinx_dynamic") - opts.tech = new ShregmapTechXilinx7Dynamic(opts); + opts.tech = new ShregmapTechXilinx7Dynamic(opts); } else { argidx--; break; From 3579d681935da5bb03876d0d562e5f4b556feabe Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 10 Jun 2019 14:34:15 -0700 Subject: [PATCH 201/213] Revert "Refactor to ShregmapTechXilinx7Static" This reverts commit e1e37db86073e545269ff440da77f57135e8b155. --- passes/techmap/shregmap.cc | 140 +++++++++++++------------------------ 1 file changed, 50 insertions(+), 90 deletions(-) diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index c8971170a..91a942c39 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -29,7 +29,7 @@ struct ShregmapTech virtual void init(const Module * /*module*/, const SigMap &/*sigmap*/) {} virtual void non_chain_user(const SigBit &/*bit*/, const Cell* /*cell*/, IdString /*port*/) {} virtual bool analyze(vector &taps, const vector &qbits) = 0; - virtual RTLIL::Cell* fixup(Cell *cell, dict &taps) = 0; + virtual bool fixup(Cell *cell, dict &taps) = 0; }; struct ShregmapOptions @@ -71,7 +71,7 @@ struct ShregmapTechGreenpak4 : ShregmapTech return true; } - virtual RTLIL::Cell* fixup(Cell *cell, dict &taps) override + virtual bool fixup(Cell *cell, dict &taps) override { auto D = cell->getPort("\\D"); auto C = cell->getPort("\\C"); @@ -89,84 +89,16 @@ struct ShregmapTechGreenpak4 : ShregmapTech } cell->setParam("\\OUTA_INVERT", 0); - return newcell; + return false; } }; -struct ShregmapTechXilinx7Static : ShregmapTech -{ - const ShregmapOptions &opts; - - ShregmapTechXilinx7Static(const ShregmapOptions &opts) : opts(opts) {} - - virtual bool analyze(vector &taps, const vector &/*qbits*/) override - { - if (GetSize(taps) == 1) - return taps[0] >= opts.minlen-1; - - if (taps.back() < opts.minlen-1) - return false; - - return true; - } - - virtual RTLIL::Cell* fixup(Cell *cell, dict &/*taps*/) override - { - auto newcell = cell->module->addCell(NEW_ID, "$__SHREG_"); - newcell->set_src_attribute(cell->get_src_attribute()); - newcell->setParam("\\DEPTH", cell->getParam("\\DEPTH")); - newcell->setParam("\\INIT", cell->getParam("\\INIT")); - - if (cell->type.in("$__SHREG_DFF_N_", "$__SHREG_DFF_P_", - "$__SHREG_DFFE_NN_", "$__SHREG_DFFE_NP_", "$__SHREG_DFFE_PN_", "$__SHREG_DFFE_PP_")) { - int param_clkpol = -1; - int param_enpol = 2; - if (cell->type == "$__SHREG_DFF_N_") param_clkpol = 0; - else if (cell->type == "$__SHREG_DFF_P_") param_clkpol = 1; - else if (cell->type == "$__SHREG_DFFE_NN_") param_clkpol = 0, param_enpol = 0; - else if (cell->type == "$__SHREG_DFFE_NP_") param_clkpol = 0, param_enpol = 1; - else if (cell->type == "$__SHREG_DFFE_PN_") param_clkpol = 1, param_enpol = 0; - else if (cell->type == "$__SHREG_DFFE_PP_") param_clkpol = 1, param_enpol = 1; - else log_abort(); - - log_assert(param_clkpol >= 0); - newcell->setParam("\\CLKPOL", param_clkpol); - newcell->setParam("\\ENPOL", param_enpol); - - if (cell->hasPort("\\E")) - newcell->setPort("\\E", cell->getPort("\\E")); - } - else if (cell->type.in("$__SHREG_FDRE_", "$__SHREG_FDSE_", "$__SHREG_FDCE_", "$__SHREG_FDPE_")) { - if (cell->getParam("\\IS_C_INVERTED").as_bool()) - newcell->setParam("\\CLKPOL", 0); - else - newcell->setParam("\\CLKPOL", 1); - newcell->setParam("\\ENPOL", 1); - - newcell->setPort("\\E", cell->getPort("\\CE")); - } - else if (cell->type.in("$__SHREG_FDRE_1_", "$__SHREG_FDSE_1_", "$__SHREG_FDCE_1_", "$__SHREG_FDPE_1_")) { - newcell->setParam("\\CLKPOL", 0); - - newcell->setPort("\\E", cell->getPort("\\CE")); - } - else log_abort(); - - newcell->setParam("\\ENPOL", 1); - - newcell->setPort("\\C", cell->getPort("\\C")); - newcell->setPort("\\D", cell->getPort("\\D")); - newcell->setPort("\\Q", cell->getPort("\\Q")); - - return newcell; - } -}; - -struct ShregmapTechXilinx7Dynamic : ShregmapTechXilinx7Static +struct ShregmapTechXilinx7Dynamic : ShregmapTech { dict> sigbit_to_shiftx_offset; + const ShregmapOptions &opts; - ShregmapTechXilinx7Dynamic(const ShregmapOptions &opts) : ShregmapTechXilinx7Static(opts) {} + ShregmapTechXilinx7Dynamic(const ShregmapOptions &opts) : opts(opts) {} virtual void init(const Module* module, const SigMap &sigmap) override { @@ -268,7 +200,7 @@ struct ShregmapTechXilinx7Dynamic : ShregmapTechXilinx7Static return true; } - virtual RTLIL::Cell* fixup(Cell *cell, dict &taps) override + virtual bool fixup(Cell *cell, dict &taps) override { const auto &tap = *taps.begin(); auto bit = tap.second; @@ -276,24 +208,52 @@ struct ShregmapTechXilinx7Dynamic : ShregmapTechXilinx7Static auto it = sigbit_to_shiftx_offset.find(bit); log_assert(it != sigbit_to_shiftx_offset.end()); - RTLIL::Cell* newcell = ShregmapTechXilinx7Static::fixup(cell, taps); - log_assert(newcell); - log_assert(newcell->type == "$__SHREG_"); - newcell->type = "$__XILINX_SHREG_"; + auto newcell = cell->module->addCell(NEW_ID, "$__XILINX_SHREG_"); + newcell->set_src_attribute(cell->get_src_attribute()); + newcell->setParam("\\DEPTH", cell->getParam("\\DEPTH")); + newcell->setParam("\\INIT", cell->getParam("\\INIT")); - Cell* shiftx = std::get<0>(it->second); - RTLIL::SigSpec l_wire; - if (shiftx->type == "$shiftx") - l_wire = shiftx->getPort("\\B"); - else if (shiftx->type == "$mux") - l_wire = shiftx->getPort("\\S"); + if (cell->type.in("$__SHREG_DFF_N_", "$__SHREG_DFF_P_", + "$__SHREG_DFFE_NN_", "$__SHREG_DFFE_NP_", "$__SHREG_DFFE_PN_", "$__SHREG_DFFE_PP_")) { + int param_clkpol = -1; + int param_enpol = 2; + if (cell->type == "$__SHREG_DFF_N_") param_clkpol = 0; + else if (cell->type == "$__SHREG_DFF_P_") param_clkpol = 1; + else if (cell->type == "$__SHREG_DFFE_NN_") param_clkpol = 0, param_enpol = 0; + else if (cell->type == "$__SHREG_DFFE_NP_") param_clkpol = 0, param_enpol = 1; + else if (cell->type == "$__SHREG_DFFE_PN_") param_clkpol = 1, param_enpol = 0; + else if (cell->type == "$__SHREG_DFFE_PP_") param_clkpol = 1, param_enpol = 1; + else log_abort(); + + log_assert(param_clkpol >= 0); + cell->setParam("\\CLKPOL", param_clkpol); + cell->setParam("\\ENPOL", param_enpol); + } else log_abort(); - newcell->setPort("\\L", l_wire); - newcell->setPort("\\Q", shiftx->getPort("\\Y")); - shiftx->setPort("\\Y", cell->module->addWire(NEW_ID)); + newcell->setPort("\\C", cell->getPort("\\C")); + newcell->setPort("\\D", cell->getPort("\\D")); + if (cell->hasPort("\\E")) + newcell->setPort("\\E", cell->getPort("\\E")); - return newcell; + Cell* shiftx = std::get<0>(it->second); + RTLIL::SigSpec l_wire, q_wire; + if (shiftx->type == "$shiftx") { + l_wire = shiftx->getPort("\\B"); + q_wire = shiftx->getPort("\\Y"); + shiftx->setPort("\\Y", cell->module->addWire(NEW_ID)); + } + else if (shiftx->type == "$mux") { + l_wire = shiftx->getPort("\\S"); + q_wire = shiftx->getPort("\\Y"); + shiftx->setPort("\\Y", cell->module->addWire(NEW_ID)); + } + else log_abort(); + + newcell->setPort("\\Q", q_wire); + newcell->setPort("\\L", l_wire); + + return false; } }; @@ -549,7 +509,7 @@ struct ShregmapWorker first_cell->setPort(q_port, last_cell->getPort(q_port)); first_cell->setParam("\\DEPTH", depth); - if (opts.tech != nullptr && opts.tech->fixup(first_cell, taps_dict)) + if (opts.tech != nullptr && !opts.tech->fixup(first_cell, taps_dict)) remove_cells.insert(first_cell); for (int i = 1; i < depth; i++) From 7d27e1e4312499b72d253470c97cfbf98e4c9d8e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 10 Jun 2019 14:34:16 -0700 Subject: [PATCH 202/213] Revert "shregmap -tech xilinx_dynamic to work -params and -enpol" This reverts commit 45d1bdf83ae6d51628e917b66f1b6043c8a3baee. --- passes/techmap/shregmap.cc | 32 ++++++-------------------------- 1 file changed, 6 insertions(+), 26 deletions(-) diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index 91a942c39..60b04be6f 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -56,7 +56,7 @@ struct ShregmapOptions struct ShregmapTechGreenpak4 : ShregmapTech { - virtual bool analyze(vector &taps, const vector &/*qbits*/) override + bool analyze(vector &taps, const vector &/*qbits*/) { if (GetSize(taps) > 2 && taps[0] == 0 && taps[2] < 17) { taps.clear(); @@ -71,7 +71,7 @@ struct ShregmapTechGreenpak4 : ShregmapTech return true; } - virtual bool fixup(Cell *cell, dict &taps) override + bool fixup(Cell *cell, dict &taps) { auto D = cell->getPort("\\D"); auto C = cell->getPort("\\C"); @@ -212,24 +212,8 @@ struct ShregmapTechXilinx7Dynamic : ShregmapTech newcell->set_src_attribute(cell->get_src_attribute()); newcell->setParam("\\DEPTH", cell->getParam("\\DEPTH")); newcell->setParam("\\INIT", cell->getParam("\\INIT")); - - if (cell->type.in("$__SHREG_DFF_N_", "$__SHREG_DFF_P_", - "$__SHREG_DFFE_NN_", "$__SHREG_DFFE_NP_", "$__SHREG_DFFE_PN_", "$__SHREG_DFFE_PP_")) { - int param_clkpol = -1; - int param_enpol = 2; - if (cell->type == "$__SHREG_DFF_N_") param_clkpol = 0; - else if (cell->type == "$__SHREG_DFF_P_") param_clkpol = 1; - else if (cell->type == "$__SHREG_DFFE_NN_") param_clkpol = 0, param_enpol = 0; - else if (cell->type == "$__SHREG_DFFE_NP_") param_clkpol = 0, param_enpol = 1; - else if (cell->type == "$__SHREG_DFFE_PN_") param_clkpol = 1, param_enpol = 0; - else if (cell->type == "$__SHREG_DFFE_PP_") param_clkpol = 1, param_enpol = 1; - else log_abort(); - - log_assert(param_clkpol >= 0); - cell->setParam("\\CLKPOL", param_clkpol); - cell->setParam("\\ENPOL", param_enpol); - } - else log_abort(); + newcell->setParam("\\CLKPOL", cell->getParam("\\CLKPOL")); + newcell->setParam("\\ENPOL", cell->getParam("\\ENPOL")); newcell->setPort("\\C", cell->getPort("\\C")); newcell->setPort("\\D", cell->getPort("\\D")); @@ -681,12 +665,8 @@ struct ShregmapPass : public Pass { } else if (tech == "xilinx_dynamic") { opts.init = true; - opts.ffcells["$_DFF_P_"] = make_pair(IdString("\\D"), IdString("\\Q")); - opts.ffcells["$_DFF_N_"] = make_pair(IdString("\\D"), IdString("\\Q")); - opts.ffcells["$_DFFE_PP_"] = make_pair(IdString("\\D"), IdString("\\Q")); - opts.ffcells["$_DFFE_PN_"] = make_pair(IdString("\\D"), IdString("\\Q")); - opts.ffcells["$_DFFE_NP_"] = make_pair(IdString("\\D"), IdString("\\Q")); - opts.ffcells["$_DFFE_NN_"] = make_pair(IdString("\\D"), IdString("\\Q")); + opts.params = true; + enpol = "any_or_none"; opts.tech = new ShregmapTechXilinx7Dynamic(opts); } else { argidx--; From a1d4ae78a0ee474af6782bc5e12d8bd1fc790f04 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 10 Jun 2019 14:34:43 -0700 Subject: [PATCH 203/213] Revert "Rename shregmap -tech xilinx -> xilinx_dynamic" This reverts commit 94a5f4e60985fc1e3fea75eec85638fa29874bea. --- passes/techmap/shregmap.cc | 8 ++++---- techlibs/xilinx/synth_xilinx.cc | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index 60b04be6f..21dfe9619 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -93,12 +93,12 @@ struct ShregmapTechGreenpak4 : ShregmapTech } }; -struct ShregmapTechXilinx7Dynamic : ShregmapTech +struct ShregmapTechXilinx7 : ShregmapTech { dict> sigbit_to_shiftx_offset; const ShregmapOptions &opts; - ShregmapTechXilinx7Dynamic(const ShregmapOptions &opts) : opts(opts) {} + ShregmapTechXilinx7(const ShregmapOptions &opts) : opts(opts) {} virtual void init(const Module* module, const SigMap &sigmap) override { @@ -663,11 +663,11 @@ struct ShregmapPass : public Pass { opts.zinit = true; opts.tech = new ShregmapTechGreenpak4; } - else if (tech == "xilinx_dynamic") { + else if (tech == "xilinx") { opts.init = true; opts.params = true; enpol = "any_or_none"; - opts.tech = new ShregmapTechXilinx7Dynamic(opts); + opts.tech = new ShregmapTechXilinx7(opts); } else { argidx--; break; diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index ffdb22960..689a40135 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -266,8 +266,8 @@ struct SynthXilinxPass : public ScriptPass // shregmap operates on bit-level flops, not word-level, // so break those down here run("simplemap t:$dff t:$dffe", "(skip if '-nosrl')"); - // shregmap to infer variable length shift regs - run("shregmap -tech xilinx_dynamic -minlen 3", "(skip if '-nosrl')"); + // shregmap with '-tech xilinx' infers variable length shift regs + run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')"); } std::string techmap_files = " -map +/techmap.v"; From b77c5da76919f7f99f171a0a2775896fbc8debc2 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 10 Jun 2019 14:37:09 -0700 Subject: [PATCH 204/213] Revert "Revert "Move ff_map back after ABC for shregmap"" This reverts commit e473e7456545d702c011ee7872956f94a8522865. --- techlibs/xilinx/synth_xilinx.cc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 689a40135..f5f8c43e0 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -291,9 +291,7 @@ struct SynthXilinxPass : public ScriptPass if (check_label("map_cells")) { if (!nomux || help_mode) run("muxcover -mux8 -mux16", "(skip if '-nomux')"); - run("techmap -map +/techmap.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v"); - run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " - "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT"); + run("techmap -map +/techmap.v -map +/xilinx/cells_map.v"); run("clean"); } @@ -309,8 +307,10 @@ struct SynthXilinxPass : public ScriptPass // This shregmap call infers fixed length shift registers after abc // has performed any necessary retiming if (!nosrl || help_mode) - run("shregmap -tech xilinx_static -minlen 3", "(skip if '-nosrl')"); - run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v"); + run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')"); + run("techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v -map +/xilinx/ff_map.v"); + run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT " + "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT"); run("clean"); } From c314ca3c51579a9c5305cbf9a69635e123db0423 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 10 Jun 2019 16:16:26 -0700 Subject: [PATCH 205/213] Add test --- tests/various/shregmap.v | 22 ++++++++++++++++++++++ tests/various/shregmap.ys | 31 +++++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+) create mode 100644 tests/various/shregmap.v create mode 100644 tests/various/shregmap.ys diff --git a/tests/various/shregmap.v b/tests/various/shregmap.v new file mode 100644 index 000000000..56e05c2c0 --- /dev/null +++ b/tests/various/shregmap.v @@ -0,0 +1,22 @@ +module shregmap_test(input i, clk, output [1:0] q); +reg head = 1'b0; +reg [3:0] shift1 = 4'b0000; +reg [3:0] shift2 = 4'b0000; + +always @(posedge clk) begin + head <= i; + shift1 <= {shift1[2:0], head}; + shift2 <= {shift2[2:0], head}; +end + +assign q = {shift2[3], shift1[3]}; +endmodule + +module $__SHREG_DFF_P_(input C, D, output Q); +parameter DEPTH = 1; +parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}}; +reg [DEPTH-1:0] r = INIT; +always @(posedge C) + r <= { r[DEPTH-2:0], D }; +assign Q = r[DEPTH-1]; +endmodule diff --git a/tests/various/shregmap.ys b/tests/various/shregmap.ys new file mode 100644 index 000000000..ca7f47015 --- /dev/null +++ b/tests/various/shregmap.ys @@ -0,0 +1,31 @@ +read_verilog shregmap.v +design -copy-to model $__SHREG_DFF_P_ +hierarchy -top shregmap_test +prep +design -save gold + +techmap +shregmap -init + +opt + +stat +# show -width +select -assert-count 1 t:$_DFF_P_ +select -assert-count 2 t:$__SHREG_DFF_P_ + +design -stash gate + +design -import gold -as gold +design -import gate -as gate +design -copy-from model -as $__SHREG_DFF_P_ \$__SHREG_DFF_P_ +prep + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports -seq 5 miter + +design -load gold +stat + +design -load gate +stat From f19aa8d989df9e443d26cf6beaf389c2f3d6a424 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 10 Jun 2019 16:16:40 -0700 Subject: [PATCH 206/213] If d_bit already in sigbit_chain_next, create extra wire --- passes/techmap/shregmap.cc | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index 21dfe9619..46f6a79fb 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -293,10 +293,13 @@ struct ShregmapWorker if (opts.init || sigbit_init.count(q_bit) == 0) { - if (sigbit_chain_next.count(d_bit)) { + auto r = sigbit_chain_next.insert(std::make_pair(d_bit, cell)); + if (!r.second) { sigbit_with_non_chain_users.insert(d_bit); - } else - sigbit_chain_next[d_bit] = cell; + Wire *wire = module->addWire(NEW_ID); + module->connect(wire, d_bit); + sigbit_chain_next.insert(std::make_pair(wire, cell)); + } sigbit_chain_prev[q_bit] = cell; continue; From 8a708d1fdb662f86a46720200fa15acafde30333 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 11 Jun 2019 12:02:31 -0700 Subject: [PATCH 207/213] Remove #ifndef ABC --- techlibs/xilinx/cells_sim.v | 4 ---- 1 file changed, 4 deletions(-) diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 88967b068..14e35737e 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -295,10 +295,8 @@ module RAM64X1D ( reg [63:0] mem = INIT; assign SPO = mem[a]; assign DPO = mem[dpra]; -`ifndef _ABC wire clk = WCLK ^ IS_WCLK_INVERTED; always @(posedge clk) if (WE) mem[a] <= D; -`endif endmodule (* abc_box_id = 5 /*, lib_whitebox*/ *) @@ -312,10 +310,8 @@ module RAM128X1D ( reg [127:0] mem = INIT; assign SPO = mem[A]; assign DPO = mem[DPRA]; -`ifndef _ABC wire clk = WCLK ^ IS_WCLK_INVERTED; always @(posedge clk) if (WE) mem[A] <= D; -`endif endmodule module SRL16E ( From 54379f9872ba3abdf5328994abcf5abfc7288c6b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 11 Jun 2019 12:02:51 -0700 Subject: [PATCH 208/213] Disable dist RAM boxes due to comb loop --- techlibs/xilinx/cells_sim.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 14e35737e..d9aa36666 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -281,7 +281,7 @@ module FDPE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, PRE); always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; endmodule -(* abc_box_id = 4 /*, lib_whitebox*/ *) +//(* abc_box_id = 4 /*, lib_whitebox*/ *) module RAM64X1D ( output DPO, SPO, input D, WCLK, WE, @@ -299,7 +299,7 @@ module RAM64X1D ( always @(posedge clk) if (WE) mem[a] <= D; endmodule -(* abc_box_id = 5 /*, lib_whitebox*/ *) +//(* abc_box_id = 5 /*, lib_whitebox*/ *) module RAM128X1D ( output DPO, SPO, input D, WCLK, WE, From 2f427acc9ed23c77e89386f4fbf53ac580bf0f0b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 11 Jun 2019 15:48:20 -0700 Subject: [PATCH 209/213] Try way that doesn't involve creating a new wire --- passes/techmap/shregmap.cc | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index 46f6a79fb..3adcd8968 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -294,12 +294,8 @@ struct ShregmapWorker if (opts.init || sigbit_init.count(q_bit) == 0) { auto r = sigbit_chain_next.insert(std::make_pair(d_bit, cell)); - if (!r.second) { + if (!r.second) sigbit_with_non_chain_users.insert(d_bit); - Wire *wire = module->addWire(NEW_ID); - module->connect(wire, d_bit); - sigbit_chain_next.insert(std::make_pair(wire, cell)); - } sigbit_chain_prev[q_bit] = cell; continue; @@ -319,14 +315,14 @@ struct ShregmapWorker { for (auto it : sigbit_chain_next) { + Cell *c1, *c2 = it.second; + if (opts.tech == nullptr && sigbit_with_non_chain_users.count(it.first)) goto start_cell; - if (sigbit_chain_prev.count(it.first) != 0) + c1 = sigbit_chain_prev.at(it.first, nullptr); + if (c1 != nullptr) { - Cell *c1 = sigbit_chain_prev.at(it.first); - Cell *c2 = it.second; - if (c1->type != c2->type) goto start_cell; @@ -336,6 +332,15 @@ struct ShregmapWorker IdString d_port = opts.ffcells.at(c1->type).first; IdString q_port = opts.ffcells.at(c1->type).second; + // If the previous cell's D has other non chain users, + // then it is possible that this previous cell could + // be a start of the chain + SigBit d_bit = sigmap(c1->getPort(d_port).as_bit()); + if (sigbit_with_non_chain_users.count(d_bit)) { + c2 = c1; + goto start_cell; + } + auto c1_conn = c1->connections(); auto c2_conn = c1->connections(); @@ -352,7 +357,7 @@ struct ShregmapWorker } start_cell: - chain_start_cells.insert(it.second); + chain_start_cells.insert(c2); } } From d26646051c4ae9740decd5d76eec6a3afd63844a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 11 Jun 2019 16:05:27 -0700 Subject: [PATCH 210/213] Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux" This reverts commit 5174082208ef9bea22ad1ba62622947375b3e83b, reversing changes made to 54379f9872ba3abdf5328994abcf5abfc7288c6b. --- passes/techmap/shregmap.cc | 25 ++++++++++--------------- 1 file changed, 10 insertions(+), 15 deletions(-) diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index 3adcd8968..46f6a79fb 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -294,8 +294,12 @@ struct ShregmapWorker if (opts.init || sigbit_init.count(q_bit) == 0) { auto r = sigbit_chain_next.insert(std::make_pair(d_bit, cell)); - if (!r.second) + if (!r.second) { sigbit_with_non_chain_users.insert(d_bit); + Wire *wire = module->addWire(NEW_ID); + module->connect(wire, d_bit); + sigbit_chain_next.insert(std::make_pair(wire, cell)); + } sigbit_chain_prev[q_bit] = cell; continue; @@ -315,14 +319,14 @@ struct ShregmapWorker { for (auto it : sigbit_chain_next) { - Cell *c1, *c2 = it.second; - if (opts.tech == nullptr && sigbit_with_non_chain_users.count(it.first)) goto start_cell; - c1 = sigbit_chain_prev.at(it.first, nullptr); - if (c1 != nullptr) + if (sigbit_chain_prev.count(it.first) != 0) { + Cell *c1 = sigbit_chain_prev.at(it.first); + Cell *c2 = it.second; + if (c1->type != c2->type) goto start_cell; @@ -332,15 +336,6 @@ struct ShregmapWorker IdString d_port = opts.ffcells.at(c1->type).first; IdString q_port = opts.ffcells.at(c1->type).second; - // If the previous cell's D has other non chain users, - // then it is possible that this previous cell could - // be a start of the chain - SigBit d_bit = sigmap(c1->getPort(d_port).as_bit()); - if (sigbit_with_non_chain_users.count(d_bit)) { - c2 = c1; - goto start_cell; - } - auto c1_conn = c1->connections(); auto c2_conn = c1->connections(); @@ -357,7 +352,7 @@ struct ShregmapWorker } start_cell: - chain_start_cells.insert(c2); + chain_start_cells.insert(it.second); } } From 2dffa4685b830313204f5d04314a14ed6ecac8ec Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 11 Jun 2019 17:10:47 -0700 Subject: [PATCH 211/213] Add "-W' wire delay arg to abc9, use from synth_xilinx --- frontends/verilog/verilog_lexer.l | 5 ----- passes/techmap/abc9.cc | 18 +++++++++++++----- techlibs/xilinx/synth_xilinx.cc | 2 +- 3 files changed, 14 insertions(+), 11 deletions(-) diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 3c612472d..9558bbfb9 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -311,11 +311,6 @@ supply1 { return TOK_SUPPLY1; } return TOK_ID; } -"$"(info|warning|error|fatal) { - frontend_verilog_yylval.string = new std::string(yytext); - return TOK_ELAB_TASK; -} - "$signed" { return TOK_TO_SIGNED; } "$unsigned" { return TOK_TO_UNSIGNED; } diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index af9439e41..19157adc6 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -25,7 +25,7 @@ #define ABC_COMMAND_LIB "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put" #define ABC_COMMAND_CTR "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put; buffer; upsize {D}; dnsize {D}; stime -p" //#define ABC_COMMAND_LUT "strash; ifraig; scorr; dc2; dretime; strash; dch -f; if; mfs2" -#define ABC_COMMAND_LUT "&st; &sweep; &scorr; "/*"&dc2; */"&retime; &dch -f; &ps -l; &if -W 160 -v; &ps -l" +#define ABC_COMMAND_LUT "&st; &sweep; &scorr; "/*"&dc2; */"&retime; &dch -f; &ps -l; &if {W} -v; &ps -l" #define ABC_COMMAND_SOP "strash; ifraig; scorr; dc2; dretime; strash; dch -f; cover {I} {P}" #define ABC_COMMAND_DFL "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put" @@ -272,7 +272,8 @@ failed: void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file, std::string liberty_file, std::string constr_file, bool cleanup, vector lut_costs, bool dff_mode, std::string clk_str, bool keepff, std::string delay_target, std::string sop_inputs, std::string sop_products, std::string lutin_shared, bool fast_mode, - const std::vector &cells, bool show_tempdir, bool sop_mode, std::string box_file, std::string lut_file) + const std::vector &cells, bool show_tempdir, bool sop_mode, std::string box_file, std::string lut_file, + std::string wire_delay) { module = current_module; map_autoidx = autoidx++; @@ -387,6 +388,9 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri for (size_t pos = abc_script.find("{S}"); pos != std::string::npos; pos = abc_script.find("{S}", pos)) abc_script = abc_script.substr(0, pos) + lutin_shared + abc_script.substr(pos+3); + for (size_t pos = abc_script.find("{W}"); pos != std::string::npos; pos = abc_script.find("{W}", pos)) + abc_script = abc_script.substr(0, pos) + wire_delay + abc_script.substr(pos+3); + abc_script += stringf("; &write %s/output.aig", tempdir_name.c_str()); abc_script = add_echos_to_abc_cmd(abc_script); @@ -960,7 +964,7 @@ struct Abc9Pass : public Pass { std::string exe_file = proc_self_dirname() + "yosys-abc"; #endif std::string script_file, liberty_file, constr_file, clk_str, box_file, lut_file; - std::string delay_target, sop_inputs, sop_products, lutin_shared = "-S 1"; + std::string delay_target, sop_inputs, sop_products, lutin_shared = "-S 1", wire_delay; bool fast_mode = false, dff_mode = false, keepff = false, cleanup = true; bool show_tempdir = false, sop_mode = false; vector lut_costs; @@ -1214,6 +1218,10 @@ struct Abc9Pass : public Pass { box_file = std::string(pwd) + "/" + box_file; continue; } + if (arg == "-W" && argidx+1 < args.size()) { + wire_delay = "-S " + args[++argidx]; + continue; + } break; } extra_args(args, argidx, design); @@ -1256,7 +1264,7 @@ struct Abc9Pass : public Pass { if (!dff_mode || !clk_str.empty()) { abc9_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, dff_mode, clk_str, keepff, delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, mod->selected_cells(), show_tempdir, sop_mode, - box_file, lut_file); + box_file, lut_file, wire_delay); continue; } @@ -1402,7 +1410,7 @@ struct Abc9Pass : public Pass { en_sig = assign_map(std::get<3>(it.first)); abc9_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, !clk_sig.empty(), "$", keepff, delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, it.second, show_tempdir, sop_mode, - box_file, lut_file); + box_file, lut_file, wire_delay); assign_map.set(mod); } } diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index f5f8c43e0..f966115cd 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -297,7 +297,7 @@ struct SynthXilinxPass : public ScriptPass if (check_label("map_luts")) { if (abc == "abc9") - run(abc + " -lut +/xilinx/abc.lut -box +/xilinx/abc.box" + string(retime ? " -dff" : "")); + run(abc + " -lut +/xilinx/abc.lut -box +/xilinx/abc.box -W 160" + string(retime ? " -dff" : "")); else if (help_mode) run(abc + " -luts 2:2,3,6:5,10,20 [-dff]"); else From 4c9fde87d170fc8d4b729581b055407553951e4c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 12 Jun 2019 08:48:45 -0700 Subject: [PATCH 212/213] Revert "Add "-W' wire delay arg to abc9, use from synth_xilinx" This reverts commit 2dffa4685b830313204f5d04314a14ed6ecac8ec. --- frontends/verilog/verilog_lexer.l | 5 +++++ passes/techmap/abc9.cc | 18 +++++------------- techlibs/xilinx/synth_xilinx.cc | 2 +- 3 files changed, 11 insertions(+), 14 deletions(-) diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l index 9558bbfb9..3c612472d 100644 --- a/frontends/verilog/verilog_lexer.l +++ b/frontends/verilog/verilog_lexer.l @@ -311,6 +311,11 @@ supply1 { return TOK_SUPPLY1; } return TOK_ID; } +"$"(info|warning|error|fatal) { + frontend_verilog_yylval.string = new std::string(yytext); + return TOK_ELAB_TASK; +} + "$signed" { return TOK_TO_SIGNED; } "$unsigned" { return TOK_TO_UNSIGNED; } diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 19157adc6..af9439e41 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -25,7 +25,7 @@ #define ABC_COMMAND_LIB "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put" #define ABC_COMMAND_CTR "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put; buffer; upsize {D}; dnsize {D}; stime -p" //#define ABC_COMMAND_LUT "strash; ifraig; scorr; dc2; dretime; strash; dch -f; if; mfs2" -#define ABC_COMMAND_LUT "&st; &sweep; &scorr; "/*"&dc2; */"&retime; &dch -f; &ps -l; &if {W} -v; &ps -l" +#define ABC_COMMAND_LUT "&st; &sweep; &scorr; "/*"&dc2; */"&retime; &dch -f; &ps -l; &if -W 160 -v; &ps -l" #define ABC_COMMAND_SOP "strash; ifraig; scorr; dc2; dretime; strash; dch -f; cover {I} {P}" #define ABC_COMMAND_DFL "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put" @@ -272,8 +272,7 @@ failed: void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file, std::string liberty_file, std::string constr_file, bool cleanup, vector lut_costs, bool dff_mode, std::string clk_str, bool keepff, std::string delay_target, std::string sop_inputs, std::string sop_products, std::string lutin_shared, bool fast_mode, - const std::vector &cells, bool show_tempdir, bool sop_mode, std::string box_file, std::string lut_file, - std::string wire_delay) + const std::vector &cells, bool show_tempdir, bool sop_mode, std::string box_file, std::string lut_file) { module = current_module; map_autoidx = autoidx++; @@ -388,9 +387,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri for (size_t pos = abc_script.find("{S}"); pos != std::string::npos; pos = abc_script.find("{S}", pos)) abc_script = abc_script.substr(0, pos) + lutin_shared + abc_script.substr(pos+3); - for (size_t pos = abc_script.find("{W}"); pos != std::string::npos; pos = abc_script.find("{W}", pos)) - abc_script = abc_script.substr(0, pos) + wire_delay + abc_script.substr(pos+3); - abc_script += stringf("; &write %s/output.aig", tempdir_name.c_str()); abc_script = add_echos_to_abc_cmd(abc_script); @@ -964,7 +960,7 @@ struct Abc9Pass : public Pass { std::string exe_file = proc_self_dirname() + "yosys-abc"; #endif std::string script_file, liberty_file, constr_file, clk_str, box_file, lut_file; - std::string delay_target, sop_inputs, sop_products, lutin_shared = "-S 1", wire_delay; + std::string delay_target, sop_inputs, sop_products, lutin_shared = "-S 1"; bool fast_mode = false, dff_mode = false, keepff = false, cleanup = true; bool show_tempdir = false, sop_mode = false; vector lut_costs; @@ -1218,10 +1214,6 @@ struct Abc9Pass : public Pass { box_file = std::string(pwd) + "/" + box_file; continue; } - if (arg == "-W" && argidx+1 < args.size()) { - wire_delay = "-S " + args[++argidx]; - continue; - } break; } extra_args(args, argidx, design); @@ -1264,7 +1256,7 @@ struct Abc9Pass : public Pass { if (!dff_mode || !clk_str.empty()) { abc9_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, dff_mode, clk_str, keepff, delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, mod->selected_cells(), show_tempdir, sop_mode, - box_file, lut_file, wire_delay); + box_file, lut_file); continue; } @@ -1410,7 +1402,7 @@ struct Abc9Pass : public Pass { en_sig = assign_map(std::get<3>(it.first)); abc9_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, !clk_sig.empty(), "$", keepff, delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, it.second, show_tempdir, sop_mode, - box_file, lut_file, wire_delay); + box_file, lut_file); assign_map.set(mod); } } diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index f966115cd..f5f8c43e0 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -297,7 +297,7 @@ struct SynthXilinxPass : public ScriptPass if (check_label("map_luts")) { if (abc == "abc9") - run(abc + " -lut +/xilinx/abc.lut -box +/xilinx/abc.box -W 160" + string(retime ? " -dff" : "")); + run(abc + " -lut +/xilinx/abc.lut -box +/xilinx/abc.box" + string(retime ? " -dff" : "")); else if (help_mode) run(abc + " -luts 2:2,3,6:5,10,20 [-dff]"); else From 1e838a8913afa36a57d425f26ea881f5071b8b5d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 12 Jun 2019 08:49:15 -0700 Subject: [PATCH 213/213] Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx" --- passes/techmap/abc9.cc | 18 +++++++++++++----- techlibs/xilinx/synth_xilinx.cc | 2 +- 2 files changed, 14 insertions(+), 6 deletions(-) diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index af9439e41..19157adc6 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -25,7 +25,7 @@ #define ABC_COMMAND_LIB "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put" #define ABC_COMMAND_CTR "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put; buffer; upsize {D}; dnsize {D}; stime -p" //#define ABC_COMMAND_LUT "strash; ifraig; scorr; dc2; dretime; strash; dch -f; if; mfs2" -#define ABC_COMMAND_LUT "&st; &sweep; &scorr; "/*"&dc2; */"&retime; &dch -f; &ps -l; &if -W 160 -v; &ps -l" +#define ABC_COMMAND_LUT "&st; &sweep; &scorr; "/*"&dc2; */"&retime; &dch -f; &ps -l; &if {W} -v; &ps -l" #define ABC_COMMAND_SOP "strash; ifraig; scorr; dc2; dretime; strash; dch -f; cover {I} {P}" #define ABC_COMMAND_DFL "strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f; &nf {D}; &put" @@ -272,7 +272,8 @@ failed: void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file, std::string liberty_file, std::string constr_file, bool cleanup, vector lut_costs, bool dff_mode, std::string clk_str, bool keepff, std::string delay_target, std::string sop_inputs, std::string sop_products, std::string lutin_shared, bool fast_mode, - const std::vector &cells, bool show_tempdir, bool sop_mode, std::string box_file, std::string lut_file) + const std::vector &cells, bool show_tempdir, bool sop_mode, std::string box_file, std::string lut_file, + std::string wire_delay) { module = current_module; map_autoidx = autoidx++; @@ -387,6 +388,9 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri for (size_t pos = abc_script.find("{S}"); pos != std::string::npos; pos = abc_script.find("{S}", pos)) abc_script = abc_script.substr(0, pos) + lutin_shared + abc_script.substr(pos+3); + for (size_t pos = abc_script.find("{W}"); pos != std::string::npos; pos = abc_script.find("{W}", pos)) + abc_script = abc_script.substr(0, pos) + wire_delay + abc_script.substr(pos+3); + abc_script += stringf("; &write %s/output.aig", tempdir_name.c_str()); abc_script = add_echos_to_abc_cmd(abc_script); @@ -960,7 +964,7 @@ struct Abc9Pass : public Pass { std::string exe_file = proc_self_dirname() + "yosys-abc"; #endif std::string script_file, liberty_file, constr_file, clk_str, box_file, lut_file; - std::string delay_target, sop_inputs, sop_products, lutin_shared = "-S 1"; + std::string delay_target, sop_inputs, sop_products, lutin_shared = "-S 1", wire_delay; bool fast_mode = false, dff_mode = false, keepff = false, cleanup = true; bool show_tempdir = false, sop_mode = false; vector lut_costs; @@ -1214,6 +1218,10 @@ struct Abc9Pass : public Pass { box_file = std::string(pwd) + "/" + box_file; continue; } + if (arg == "-W" && argidx+1 < args.size()) { + wire_delay = "-S " + args[++argidx]; + continue; + } break; } extra_args(args, argidx, design); @@ -1256,7 +1264,7 @@ struct Abc9Pass : public Pass { if (!dff_mode || !clk_str.empty()) { abc9_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, dff_mode, clk_str, keepff, delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, mod->selected_cells(), show_tempdir, sop_mode, - box_file, lut_file); + box_file, lut_file, wire_delay); continue; } @@ -1402,7 +1410,7 @@ struct Abc9Pass : public Pass { en_sig = assign_map(std::get<3>(it.first)); abc9_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, !clk_sig.empty(), "$", keepff, delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, it.second, show_tempdir, sop_mode, - box_file, lut_file); + box_file, lut_file, wire_delay); assign_map.set(mod); } } diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index f5f8c43e0..f966115cd 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -297,7 +297,7 @@ struct SynthXilinxPass : public ScriptPass if (check_label("map_luts")) { if (abc == "abc9") - run(abc + " -lut +/xilinx/abc.lut -box +/xilinx/abc.box" + string(retime ? " -dff" : "")); + run(abc + " -lut +/xilinx/abc.lut -box +/xilinx/abc.box -W 160" + string(retime ? " -dff" : "")); else if (help_mode) run(abc + " -luts 2:2,3,6:5,10,20 [-dff]"); else