mirror of https://github.com/YosysHQ/yosys.git
Added "scc -expect <N> -nofeedback"
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@ -100,7 +100,8 @@ struct SccWorker
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}
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}
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}
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}
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SccWorker(RTLIL::Design *design, RTLIL::Module *module, bool allCellTypes, int maxDepth) : design(design), module(module), sigmap(module)
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SccWorker(RTLIL::Design *design, RTLIL::Module *module, bool nofeedbackMode, bool allCellTypes, int maxDepth) :
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design(design), module(module), sigmap(module)
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{
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{
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if (module->processes.size() > 0) {
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if (module->processes.size() > 0) {
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log("Skipping module %s as it contains processes (run 'proc' pass first).\n", module->name.c_str());
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log("Skipping module %s as it contains processes (run 'proc' pass first).\n", module->name.c_str());
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@ -167,11 +168,23 @@ struct SccWorker
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labelCounter = 0;
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labelCounter = 0;
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cellLabels.clear();
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cellLabels.clear();
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while (workQueue.size() > 0) {
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while (workQueue.size() > 0)
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{
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RTLIL::Cell *cell = *workQueue.begin();
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RTLIL::Cell *cell = *workQueue.begin();
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log_assert(cellStack.size() == 0);
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log_assert(cellStack.size() == 0);
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cellDepth.clear();
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cellDepth.clear();
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run(cell, 0, maxDepth);
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if (!nofeedbackMode && cellToNextCell[cell].count(cell)) {
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log("Found an SCC:");
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std::set<RTLIL::Cell*> scc;
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log(" %s", RTLIL::id2cstr(cell->name));
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cell2scc[cell] = sccList.size();
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scc.insert(cell);
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sccList.push_back(scc);
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workQueue.erase(cell);
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log("\n");
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} else
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run(cell, 0, maxDepth);
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}
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}
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log("Found %d SCCs in module %s.\n", int(sccList.size()), RTLIL::id2cstr(module->name));
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log("Found %d SCCs in module %s.\n", int(sccList.size()), RTLIL::id2cstr(module->name));
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@ -212,10 +225,18 @@ struct SccPass : public Pass {
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log("This command identifies strongly connected components (aka logic loops) in the\n");
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log("This command identifies strongly connected components (aka logic loops) in the\n");
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log("design.\n");
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log("design.\n");
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log("\n");
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log("\n");
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log(" -expect <num>\n");
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log(" expect to find exactly <num> SSCs. A different number of SSCs will\n");
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log(" produce an error.\n");
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log("\n");
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log(" -max_depth <num>\n");
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log(" -max_depth <num>\n");
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log(" limit to loops not longer than the specified number of cells. This can\n");
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log(" limit to loops not longer than the specified number of cells. This\n");
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log(" e.g. be useful in identifying local loops in a module that turns out\n");
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log(" can e.g. be useful in identifying small local loops in a module that\n");
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log(" to be one gigantic SCC.\n");
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log(" implements one large SCC.\n");
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log("\n");
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log(" -nofeedback\n");
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log(" do not count cells that have their output fed back into one of their\n");
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log(" inputs as single-cell scc.\n");
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log("\n");
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log("\n");
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log(" -all_cell_types\n");
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log(" -all_cell_types\n");
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log(" Usually this command only considers internal non-memory cells. With\n");
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log(" Usually this command only considers internal non-memory cells. With\n");
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@ -239,7 +260,9 @@ struct SccPass : public Pass {
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std::map<std::string, std::string> setCellAttr, setWireAttr;
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std::map<std::string, std::string> setCellAttr, setWireAttr;
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bool allCellTypes = false;
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bool allCellTypes = false;
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bool selectMode = false;
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bool selectMode = false;
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bool nofeedbackMode = false;
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int maxDepth = -1;
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int maxDepth = -1;
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int expect = -1;
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log_header("Executing SCC pass (detecting logic loops).\n");
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log_header("Executing SCC pass (detecting logic loops).\n");
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@ -249,6 +272,14 @@ struct SccPass : public Pass {
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maxDepth = atoi(args[++argidx].c_str());
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maxDepth = atoi(args[++argidx].c_str());
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continue;
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continue;
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}
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}
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if (args[argidx] == "-expect" && argidx+1 < args.size()) {
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expect = atoi(args[++argidx].c_str());
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continue;
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}
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if (args[argidx] == "-nofeedback") {
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nofeedbackMode = true;
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continue;
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}
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if (args[argidx] == "-all_cell_types") {
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if (args[argidx] == "-all_cell_types") {
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allCellTypes = true;
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allCellTypes = true;
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continue;
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continue;
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@ -282,16 +313,26 @@ struct SccPass : public Pass {
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log_cmd_error("The -set*_attr options are not implemented at the moment!\n");
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log_cmd_error("The -set*_attr options are not implemented at the moment!\n");
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RTLIL::Selection newSelection(false);
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RTLIL::Selection newSelection(false);
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int scc_counter = 0;
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for (auto &mod_it : design->modules_)
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for (auto &mod_it : design->modules_)
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if (design->selected(mod_it.second))
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if (design->selected(mod_it.second))
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{
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{
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SccWorker worker(design, mod_it.second, allCellTypes, maxDepth);
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SccWorker worker(design, mod_it.second, nofeedbackMode, allCellTypes, maxDepth);
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scc_counter += GetSize(worker.sccList);
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if (selectMode)
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if (selectMode)
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worker.select(newSelection);
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worker.select(newSelection);
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}
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}
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if (expect >= 0) {
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if (scc_counter == expect)
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log("Found and expected %d SCCs.\n", scc_counter);
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else
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log_error("Found %d SCCs but expected %d.\n", scc_counter, expect);
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} else
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log("Found %d SCCs.\n", scc_counter);
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if (selectMode) {
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if (selectMode) {
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log_assert(origSelectPos >= 0);
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log_assert(origSelectPos >= 0);
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design->selection_stack[origSelectPos] = newSelection;
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design->selection_stack[origSelectPos] = newSelection;
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