mirror of https://github.com/YosysHQ/yosys.git
fmt: Allow non-constant $display calls in initial blocks
These are useful for formal verification with SBY where they can be used to display solver chosen `rand const reg` signals and signals derived from those. The previous error message for non-constant initial $display statements is downgraded to a log message. Constant initial $display statements will be shown both during elaboration and become part of the RTLIL so that the `sim` output is complete.
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@ -287,7 +287,7 @@ namespace AST
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bool is_simple_const_expr();
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// helper for parsing format strings
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Fmt processFormat(int stage, bool sformat_like, int default_base = 10, size_t first_arg_at = 0);
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Fmt processFormat(int stage, bool sformat_like, int default_base = 10, size_t first_arg_at = 0, bool may_fail = false);
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bool is_recursive_function() const;
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std::pair<AstNode*, AstNode*> get_tern_choice();
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@ -145,7 +145,7 @@ void AstNode::fixup_hierarchy_flags(bool force_descend)
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// Process a format string and arguments for $display, $write, $sprintf, etc
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Fmt AstNode::processFormat(int stage, bool sformat_like, int default_base, size_t first_arg_at) {
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Fmt AstNode::processFormat(int stage, bool sformat_like, int default_base, size_t first_arg_at, bool may_fail) {
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std::vector<VerilogFmtArg> args;
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for (size_t index = first_arg_at; index < children.size(); index++) {
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AstNode *node_arg = children[index];
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@ -169,6 +169,9 @@ Fmt AstNode::processFormat(int stage, bool sformat_like, int default_base, size_
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arg.type = VerilogFmtArg::INTEGER;
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arg.sig = node_arg->bitsAsConst();
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arg.signed_ = node_arg->is_signed;
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} else if (may_fail) {
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log_file_info(filename, location.first_line, "Skipping system task `%s' with non-constant argument at position %zu.\n", str.c_str(), index + 1);
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return Fmt();
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} else {
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log_file_error(filename, location.first_line, "Failed to evaluate system task `%s' with non-constant argument at position %zu.\n", str.c_str(), index + 1);
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}
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@ -1065,10 +1068,13 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
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default_base = 16;
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// when $display()/$write() functions are used in an initial block, print them during synthesis
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Fmt fmt = processFormat(stage, /*sformat_like=*/false, default_base);
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Fmt fmt = processFormat(stage, /*sformat_like=*/false, default_base, /*first_arg_at=*/0, /*may_fail=*/true);
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if (str.substr(0, 8) == "$display")
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fmt.append_string("\n");
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log("%s", fmt.render().c_str());
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for (auto node : children)
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while (node->simplify(true, stage, -1, false)) {}
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return false;
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} else {
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// when $display()/$write() functions are used in an always block, simplify the expressions and
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// convert them to a special cell later in genrtlil
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