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Fix cells_sim.v for Achronix FPGA

This commit is contained in:
Miodrag Milanovic 2019-01-04 15:15:23 +01:00
parent d98fe8ce1f
commit 50ef4561d4
1 changed files with 1 additions and 1 deletions
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2
techlibs/achronix/speedster22i/cells_sim.v
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@ -61,7 +61,7 @@ reg [1:0] s1;
end end
endfunction endfunction
always @(dataa_w or datab_w or datac_w or datad_w or cin_w) begin always @(dataa_w or datab_w or datac_w or datad_w) begin
combout_rt = lut_data(lut_function, dataa_w, datab_w, combout_rt = lut_data(lut_function, dataa_w, datab_w,
datac_w, datad_w); datac_w, datad_w);
end end