diff --git a/docs/source/code_examples/fifo/Makefile b/docs/source/code_examples/fifo/Makefile index e0287eab4..795853f81 100644 --- a/docs/source/code_examples/fifo/Makefile +++ b/docs/source/code_examples/fifo/Makefile @@ -2,14 +2,17 @@ PROGRAM_PREFIX := YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys -DOTS = addr_gen_hier.dot addr_gen_proc.dot -DOTS += rdata_proc.dot rdata_flat.dot -DOTS += fifo_flat.dot fifo_synth.dot +DOT_NAMES = addr_gen_hier addr_gen_proc addr_gen_clean +DOT_NAMES += rdata_proc rdata_flat rdata_adffe rdata_memrdv2 rdata_alumacc +DOT_NAMES += rdata_coarse rdata_map_ram rdata_map_ffram rdata_map_gates +DOT_NAMES += rdata_map_ffs rdata_map_luts rdata_map_cells + +DOTS := $(addsuffix .dot,$(DOT_NAMES)) dots: $(DOTS) fifo.out $(DOTS) fifo.out: fifo.v fifo.ys - $(YOSYS) fifo.ys -l fifo.out -Q + $(YOSYS) fifo.ys -l fifo.out -Q -T .PHONY: clean clean: diff --git a/docs/source/code_examples/fifo/fifo.out b/docs/source/code_examples/fifo/fifo.out index 5a4215e5c..d747247c5 100644 --- a/docs/source/code_examples/fifo/fifo.out +++ b/docs/source/code_examples/fifo/fifo.out @@ -27,7 +27,9 @@ Removing unused module `$abstract\fifo'. Removing unused module `$abstract\addr_gen'. Removed 2 unused modules. -yosys> show -notitle -format dot -prefix addr_gen_hier +yosys> select -set new_cells t:* + +yosys> show -color maroon3 @new_cells -notitle -format dot -prefix addr_gen_hier 4. Generating Graphviz representation of design. Writing dot description to `addr_gen_hier.dot'. @@ -105,17 +107,32 @@ yosys> opt_expr -keepdc 5.12. Executing OPT_EXPR pass (perform const folding). Optimizing module addr_gen. -yosys> show -notitle -format dot -prefix addr_gen_proc +yosys> select -set new_cells t:$mux t:*dff + +yosys> show -color maroon3 @new_cells -notitle -format dot -prefix addr_gen_proc 6. Generating Graphviz representation of design. Writing dot description to `addr_gen_proc.dot'. Dumping module addr_gen to page 1. +yosys> opt_clean + +7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \addr_gen.. +Removed 0 unused cells and 4 unused wires. + + +yosys> show -notitle -format dot -prefix addr_gen_clean + +8. Generating Graphviz representation of design. +Writing dot description to `addr_gen_clean.dot'. +Dumping module addr_gen to page 1. + yosys> design -reset yosys> read_verilog fifo.v -7. Executing Verilog-2005 frontend: fifo.v +9. Executing Verilog-2005 frontend: fifo.v Parsing Verilog input from `fifo.v' to AST representation. Generating RTLIL representation for module `\addr_gen'. Generating RTLIL representation for module `\fifo'. @@ -123,24 +140,24 @@ Successfully finished Verilog frontend. yosys> hierarchy -check -top fifo -8. Executing HIERARCHY pass (managing design hierarchy). +10. Executing HIERARCHY pass (managing design hierarchy). -8.1. Analyzing design hierarchy.. +10.1. Analyzing design hierarchy.. Top module: \fifo Used module: \addr_gen Parameter \MAX_DATA = 256 -8.2. Executing AST frontend in derive mode using pre-parsed AST for module `\addr_gen'. +10.2. Executing AST frontend in derive mode using pre-parsed AST for module `\addr_gen'. Parameter \MAX_DATA = 256 Generating RTLIL representation for module `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000'. Parameter \MAX_DATA = 256 Found cached RTLIL representation for module `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000'. -8.3. Analyzing design hierarchy.. +10.3. Analyzing design hierarchy.. Top module: \fifo Used module: $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000 -8.4. Analyzing design hierarchy.. +10.4. Analyzing design hierarchy.. Top module: \fifo Used module: $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000 Removing unused module `\addr_gen'. @@ -148,16 +165,16 @@ Removed 1 unused modules. yosys> proc -9. Executing PROC pass (convert processes to netlists). +11. Executing PROC pass (convert processes to netlists). yosys> proc_clean -9.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +11.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. yosys> proc_rmdead -9.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +11.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 2 switch rules as full_case in process $proc$fifo.v:64$24 in module fifo. Marked 1 switch rules as full_case in process $proc$fifo.v:38$16 in module fifo. Marked 2 switch rules as full_case in process $proc$fifo.v:13$32 in module $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000. @@ -165,13 +182,13 @@ Removed a total of 0 dead cases. yosys> proc_prune -9.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +11.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 6 assignments to connections. yosys> proc_init -9.4. Executing PROC_INIT pass (extract init attributes). +11.4. Executing PROC_INIT pass (extract init attributes). Found init rule in `\fifo.$proc$fifo.v:0$31'. Set init value: \count = 9'000000000 Found init rule in `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:0$35'. @@ -179,19 +196,19 @@ Found init rule in `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000 yosys> proc_arst -9.5. Executing PROC_ARST pass (detect async resets in processes). +11.5. Executing PROC_ARST pass (detect async resets in processes). Found async reset \rst in `\fifo.$proc$fifo.v:64$24'. Found async reset \rst in `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:13$32'. yosys> proc_rom -9.6. Executing PROC_ROM pass (convert switches to ROMs). +11.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. yosys> proc_mux -9.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +11.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\fifo.$proc$fifo.v:0$31'. Creating decoders for process `\fifo.$proc$fifo.v:64$24'. 1/1: $0\count[8:0] @@ -205,11 +222,11 @@ Creating decoders for process `$paramod\addr_gen\MAX_DATA=s32'000000000000000000 yosys> proc_dlatch -9.8. Executing PROC_DLATCH pass (convert process syncs to latches). +11.8. Executing PROC_DLATCH pass (convert process syncs to latches). yosys> proc_dff -9.9. Executing PROC_DFF pass (convert process syncs to FFs). +11.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\fifo.\count' using process `\fifo.$proc$fifo.v:64$24'. created $adff cell `$procdff$55' with positive edge clock and positive level reset. Creating register for signal `\fifo.\rdata' using process `\fifo.$proc$fifo.v:38$16'. @@ -225,11 +242,11 @@ Creating register for signal `$paramod\addr_gen\MAX_DATA=s32'0000000000000000000 yosys> proc_memwr -9.10. Executing PROC_MEMWR pass (convert process memory writes to cells). +11.10. Executing PROC_MEMWR pass (convert process memory writes to cells). yosys> proc_clean -9.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +11.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `fifo.$proc$fifo.v:0$31'. Found and cleaned up 2 empty switches in `\fifo.$proc$fifo.v:64$24'. Removing empty process `fifo.$proc$fifo.v:64$24'. @@ -242,58 +259,103 @@ Cleaned up 5 empty switches. yosys> opt_expr -keepdc -9.12. Executing OPT_EXPR pass (perform const folding). +11.12. Executing OPT_EXPR pass (perform const folding). Optimizing module fifo. Optimizing module $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000. -yosys> show -notitle -format dot -prefix rdata_proc o:rdata %ci* +yosys> show -color maroon3 c:fifo_reader -notitle -format dot -prefix rdata_proc o:rdata %ci* -10. Generating Graphviz representation of design. +12. Generating Graphviz representation of design. Writing dot description to `rdata_proc.dot'. Dumping selected parts of module fifo to page 1. yosys> flatten -11. Executing FLATTEN pass (flatten design). +13. Executing FLATTEN pass (flatten design). Deleting now unused module $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000. +yosys> clean +Removed 3 unused cells and 25 unused wires. + yosys> show -notitle -format dot -prefix rdata_flat o:rdata %ci* -12. Generating Graphviz representation of design. +14. Generating Graphviz representation of design. Writing dot description to `rdata_flat.dot'. Dumping selected parts of module fifo to page 1. -yosys> opt_clean +yosys> opt_dff -13. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \fifo.. -Removed 3 unused cells and 25 unused wires. - +15. Executing OPT_DFF pass (perform DFF optimizations). +Adding EN signal on $procdff$55 ($adff) from module fifo (D = $0\count[8:0], Q = \count). +Adding EN signal on $flatten\fifo_writer.$procdff$60 ($adff) from module fifo (D = $flatten\fifo_writer.$procmux$51_Y, Q = \fifo_writer.addr). +Adding EN signal on $flatten\fifo_reader.$procdff$60 ($adff) from module fifo (D = $flatten\fifo_reader.$procmux$51_Y, Q = \fifo_reader.addr). -yosys> show -notitle -format dot -prefix fifo_flat +yosys> select -set new_cells t:$adffe -14. Generating Graphviz representation of design. -Writing dot description to `fifo_flat.dot'. -Dumping module fifo to page 1. +yosys> show -color maroon3 @new_cells -notitle -format dot -prefix rdata_adffe o:rdata %ci* + +16. Generating Graphviz representation of design. +Writing dot description to `rdata_adffe.dot'. +Dumping selected parts of module fifo to page 1. + +yosys> memory_dff + +17. Executing MEMORY_DFF pass (merging $dff cells to $memrd). +Checking read port `\data'[0] in module `\fifo': merging output FF to cell. + Write port 0: non-transparent. + +yosys> select -set new_cells t:$memrd_v2 + +yosys> show -color maroon3 @new_cells -notitle -format dot -prefix rdata_memrdv2 o:rdata %ci* + +18. Generating Graphviz representation of design. +Writing dot description to `rdata_memrdv2.dot'. +Dumping selected parts of module fifo to page 1. + +yosys> alumacc + +19. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module fifo: + creating $macc model for $add$fifo.v:68$27 ($add). + creating $macc model for $flatten\fifo_reader.$add$fifo.v:20$34 ($add). + creating $macc model for $flatten\fifo_writer.$add$fifo.v:20$34 ($add). + creating $macc model for $sub$fifo.v:70$30 ($sub). + creating $alu model for $macc $sub$fifo.v:70$30. + creating $alu model for $macc $flatten\fifo_writer.$add$fifo.v:20$34. + creating $alu model for $macc $flatten\fifo_reader.$add$fifo.v:20$34. + creating $alu model for $macc $add$fifo.v:68$27. + creating $alu cell for $flatten\fifo_reader.$add$fifo.v:20$34: $auto$alumacc.cc:485:replace_alu$76 + creating $alu cell for $flatten\fifo_writer.$add$fifo.v:20$34: $auto$alumacc.cc:485:replace_alu$79 + creating $alu cell for $add$fifo.v:68$27: $auto$alumacc.cc:485:replace_alu$82 + creating $alu cell for $sub$fifo.v:70$30: $auto$alumacc.cc:485:replace_alu$85 + created 4 $alu and 0 $macc cells. + +yosys> select -set new_cells t:$alu t:$macc + +yosys> show -color maroon3 @new_cells -notitle -format dot -prefix rdata_alumacc o:rdata %ci* + +20. Generating Graphviz representation of design. +Writing dot description to `rdata_alumacc.dot'. +Dumping selected parts of module fifo to page 1. yosys> design -reset yosys> read_verilog fifo.v -15. Executing Verilog-2005 frontend: fifo.v +21. Executing Verilog-2005 frontend: fifo.v Parsing Verilog input from `fifo.v' to AST representation. Generating RTLIL representation for module `\addr_gen'. Generating RTLIL representation for module `\fifo'. Successfully finished Verilog frontend. -yosys> synth_ice40 -dsp -top fifo +yosys> synth_ice40 -top fifo -run begin:map_ram -16. Executing SYNTH_ICE40 pass. +22. Executing SYNTH_ICE40 pass. yosys> read_verilog -D ICE40_HX -lib -specify +/ice40/cells_sim.v -16.1. Executing Verilog-2005 frontend: /home/dawn/yosys/share/ice40/cells_sim.v +22.1. Executing Verilog-2005 frontend: /home/dawn/yosys/share/ice40/cells_sim.v Parsing Verilog input from `/home/dawn/yosys/share/ice40/cells_sim.v' to AST representation. Generating RTLIL representation for module `\SB_IO'. Generating RTLIL representation for module `\SB_GB_IO'. @@ -349,24 +411,24 @@ Successfully finished Verilog frontend. yosys> hierarchy -check -top fifo -16.2. Executing HIERARCHY pass (managing design hierarchy). +22.2. Executing HIERARCHY pass (managing design hierarchy). -16.2.1. Analyzing design hierarchy.. +22.2.1. Analyzing design hierarchy.. Top module: \fifo Used module: \addr_gen Parameter \MAX_DATA = 256 -16.2.2. Executing AST frontend in derive mode using pre-parsed AST for module `\addr_gen'. +22.2.2. Executing AST frontend in derive mode using pre-parsed AST for module `\addr_gen'. Parameter \MAX_DATA = 256 Generating RTLIL representation for module `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000'. Parameter \MAX_DATA = 256 Found cached RTLIL representation for module `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000'. -16.2.3. Analyzing design hierarchy.. +22.2.3. Analyzing design hierarchy.. Top module: \fifo Used module: $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000 -16.2.4. Analyzing design hierarchy.. +22.2.4. Analyzing design hierarchy.. Top module: \fifo Used module: $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000 Removing unused module `\addr_gen'. @@ -374,370 +436,370 @@ Removed 1 unused modules. yosys> proc -16.3. Executing PROC pass (convert processes to netlists). +22.3. Executing PROC pass (convert processes to netlists). yosys> proc_clean -16.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +22.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. yosys> proc_rmdead -16.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). -Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:1414$323 in module SB_DFFNES. -Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:1353$316 in module SB_DFFNESS. -Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:1273$312 in module SB_DFFNER. -Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:1212$305 in module SB_DFFNESR. -Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:1138$302 in module SB_DFFNS. -Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:1088$299 in module SB_DFFNSS. -Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:1017$296 in module SB_DFFNR. -Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:967$293 in module SB_DFFNSR. -Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:803$285 in module SB_DFFES. -Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:742$278 in module SB_DFFESS. -Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:662$274 in module SB_DFFER. -Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:601$267 in module SB_DFFESR. -Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:527$264 in module SB_DFFS. -Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:477$261 in module SB_DFFSS. -Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:406$258 in module SB_DFFR. -Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:356$255 in module SB_DFFSR. -Marked 2 switch rules as full_case in process $proc$fifo.v:64$75 in module fifo. -Marked 1 switch rules as full_case in process $proc$fifo.v:38$67 in module fifo. -Marked 2 switch rules as full_case in process $proc$fifo.v:13$463 in module $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000. +22.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:1414$349 in module SB_DFFNES. +Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:1353$342 in module SB_DFFNESS. +Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:1273$338 in module SB_DFFNER. +Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:1212$331 in module SB_DFFNESR. +Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:1138$328 in module SB_DFFNS. +Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:1088$325 in module SB_DFFNSS. +Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:1017$322 in module SB_DFFNR. +Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:967$319 in module SB_DFFNSR. +Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:803$311 in module SB_DFFES. +Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:742$304 in module SB_DFFESS. +Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:662$300 in module SB_DFFER. +Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:601$293 in module SB_DFFESR. +Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:527$290 in module SB_DFFS. +Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:477$287 in module SB_DFFSS. +Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:406$284 in module SB_DFFR. +Marked 1 switch rules as full_case in process $proc$/home/dawn/yosys/share/ice40/cells_sim.v:356$281 in module SB_DFFSR. +Marked 2 switch rules as full_case in process $proc$fifo.v:64$101 in module fifo. +Marked 1 switch rules as full_case in process $proc$fifo.v:38$93 in module fifo. +Marked 2 switch rules as full_case in process $proc$fifo.v:13$489 in module $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000. Removed a total of 0 dead cases. yosys> proc_prune -16.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +22.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 8 redundant assignments. Promoted 28 assignments to connections. yosys> proc_init -16.3.4. Executing PROC_INIT pass (extract init attributes). -Found init rule in `\SB_DFFNES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$326'. +22.3.4. Executing PROC_INIT pass (extract init attributes). +Found init rule in `\SB_DFFNES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$352'. Set init value: \Q = 1'0 -Found init rule in `\SB_DFFNESS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$322'. +Found init rule in `\SB_DFFNESS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$348'. Set init value: \Q = 1'0 -Found init rule in `\SB_DFFNER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$315'. +Found init rule in `\SB_DFFNER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$341'. Set init value: \Q = 1'0 -Found init rule in `\SB_DFFNESR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$311'. +Found init rule in `\SB_DFFNESR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$337'. Set init value: \Q = 1'0 -Found init rule in `\SB_DFFNS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$304'. +Found init rule in `\SB_DFFNS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$330'. Set init value: \Q = 1'0 -Found init rule in `\SB_DFFNSS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$301'. +Found init rule in `\SB_DFFNSS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$327'. Set init value: \Q = 1'0 -Found init rule in `\SB_DFFNR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$298'. +Found init rule in `\SB_DFFNR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$324'. Set init value: \Q = 1'0 -Found init rule in `\SB_DFFNSR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$295'. +Found init rule in `\SB_DFFNSR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$321'. Set init value: \Q = 1'0 -Found init rule in `\SB_DFFNE.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$292'. +Found init rule in `\SB_DFFNE.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$318'. Set init value: \Q = 1'0 -Found init rule in `\SB_DFFN.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$290'. +Found init rule in `\SB_DFFN.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$316'. Set init value: \Q = 1'0 -Found init rule in `\SB_DFFES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$288'. +Found init rule in `\SB_DFFES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$314'. Set init value: \Q = 1'0 -Found init rule in `\SB_DFFESS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$284'. +Found init rule in `\SB_DFFESS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$310'. Set init value: \Q = 1'0 -Found init rule in `\SB_DFFER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$277'. +Found init rule in `\SB_DFFER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$303'. Set init value: \Q = 1'0 -Found init rule in `\SB_DFFESR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$273'. +Found init rule in `\SB_DFFESR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$299'. Set init value: \Q = 1'0 -Found init rule in `\SB_DFFS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$266'. +Found init rule in `\SB_DFFS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$292'. Set init value: \Q = 1'0 -Found init rule in `\SB_DFFSS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$263'. +Found init rule in `\SB_DFFSS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$289'. Set init value: \Q = 1'0 -Found init rule in `\SB_DFFR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$260'. +Found init rule in `\SB_DFFR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$286'. Set init value: \Q = 1'0 -Found init rule in `\SB_DFFSR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$257'. +Found init rule in `\SB_DFFSR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$283'. Set init value: \Q = 1'0 -Found init rule in `\SB_DFFE.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$254'. +Found init rule in `\SB_DFFE.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$280'. Set init value: \Q = 1'0 -Found init rule in `\SB_DFF.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$252'. +Found init rule in `\SB_DFF.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$278'. Set init value: \Q = 1'0 -Found init rule in `\fifo.$proc$fifo.v:0$82'. +Found init rule in `\fifo.$proc$fifo.v:0$108'. Set init value: \count = 9'000000000 -Found init rule in `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:0$466'. +Found init rule in `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:0$492'. Set init value: \addr = 8'00000000 yosys> proc_arst -16.3.5. Executing PROC_ARST pass (detect async resets in processes). -Found async reset \S in `\SB_DFFNES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1414$323'. -Found async reset \R in `\SB_DFFNER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1273$312'. -Found async reset \S in `\SB_DFFNS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1138$302'. -Found async reset \R in `\SB_DFFNR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1017$296'. -Found async reset \S in `\SB_DFFES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:803$285'. -Found async reset \R in `\SB_DFFER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:662$274'. -Found async reset \S in `\SB_DFFS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:527$264'. -Found async reset \R in `\SB_DFFR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:406$258'. -Found async reset \rst in `\fifo.$proc$fifo.v:64$75'. -Found async reset \rst in `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:13$463'. +22.3.5. Executing PROC_ARST pass (detect async resets in processes). +Found async reset \S in `\SB_DFFNES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1414$349'. +Found async reset \R in `\SB_DFFNER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1273$338'. +Found async reset \S in `\SB_DFFNS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1138$328'. +Found async reset \R in `\SB_DFFNR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1017$322'. +Found async reset \S in `\SB_DFFES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:803$311'. +Found async reset \R in `\SB_DFFER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:662$300'. +Found async reset \S in `\SB_DFFS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:527$290'. +Found async reset \R in `\SB_DFFR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:406$284'. +Found async reset \rst in `\fifo.$proc$fifo.v:64$101'. +Found async reset \rst in `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:13$489'. yosys> proc_rom -16.3.6. Executing PROC_ROM pass (convert switches to ROMs). +22.3.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. yosys> proc_mux -16.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). -Creating decoders for process `\SB_DFFNES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$326'. -Creating decoders for process `\SB_DFFNES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1414$323'. +22.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\SB_DFFNES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$352'. +Creating decoders for process `\SB_DFFNES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1414$349'. 1/1: $0\Q[0:0] -Creating decoders for process `\SB_DFFNESS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$322'. -Creating decoders for process `\SB_DFFNESS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1353$316'. +Creating decoders for process `\SB_DFFNESS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$348'. +Creating decoders for process `\SB_DFFNESS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1353$342'. 1/1: $0\Q[0:0] -Creating decoders for process `\SB_DFFNER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$315'. -Creating decoders for process `\SB_DFFNER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1273$312'. +Creating decoders for process `\SB_DFFNER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$341'. +Creating decoders for process `\SB_DFFNER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1273$338'. 1/1: $0\Q[0:0] -Creating decoders for process `\SB_DFFNESR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$311'. -Creating decoders for process `\SB_DFFNESR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1212$305'. +Creating decoders for process `\SB_DFFNESR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$337'. +Creating decoders for process `\SB_DFFNESR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1212$331'. 1/1: $0\Q[0:0] -Creating decoders for process `\SB_DFFNS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$304'. -Creating decoders for process `\SB_DFFNS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1138$302'. +Creating decoders for process `\SB_DFFNS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$330'. +Creating decoders for process `\SB_DFFNS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1138$328'. 1/1: $0\Q[0:0] -Creating decoders for process `\SB_DFFNSS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$301'. -Creating decoders for process `\SB_DFFNSS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1088$299'. +Creating decoders for process `\SB_DFFNSS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$327'. +Creating decoders for process `\SB_DFFNSS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1088$325'. 1/1: $0\Q[0:0] -Creating decoders for process `\SB_DFFNR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$298'. -Creating decoders for process `\SB_DFFNR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1017$296'. +Creating decoders for process `\SB_DFFNR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$324'. +Creating decoders for process `\SB_DFFNR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1017$322'. 1/1: $0\Q[0:0] -Creating decoders for process `\SB_DFFNSR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$295'. -Creating decoders for process `\SB_DFFNSR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:967$293'. +Creating decoders for process `\SB_DFFNSR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$321'. +Creating decoders for process `\SB_DFFNSR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:967$319'. 1/1: $0\Q[0:0] -Creating decoders for process `\SB_DFFNE.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$292'. -Creating decoders for process `\SB_DFFNE.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:922$291'. +Creating decoders for process `\SB_DFFNE.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$318'. +Creating decoders for process `\SB_DFFNE.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:922$317'. 1/1: $0\Q[0:0] -Creating decoders for process `\SB_DFFN.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$290'. -Creating decoders for process `\SB_DFFN.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:882$289'. -Creating decoders for process `\SB_DFFES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$288'. -Creating decoders for process `\SB_DFFES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:803$285'. +Creating decoders for process `\SB_DFFN.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$316'. +Creating decoders for process `\SB_DFFN.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:882$315'. +Creating decoders for process `\SB_DFFES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$314'. +Creating decoders for process `\SB_DFFES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:803$311'. 1/1: $0\Q[0:0] -Creating decoders for process `\SB_DFFESS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$284'. -Creating decoders for process `\SB_DFFESS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:742$278'. +Creating decoders for process `\SB_DFFESS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$310'. +Creating decoders for process `\SB_DFFESS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:742$304'. 1/1: $0\Q[0:0] -Creating decoders for process `\SB_DFFER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$277'. -Creating decoders for process `\SB_DFFER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:662$274'. +Creating decoders for process `\SB_DFFER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$303'. +Creating decoders for process `\SB_DFFER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:662$300'. 1/1: $0\Q[0:0] -Creating decoders for process `\SB_DFFESR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$273'. -Creating decoders for process `\SB_DFFESR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:601$267'. +Creating decoders for process `\SB_DFFESR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$299'. +Creating decoders for process `\SB_DFFESR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:601$293'. 1/1: $0\Q[0:0] -Creating decoders for process `\SB_DFFS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$266'. -Creating decoders for process `\SB_DFFS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:527$264'. +Creating decoders for process `\SB_DFFS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$292'. +Creating decoders for process `\SB_DFFS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:527$290'. 1/1: $0\Q[0:0] -Creating decoders for process `\SB_DFFSS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$263'. -Creating decoders for process `\SB_DFFSS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:477$261'. +Creating decoders for process `\SB_DFFSS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$289'. +Creating decoders for process `\SB_DFFSS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:477$287'. 1/1: $0\Q[0:0] -Creating decoders for process `\SB_DFFR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$260'. -Creating decoders for process `\SB_DFFR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:406$258'. +Creating decoders for process `\SB_DFFR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$286'. +Creating decoders for process `\SB_DFFR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:406$284'. 1/1: $0\Q[0:0] -Creating decoders for process `\SB_DFFSR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$257'. -Creating decoders for process `\SB_DFFSR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:356$255'. +Creating decoders for process `\SB_DFFSR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$283'. +Creating decoders for process `\SB_DFFSR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:356$281'. 1/1: $0\Q[0:0] -Creating decoders for process `\SB_DFFE.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$254'. -Creating decoders for process `\SB_DFFE.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:311$253'. +Creating decoders for process `\SB_DFFE.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$280'. +Creating decoders for process `\SB_DFFE.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:311$279'. 1/1: $0\Q[0:0] -Creating decoders for process `\SB_DFF.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$252'. -Creating decoders for process `\SB_DFF.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:271$251'. -Creating decoders for process `\fifo.$proc$fifo.v:0$82'. -Creating decoders for process `\fifo.$proc$fifo.v:64$75'. +Creating decoders for process `\SB_DFF.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$278'. +Creating decoders for process `\SB_DFF.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:271$277'. +Creating decoders for process `\fifo.$proc$fifo.v:0$108'. +Creating decoders for process `\fifo.$proc$fifo.v:64$101'. 1/1: $0\count[8:0] -Creating decoders for process `\fifo.$proc$fifo.v:38$67'. - 1/3: $1$memwr$\data$fifo.v:40$66_EN[7:0]$73 - 2/3: $1$memwr$\data$fifo.v:40$66_DATA[7:0]$72 - 3/3: $1$memwr$\data$fifo.v:40$66_ADDR[7:0]$71 -Creating decoders for process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:0$466'. -Creating decoders for process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:13$463'. +Creating decoders for process `\fifo.$proc$fifo.v:38$93'. + 1/3: $1$memwr$\data$fifo.v:40$92_EN[7:0]$97 + 2/3: $1$memwr$\data$fifo.v:40$92_DATA[7:0]$98 + 3/3: $1$memwr$\data$fifo.v:40$92_ADDR[7:0]$99 +Creating decoders for process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:0$492'. +Creating decoders for process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:13$489'. 1/1: $0\addr[7:0] yosys> proc_dlatch -16.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). +22.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). yosys> proc_dff -16.3.9. Executing PROC_DFF pass (convert process syncs to FFs). -Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1414$323'. - created $adff cell `$procdff$530' with negative edge clock and positive level reset. -Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1353$316'. - created $dff cell `$procdff$531' with negative edge clock. -Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1273$312'. - created $adff cell `$procdff$532' with negative edge clock and positive level reset. -Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1212$305'. - created $dff cell `$procdff$533' with negative edge clock. -Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1138$302'. - created $adff cell `$procdff$534' with negative edge clock and positive level reset. -Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1088$299'. - created $dff cell `$procdff$535' with negative edge clock. -Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1017$296'. - created $adff cell `$procdff$536' with negative edge clock and positive level reset. -Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:967$293'. - created $dff cell `$procdff$537' with negative edge clock. -Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:922$291'. - created $dff cell `$procdff$538' with negative edge clock. -Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:882$289'. - created $dff cell `$procdff$539' with negative edge clock. -Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:803$285'. - created $adff cell `$procdff$540' with positive edge clock and positive level reset. -Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:742$278'. - created $dff cell `$procdff$541' with positive edge clock. -Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:662$274'. - created $adff cell `$procdff$542' with positive edge clock and positive level reset. -Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:601$267'. - created $dff cell `$procdff$543' with positive edge clock. -Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:527$264'. - created $adff cell `$procdff$544' with positive edge clock and positive level reset. -Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:477$261'. - created $dff cell `$procdff$545' with positive edge clock. -Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:406$258'. - created $adff cell `$procdff$546' with positive edge clock and positive level reset. -Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:356$255'. - created $dff cell `$procdff$547' with positive edge clock. -Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:311$253'. - created $dff cell `$procdff$548' with positive edge clock. -Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:271$251'. - created $dff cell `$procdff$549' with positive edge clock. -Creating register for signal `\fifo.\count' using process `\fifo.$proc$fifo.v:64$75'. - created $adff cell `$procdff$550' with positive edge clock and positive level reset. -Creating register for signal `\fifo.\rdata' using process `\fifo.$proc$fifo.v:38$67'. - created $dff cell `$procdff$551' with positive edge clock. -Creating register for signal `\fifo.$memwr$\data$fifo.v:40$66_ADDR' using process `\fifo.$proc$fifo.v:38$67'. - created $dff cell `$procdff$552' with positive edge clock. -Creating register for signal `\fifo.$memwr$\data$fifo.v:40$66_DATA' using process `\fifo.$proc$fifo.v:38$67'. - created $dff cell `$procdff$553' with positive edge clock. -Creating register for signal `\fifo.$memwr$\data$fifo.v:40$66_EN' using process `\fifo.$proc$fifo.v:38$67'. - created $dff cell `$procdff$554' with positive edge clock. -Creating register for signal `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.\addr' using process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:13$463'. - created $adff cell `$procdff$555' with positive edge clock and positive level reset. +22.3.9. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1414$349'. + created $adff cell `$procdff$556' with negative edge clock and positive level reset. +Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1353$342'. + created $dff cell `$procdff$557' with negative edge clock. +Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1273$338'. + created $adff cell `$procdff$558' with negative edge clock and positive level reset. +Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1212$331'. + created $dff cell `$procdff$559' with negative edge clock. +Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1138$328'. + created $adff cell `$procdff$560' with negative edge clock and positive level reset. +Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1088$325'. + created $dff cell `$procdff$561' with negative edge clock. +Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1017$322'. + created $adff cell `$procdff$562' with negative edge clock and positive level reset. +Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:967$319'. + created $dff cell `$procdff$563' with negative edge clock. +Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:922$317'. + created $dff cell `$procdff$564' with negative edge clock. +Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:882$315'. + created $dff cell `$procdff$565' with negative edge clock. +Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:803$311'. + created $adff cell `$procdff$566' with positive edge clock and positive level reset. +Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:742$304'. + created $dff cell `$procdff$567' with positive edge clock. +Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:662$300'. + created $adff cell `$procdff$568' with positive edge clock and positive level reset. +Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:601$293'. + created $dff cell `$procdff$569' with positive edge clock. +Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:527$290'. + created $adff cell `$procdff$570' with positive edge clock and positive level reset. +Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:477$287'. + created $dff cell `$procdff$571' with positive edge clock. +Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:406$284'. + created $adff cell `$procdff$572' with positive edge clock and positive level reset. +Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:356$281'. + created $dff cell `$procdff$573' with positive edge clock. +Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:311$279'. + created $dff cell `$procdff$574' with positive edge clock. +Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:271$277'. + created $dff cell `$procdff$575' with positive edge clock. +Creating register for signal `\fifo.\count' using process `\fifo.$proc$fifo.v:64$101'. + created $adff cell `$procdff$576' with positive edge clock and positive level reset. +Creating register for signal `\fifo.\rdata' using process `\fifo.$proc$fifo.v:38$93'. + created $dff cell `$procdff$577' with positive edge clock. +Creating register for signal `\fifo.$memwr$\data$fifo.v:40$92_EN' using process `\fifo.$proc$fifo.v:38$93'. + created $dff cell `$procdff$578' with positive edge clock. +Creating register for signal `\fifo.$memwr$\data$fifo.v:40$92_DATA' using process `\fifo.$proc$fifo.v:38$93'. + created $dff cell `$procdff$579' with positive edge clock. +Creating register for signal `\fifo.$memwr$\data$fifo.v:40$92_ADDR' using process `\fifo.$proc$fifo.v:38$93'. + created $dff cell `$procdff$580' with positive edge clock. +Creating register for signal `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.\addr' using process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:13$489'. + created $adff cell `$procdff$581' with positive edge clock and positive level reset. yosys> proc_memwr -16.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). +22.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). yosys> proc_clean -16.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Removing empty process `SB_DFFNES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$326'. -Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1414$323'. -Removing empty process `SB_DFFNES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1414$323'. -Removing empty process `SB_DFFNESS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$322'. -Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1353$316'. -Removing empty process `SB_DFFNESS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1353$316'. -Removing empty process `SB_DFFNER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$315'. -Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1273$312'. -Removing empty process `SB_DFFNER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1273$312'. -Removing empty process `SB_DFFNESR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$311'. -Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1212$305'. -Removing empty process `SB_DFFNESR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1212$305'. -Removing empty process `SB_DFFNS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$304'. -Removing empty process `SB_DFFNS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1138$302'. -Removing empty process `SB_DFFNSS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$301'. -Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1088$299'. -Removing empty process `SB_DFFNSS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1088$299'. -Removing empty process `SB_DFFNR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$298'. -Removing empty process `SB_DFFNR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1017$296'. -Removing empty process `SB_DFFNSR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$295'. -Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:967$293'. -Removing empty process `SB_DFFNSR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:967$293'. -Removing empty process `SB_DFFNE.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$292'. -Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:922$291'. -Removing empty process `SB_DFFNE.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:922$291'. -Removing empty process `SB_DFFN.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$290'. -Removing empty process `SB_DFFN.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:882$289'. -Removing empty process `SB_DFFES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$288'. -Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:803$285'. -Removing empty process `SB_DFFES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:803$285'. -Removing empty process `SB_DFFESS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$284'. -Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:742$278'. -Removing empty process `SB_DFFESS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:742$278'. -Removing empty process `SB_DFFER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$277'. -Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:662$274'. -Removing empty process `SB_DFFER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:662$274'. -Removing empty process `SB_DFFESR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$273'. -Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:601$267'. -Removing empty process `SB_DFFESR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:601$267'. -Removing empty process `SB_DFFS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$266'. -Removing empty process `SB_DFFS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:527$264'. -Removing empty process `SB_DFFSS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$263'. -Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:477$261'. -Removing empty process `SB_DFFSS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:477$261'. -Removing empty process `SB_DFFR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$260'. -Removing empty process `SB_DFFR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:406$258'. -Removing empty process `SB_DFFSR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$257'. -Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:356$255'. -Removing empty process `SB_DFFSR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:356$255'. -Removing empty process `SB_DFFE.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$254'. -Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:311$253'. -Removing empty process `SB_DFFE.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:311$253'. -Removing empty process `SB_DFF.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$252'. -Removing empty process `SB_DFF.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:271$251'. -Removing empty process `fifo.$proc$fifo.v:0$82'. -Found and cleaned up 2 empty switches in `\fifo.$proc$fifo.v:64$75'. -Removing empty process `fifo.$proc$fifo.v:64$75'. -Found and cleaned up 1 empty switch in `\fifo.$proc$fifo.v:38$67'. -Removing empty process `fifo.$proc$fifo.v:38$67'. -Removing empty process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:0$466'. -Found and cleaned up 2 empty switches in `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:13$463'. -Removing empty process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:13$463'. +22.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Removing empty process `SB_DFFNES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$352'. +Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1414$349'. +Removing empty process `SB_DFFNES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1414$349'. +Removing empty process `SB_DFFNESS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$348'. +Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1353$342'. +Removing empty process `SB_DFFNESS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1353$342'. +Removing empty process `SB_DFFNER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$341'. +Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1273$338'. +Removing empty process `SB_DFFNER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1273$338'. +Removing empty process `SB_DFFNESR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$337'. +Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1212$331'. +Removing empty process `SB_DFFNESR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1212$331'. +Removing empty process `SB_DFFNS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$330'. +Removing empty process `SB_DFFNS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1138$328'. +Removing empty process `SB_DFFNSS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$327'. +Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1088$325'. +Removing empty process `SB_DFFNSS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1088$325'. +Removing empty process `SB_DFFNR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$324'. +Removing empty process `SB_DFFNR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:1017$322'. +Removing empty process `SB_DFFNSR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$321'. +Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:967$319'. +Removing empty process `SB_DFFNSR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:967$319'. +Removing empty process `SB_DFFNE.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$318'. +Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:922$317'. +Removing empty process `SB_DFFNE.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:922$317'. +Removing empty process `SB_DFFN.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$316'. +Removing empty process `SB_DFFN.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:882$315'. +Removing empty process `SB_DFFES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$314'. +Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:803$311'. +Removing empty process `SB_DFFES.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:803$311'. +Removing empty process `SB_DFFESS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$310'. +Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:742$304'. +Removing empty process `SB_DFFESS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:742$304'. +Removing empty process `SB_DFFER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$303'. +Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:662$300'. +Removing empty process `SB_DFFER.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:662$300'. +Removing empty process `SB_DFFESR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$299'. +Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:601$293'. +Removing empty process `SB_DFFESR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:601$293'. +Removing empty process `SB_DFFS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$292'. +Removing empty process `SB_DFFS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:527$290'. +Removing empty process `SB_DFFSS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$289'. +Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:477$287'. +Removing empty process `SB_DFFSS.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:477$287'. +Removing empty process `SB_DFFR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$286'. +Removing empty process `SB_DFFR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:406$284'. +Removing empty process `SB_DFFSR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$283'. +Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:356$281'. +Removing empty process `SB_DFFSR.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:356$281'. +Removing empty process `SB_DFFE.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$280'. +Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:311$279'. +Removing empty process `SB_DFFE.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:311$279'. +Removing empty process `SB_DFF.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:0$278'. +Removing empty process `SB_DFF.$proc$/home/dawn/yosys/share/ice40/cells_sim.v:271$277'. +Removing empty process `fifo.$proc$fifo.v:0$108'. +Found and cleaned up 2 empty switches in `\fifo.$proc$fifo.v:64$101'. +Removing empty process `fifo.$proc$fifo.v:64$101'. +Found and cleaned up 1 empty switch in `\fifo.$proc$fifo.v:38$93'. +Removing empty process `fifo.$proc$fifo.v:38$93'. +Removing empty process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:0$492'. +Found and cleaned up 2 empty switches in `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:13$489'. +Removing empty process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:13$489'. Cleaned up 23 empty switches. yosys> opt_expr -keepdc -16.3.12. Executing OPT_EXPR pass (perform const folding). +22.3.12. Executing OPT_EXPR pass (perform const folding). Optimizing module fifo. Optimizing module $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000. yosys> flatten -16.4. Executing FLATTEN pass (flatten design). +22.4. Executing FLATTEN pass (flatten design). Deleting now unused module $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000. yosys> tribuf -logic -16.5. Executing TRIBUF pass. +22.5. Executing TRIBUF pass. yosys> deminout -16.6. Executing DEMINOUT pass (demote inout ports to input or output). +22.6. Executing DEMINOUT pass (demote inout ports to input or output). yosys> opt_expr -16.7. Executing OPT_EXPR pass (perform const folding). +22.7. Executing OPT_EXPR pass (perform const folding). Optimizing module fifo. yosys> opt_clean -16.8. Executing OPT_CLEAN pass (remove unused cells and wires). +22.8. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \fifo.. Removed 3 unused cells and 25 unused wires. yosys> check -16.9. Executing CHECK pass (checking for obvious problems). +22.9. Executing CHECK pass (checking for obvious problems). Checking module fifo... Found and reported 0 problems. yosys> opt -nodffe -nosdff -16.10. Executing OPT pass (performing simple optimizations). +22.10. Executing OPT pass (performing simple optimizations). yosys> opt_expr -16.10.1. Executing OPT_EXPR pass (perform const folding). +22.10.1. Executing OPT_EXPR pass (perform const folding). Optimizing module fifo. yosys> opt_merge -nomux -16.10.2. Executing OPT_MERGE pass (detect identical cells). +22.10.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\fifo'. Removed a total of 0 cells. yosys> opt_muxtree -16.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +22.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \fifo.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. @@ -747,40 +809,40 @@ Removed 0 multiplexer ports. yosys> opt_reduce -16.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). +22.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \fifo. - Consolidated identical input bits for $mux cell $procmux$517: - Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\data$fifo.v:40$66_EN[7:0]$70 - New ports: A=1'0, B=1'1, Y=$0$memwr$\data$fifo.v:40$66_EN[7:0]$70 [0] - New connections: $0$memwr$\data$fifo.v:40$66_EN[7:0]$70 [7:1] = { $0$memwr$\data$fifo.v:40$66_EN[7:0]$70 [0] $0$memwr$\data$fifo.v:40$66_EN[7:0]$70 [0] $0$memwr$\data$fifo.v:40$66_EN[7:0]$70 [0] $0$memwr$\data$fifo.v:40$66_EN[7:0]$70 [0] $0$memwr$\data$fifo.v:40$66_EN[7:0]$70 [0] $0$memwr$\data$fifo.v:40$66_EN[7:0]$70 [0] $0$memwr$\data$fifo.v:40$66_EN[7:0]$70 [0] } + Consolidated identical input bits for $mux cell $procmux$543: + Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\data$fifo.v:40$92_EN[7:0]$94 + New ports: A=1'0, B=1'1, Y=$0$memwr$\data$fifo.v:40$92_EN[7:0]$94 [0] + New connections: $0$memwr$\data$fifo.v:40$92_EN[7:0]$94 [7:1] = { $0$memwr$\data$fifo.v:40$92_EN[7:0]$94 [0] $0$memwr$\data$fifo.v:40$92_EN[7:0]$94 [0] $0$memwr$\data$fifo.v:40$92_EN[7:0]$94 [0] $0$memwr$\data$fifo.v:40$92_EN[7:0]$94 [0] $0$memwr$\data$fifo.v:40$92_EN[7:0]$94 [0] $0$memwr$\data$fifo.v:40$92_EN[7:0]$94 [0] $0$memwr$\data$fifo.v:40$92_EN[7:0]$94 [0] } Optimizing cells in module \fifo. Performed a total of 1 changes. yosys> opt_merge -16.10.5. Executing OPT_MERGE pass (detect identical cells). +22.10.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\fifo'. Removed a total of 0 cells. yosys> opt_dff -nodffe -nosdff -16.10.6. Executing OPT_DFF pass (perform DFF optimizations). +22.10.6. Executing OPT_DFF pass (perform DFF optimizations). yosys> opt_clean -16.10.7. Executing OPT_CLEAN pass (remove unused cells and wires). +22.10.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \fifo.. yosys> opt_expr -16.10.8. Executing OPT_EXPR pass (perform const folding). +22.10.8. Executing OPT_EXPR pass (perform const folding). Optimizing module fifo. -16.10.9. Rerunning OPT passes. (Maybe there is more to do..) +22.10.9. Rerunning OPT passes. (Maybe there is more to do..) yosys> opt_muxtree -16.10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +22.10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \fifo.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. @@ -790,87 +852,87 @@ Removed 0 multiplexer ports. yosys> opt_reduce -16.10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). +22.10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \fifo. Performed a total of 0 changes. yosys> opt_merge -16.10.12. Executing OPT_MERGE pass (detect identical cells). +22.10.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\fifo'. Removed a total of 0 cells. yosys> opt_dff -nodffe -nosdff -16.10.13. Executing OPT_DFF pass (perform DFF optimizations). +22.10.13. Executing OPT_DFF pass (perform DFF optimizations). yosys> opt_clean -16.10.14. Executing OPT_CLEAN pass (remove unused cells and wires). +22.10.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \fifo.. yosys> opt_expr -16.10.15. Executing OPT_EXPR pass (perform const folding). +22.10.15. Executing OPT_EXPR pass (perform const folding). Optimizing module fifo. -16.10.16. Finished OPT passes. (There is nothing left to do.) +22.10.16. Finished OPT passes. (There is nothing left to do.) yosys> fsm -16.11. Executing FSM pass (extract and optimize FSM). +22.11. Executing FSM pass (extract and optimize FSM). yosys> fsm_detect -16.11.1. Executing FSM_DETECT pass (finding FSMs in design). +22.11.1. Executing FSM_DETECT pass (finding FSMs in design). yosys> fsm_extract -16.11.2. Executing FSM_EXTRACT pass (extracting FSM from design). +22.11.2. Executing FSM_EXTRACT pass (extracting FSM from design). yosys> fsm_opt -16.11.3. Executing FSM_OPT pass (simple optimizations of FSMs). +22.11.3. Executing FSM_OPT pass (simple optimizations of FSMs). yosys> opt_clean -16.11.4. Executing OPT_CLEAN pass (remove unused cells and wires). +22.11.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \fifo.. yosys> fsm_opt -16.11.5. Executing FSM_OPT pass (simple optimizations of FSMs). +22.11.5. Executing FSM_OPT pass (simple optimizations of FSMs). yosys> fsm_recode -16.11.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). +22.11.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). yosys> fsm_info -16.11.7. Executing FSM_INFO pass (dumping all available information on FSM cells). +22.11.7. Executing FSM_INFO pass (dumping all available information on FSM cells). yosys> fsm_map -16.11.8. Executing FSM_MAP pass (mapping FSMs to basic logic). +22.11.8. Executing FSM_MAP pass (mapping FSMs to basic logic). yosys> opt -16.12. Executing OPT pass (performing simple optimizations). +22.12. Executing OPT pass (performing simple optimizations). yosys> opt_expr -16.12.1. Executing OPT_EXPR pass (perform const folding). +22.12.1. Executing OPT_EXPR pass (perform const folding). Optimizing module fifo. yosys> opt_merge -nomux -16.12.2. Executing OPT_MERGE pass (detect identical cells). +22.12.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\fifo'. Removed a total of 0 cells. yosys> opt_muxtree -16.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +22.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \fifo.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. @@ -880,41 +942,41 @@ Removed 0 multiplexer ports. yosys> opt_reduce -16.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). +22.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \fifo. Performed a total of 0 changes. yosys> opt_merge -16.12.5. Executing OPT_MERGE pass (detect identical cells). +22.12.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\fifo'. Removed a total of 0 cells. yosys> opt_dff -16.12.6. Executing OPT_DFF pass (perform DFF optimizations). -Adding EN signal on $procdff$550 ($adff) from module fifo (D = $0\count[8:0], Q = \count). -Adding EN signal on $flatten\fifo_writer.$procdff$555 ($adff) from module fifo (D = $flatten\fifo_writer.$procmux$526_Y, Q = \fifo_writer.addr). -Adding EN signal on $flatten\fifo_reader.$procdff$555 ($adff) from module fifo (D = $flatten\fifo_reader.$procmux$526_Y, Q = \fifo_reader.addr). +22.12.6. Executing OPT_DFF pass (perform DFF optimizations). +Adding EN signal on $procdff$576 ($adff) from module fifo (D = $0\count[8:0], Q = \count). +Adding EN signal on $flatten\fifo_writer.$procdff$581 ($adff) from module fifo (D = $flatten\fifo_writer.$procmux$552_Y, Q = \fifo_writer.addr). +Adding EN signal on $flatten\fifo_reader.$procdff$581 ($adff) from module fifo (D = $flatten\fifo_reader.$procmux$552_Y, Q = \fifo_reader.addr). yosys> opt_clean -16.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). +22.12.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \fifo.. Removed 2 unused cells and 2 unused wires. yosys> opt_expr -16.12.8. Executing OPT_EXPR pass (perform const folding). +22.12.8. Executing OPT_EXPR pass (perform const folding). Optimizing module fifo. -16.12.9. Rerunning OPT passes. (Maybe there is more to do..) +22.12.9. Rerunning OPT passes. (Maybe there is more to do..) yosys> opt_muxtree -16.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +22.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \fifo.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. @@ -924,169 +986,120 @@ Removed 0 multiplexer ports. yosys> opt_reduce -16.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). +22.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \fifo. Performed a total of 0 changes. yosys> opt_merge -16.12.12. Executing OPT_MERGE pass (detect identical cells). +22.12.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\fifo'. Removed a total of 0 cells. yosys> opt_dff -16.12.13. Executing OPT_DFF pass (perform DFF optimizations). +22.12.13. Executing OPT_DFF pass (perform DFF optimizations). yosys> opt_clean -16.12.14. Executing OPT_CLEAN pass (remove unused cells and wires). +22.12.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \fifo.. yosys> opt_expr -16.12.15. Executing OPT_EXPR pass (perform const folding). +22.12.15. Executing OPT_EXPR pass (perform const folding). Optimizing module fifo. -16.12.16. Finished OPT passes. (There is nothing left to do.) +22.12.16. Finished OPT passes. (There is nothing left to do.) yosys> wreduce -16.13. Executing WREDUCE pass (reducing word size of cells). -Removed top 31 bits (of 32) from port B of cell fifo.$add$fifo.v:68$78 ($add). -Removed top 23 bits (of 32) from port Y of cell fifo.$add$fifo.v:68$78 ($add). -Removed top 31 bits (of 32) from port B of cell fifo.$sub$fifo.v:70$81 ($sub). -Removed top 23 bits (of 32) from port Y of cell fifo.$sub$fifo.v:70$81 ($sub). -Removed top 31 bits (of 32) from port B of cell fifo.$flatten\fifo_writer.$add$fifo.v:20$465 ($add). -Removed top 24 bits (of 32) from port Y of cell fifo.$flatten\fifo_writer.$add$fifo.v:20$465 ($add). -Removed top 31 bits (of 32) from port B of cell fifo.$flatten\fifo_reader.$add$fifo.v:20$465 ($add). -Removed top 24 bits (of 32) from port Y of cell fifo.$flatten\fifo_reader.$add$fifo.v:20$465 ($add). -Removed top 23 bits (of 32) from wire fifo.$add$fifo.v:68$78_Y. -Removed top 23 bits (of 32) from wire fifo.$sub$fifo.v:70$81_Y. +22.13. Executing WREDUCE pass (reducing word size of cells). +Removed top 31 bits (of 32) from port B of cell fifo.$sub$fifo.v:70$107 ($sub). +Removed top 23 bits (of 32) from port Y of cell fifo.$sub$fifo.v:70$107 ($sub). +Removed top 31 bits (of 32) from port B of cell fifo.$add$fifo.v:68$104 ($add). +Removed top 23 bits (of 32) from port Y of cell fifo.$add$fifo.v:68$104 ($add). +Removed top 31 bits (of 32) from port B of cell fifo.$flatten\fifo_writer.$add$fifo.v:20$491 ($add). +Removed top 24 bits (of 32) from port Y of cell fifo.$flatten\fifo_writer.$add$fifo.v:20$491 ($add). +Removed top 31 bits (of 32) from port B of cell fifo.$flatten\fifo_reader.$add$fifo.v:20$491 ($add). +Removed top 24 bits (of 32) from port Y of cell fifo.$flatten\fifo_reader.$add$fifo.v:20$491 ($add). +Removed top 23 bits (of 32) from wire fifo.$add$fifo.v:68$104_Y. +Removed top 23 bits (of 32) from wire fifo.$sub$fifo.v:70$107_Y. yosys> peepopt -16.14. Executing PEEPOPT pass (run peephole optimizers). +22.14. Executing PEEPOPT pass (run peephole optimizers). yosys> opt_clean -16.15. Executing OPT_CLEAN pass (remove unused cells and wires). +22.15. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \fifo.. Removed 0 unused cells and 2 unused wires. yosys> share -16.16. Executing SHARE pass (SAT-based resource sharing). +22.16. Executing SHARE pass (SAT-based resource sharing). yosys> techmap -map +/cmp2lut.v -D LUT_WIDTH=4 -16.17. Executing TECHMAP pass (map to technology primitives). +22.17. Executing TECHMAP pass (map to technology primitives). -16.17.1. Executing Verilog-2005 frontend: /home/dawn/yosys/share/cmp2lut.v +22.17.1. Executing Verilog-2005 frontend: /home/dawn/yosys/share/cmp2lut.v Parsing Verilog input from `/home/dawn/yosys/share/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. -16.17.2. Continuing TECHMAP pass. +22.17.2. Continuing TECHMAP pass. No more expansions possible. yosys> opt_expr -16.18. Executing OPT_EXPR pass (perform const folding). +22.18. Executing OPT_EXPR pass (perform const folding). Optimizing module fifo. yosys> opt_clean -16.19. Executing OPT_CLEAN pass (remove unused cells and wires). +22.19. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \fifo.. -yosys> memory_dff - -16.20. Executing MEMORY_DFF pass (merging $dff cells to $memrd). -Checking read port `\data'[0] in module `\fifo': merging output FF to cell. - Write port 0: non-transparent. - -yosys> wreduce t:$mul - -16.21. Executing WREDUCE pass (reducing word size of cells). - -yosys> techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 -D DSP_NAME=$__MUL16X16 - -16.22. Executing TECHMAP pass (map to technology primitives). - -16.22.1. Executing Verilog-2005 frontend: /home/dawn/yosys/share/mul2dsp.v -Parsing Verilog input from `/home/dawn/yosys/share/mul2dsp.v' to AST representation. -Generating RTLIL representation for module `\_80_mul'. -Generating RTLIL representation for module `\_90_soft_mul'. -Successfully finished Verilog frontend. - -16.22.2. Executing Verilog-2005 frontend: /home/dawn/yosys/share/ice40/dsp_map.v -Parsing Verilog input from `/home/dawn/yosys/share/ice40/dsp_map.v' to AST representation. -Generating RTLIL representation for module `\$__MUL16X16'. -Successfully finished Verilog frontend. - -16.22.3. Continuing TECHMAP pass. -No more expansions possible. - - -yosys> select a:mul2dsp - -yosys*> setattr -unset mul2dsp - -yosys*> opt_expr -fine - -16.23. Executing OPT_EXPR pass (perform const folding). - -yosys*> wreduce - -16.24. Executing WREDUCE pass (reducing word size of cells). - -yosys*> select -clear - -yosys> ice40_dsp - -16.25. Executing ICE40_DSP pass (map multipliers). - -yosys> chtype -set $mul t:$__soft_mul - yosys> alumacc -16.26. Executing ALUMACC pass (create $alu and $macc cells). +22.20. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module fifo: - creating $macc model for $add$fifo.v:68$78 ($add). - creating $macc model for $flatten\fifo_reader.$add$fifo.v:20$465 ($add). - creating $macc model for $flatten\fifo_writer.$add$fifo.v:20$465 ($add). - creating $macc model for $sub$fifo.v:70$81 ($sub). - creating $alu model for $macc $sub$fifo.v:70$81. - creating $alu model for $macc $flatten\fifo_writer.$add$fifo.v:20$465. - creating $alu model for $macc $flatten\fifo_reader.$add$fifo.v:20$465. - creating $alu model for $macc $add$fifo.v:68$78. - creating $alu cell for $add$fifo.v:68$78: $auto$alumacc.cc:485:replace_alu$574 - creating $alu cell for $flatten\fifo_reader.$add$fifo.v:20$465: $auto$alumacc.cc:485:replace_alu$577 - creating $alu cell for $flatten\fifo_writer.$add$fifo.v:20$465: $auto$alumacc.cc:485:replace_alu$580 - creating $alu cell for $sub$fifo.v:70$81: $auto$alumacc.cc:485:replace_alu$583 + creating $macc model for $add$fifo.v:68$104 ($add). + creating $macc model for $flatten\fifo_reader.$add$fifo.v:20$491 ($add). + creating $macc model for $flatten\fifo_writer.$add$fifo.v:20$491 ($add). + creating $macc model for $sub$fifo.v:70$107 ($sub). + creating $alu model for $macc $sub$fifo.v:70$107. + creating $alu model for $macc $flatten\fifo_writer.$add$fifo.v:20$491. + creating $alu model for $macc $flatten\fifo_reader.$add$fifo.v:20$491. + creating $alu model for $macc $add$fifo.v:68$104. + creating $alu cell for $add$fifo.v:68$104: $auto$alumacc.cc:485:replace_alu$591 + creating $alu cell for $flatten\fifo_reader.$add$fifo.v:20$491: $auto$alumacc.cc:485:replace_alu$594 + creating $alu cell for $flatten\fifo_writer.$add$fifo.v:20$491: $auto$alumacc.cc:485:replace_alu$597 + creating $alu cell for $sub$fifo.v:70$107: $auto$alumacc.cc:485:replace_alu$600 created 4 $alu and 0 $macc cells. yosys> opt -16.27. Executing OPT pass (performing simple optimizations). +22.21. Executing OPT pass (performing simple optimizations). yosys> opt_expr -16.27.1. Executing OPT_EXPR pass (perform const folding). +22.21.1. Executing OPT_EXPR pass (perform const folding). Optimizing module fifo. yosys> opt_merge -nomux -16.27.2. Executing OPT_MERGE pass (detect identical cells). +22.21.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\fifo'. Removed a total of 0 cells. yosys> opt_muxtree -16.27.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +22.21.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \fifo.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. @@ -1096,229 +1109,181 @@ Removed 0 multiplexer ports. yosys> opt_reduce -16.27.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). +22.21.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \fifo. Performed a total of 0 changes. yosys> opt_merge -16.27.5. Executing OPT_MERGE pass (detect identical cells). +22.21.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\fifo'. Removed a total of 0 cells. yosys> opt_dff -16.27.6. Executing OPT_DFF pass (perform DFF optimizations). +22.21.6. Executing OPT_DFF pass (perform DFF optimizations). yosys> opt_clean -16.27.7. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \fifo.. -Removed 1 unused cells and 9 unused wires. - - -yosys> opt_expr - -16.27.8. Executing OPT_EXPR pass (perform const folding). -Optimizing module fifo. - -16.27.9. Rerunning OPT passes. (Maybe there is more to do..) - -yosys> opt_muxtree - -16.27.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \fifo.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Removed 0 multiplexer ports. - - -yosys> opt_reduce - -16.27.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \fifo. -Performed a total of 0 changes. - -yosys> opt_merge - -16.27.12. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\fifo'. -Removed a total of 0 cells. - -yosys> opt_dff - -16.27.13. Executing OPT_DFF pass (perform DFF optimizations). - -yosys> opt_clean - -16.27.14. Executing OPT_CLEAN pass (remove unused cells and wires). +22.21.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \fifo.. yosys> opt_expr -16.27.15. Executing OPT_EXPR pass (perform const folding). +22.21.8. Executing OPT_EXPR pass (perform const folding). Optimizing module fifo. -16.27.16. Finished OPT passes. (There is nothing left to do.) +22.21.9. Finished OPT passes. (There is nothing left to do.) yosys> memory -nomap -16.28. Executing MEMORY pass. +22.22. Executing MEMORY pass. yosys> opt_mem -16.28.1. Executing OPT_MEM pass (optimize memories). +22.22.1. Executing OPT_MEM pass (optimize memories). Performed a total of 0 transformations. yosys> opt_mem_priority -16.28.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). +22.22.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. yosys> opt_mem_feedback -16.28.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). +22.22.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). + Analyzing fifo.data write port 0. yosys> memory_bmux2rom -16.28.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). +22.22.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). yosys> memory_dff -16.28.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). +22.22.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). +Checking read port `\data'[0] in module `\fifo': merging output FF to cell. + Write port 0: non-transparent. yosys> opt_clean -16.28.6. Executing OPT_CLEAN pass (remove unused cells and wires). +22.22.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \fifo.. +Removed 1 unused cells and 9 unused wires. + yosys> memory_share -16.28.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). +22.22.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). yosys> opt_mem_widen -16.28.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). +22.22.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. yosys> opt_clean -16.28.9. Executing OPT_CLEAN pass (remove unused cells and wires). +22.22.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \fifo.. yosys> memory_collect -16.28.10. Executing MEMORY_COLLECT pass (generating $mem cells). +22.22.10. Executing MEMORY_COLLECT pass (generating $mem cells). yosys> opt_clean -16.29. Executing OPT_CLEAN pass (remove unused cells and wires). +22.23. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \fifo.. -yosys> memory_libmap -lib +/ice40/brams.txt -lib +/ice40/spram.txt -no-auto-huge +yosys> select -set new_cells t:$mem_v2 -16.30. Executing MEMORY_LIBMAP pass (mapping memories to cells). +yosys> select -set rdata_path @new_cells %ci*:-$mem_v2[WR_DATA,WR_ADDR,WR_EN] @new_cells %co* %% + +yosys> show -color maroon3 @new_cells -notitle -format dot -prefix rdata_coarse @rdata_path + +23. Generating Graphviz representation of design. +Writing dot description to `rdata_coarse.dot'. +Dumping selected parts of module fifo to page 1. + +yosys> echo off +echo off + +24. Executing SYNTH_ICE40 pass. + +24.1. Executing MEMORY_LIBMAP pass (mapping memories to cells). mapping memory fifo.data via $__ICE40_RAM4K_ -yosys> techmap -map +/ice40/brams_map.v -map +/ice40/spram_map.v +24.2. Executing TECHMAP pass (map to technology primitives). -16.31. Executing TECHMAP pass (map to technology primitives). - -16.31.1. Executing Verilog-2005 frontend: /home/dawn/yosys/share/ice40/brams_map.v +24.2.1. Executing Verilog-2005 frontend: /home/dawn/yosys/share/ice40/brams_map.v Parsing Verilog input from `/home/dawn/yosys/share/ice40/brams_map.v' to AST representation. Generating RTLIL representation for module `\$__ICE40_RAM4K_'. Successfully finished Verilog frontend. -16.31.2. Executing Verilog-2005 frontend: /home/dawn/yosys/share/ice40/spram_map.v +24.2.2. Executing Verilog-2005 frontend: /home/dawn/yosys/share/ice40/spram_map.v Parsing Verilog input from `/home/dawn/yosys/share/ice40/spram_map.v' to AST representation. Generating RTLIL representation for module `\$__ICE40_SPRAM_'. Successfully finished Verilog frontend. -16.31.3. Continuing TECHMAP pass. +24.2.3. Continuing TECHMAP pass. Using template $paramod$13b3947419e62b7bbba1b93c77e4155efbe69a94\$__ICE40_RAM4K_ for cells of type $__ICE40_RAM4K_. No more expansions possible. -yosys> ice40_braminit +24.3. Executing ICE40_BRAMINIT pass. -16.32. Executing ICE40_BRAMINIT pass. +25. Generating Graphviz representation of design. +Writing dot description to `rdata_map_ram.dot'. +Dumping selected parts of module fifo to page 1. -yosys> opt -fast -mux_undef -undriven -fine +26. Executing SYNTH_ICE40 pass. -16.33. Executing OPT pass (performing simple optimizations). +26.1. Executing OPT pass (performing simple optimizations). -yosys> opt_expr -mux_undef -undriven -fine - -16.33.1. Executing OPT_EXPR pass (perform const folding). +26.1.1. Executing OPT_EXPR pass (perform const folding). Optimizing module fifo. -yosys> opt_merge - -16.33.2. Executing OPT_MERGE pass (detect identical cells). +26.1.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\fifo'. Removed a total of 0 cells. -yosys> opt_dff +26.1.3. Executing OPT_DFF pass (perform DFF optimizations). +Removing always-active EN on $auto$mem.cc:1146:emulate_transparency$619 ($dffe) from module fifo. -16.33.3. Executing OPT_DFF pass (perform DFF optimizations). -Removing always-active EN on $auto$mem.cc:1146:emulate_transparency$593 ($dffe) from module fifo. - -yosys> opt_clean - -16.33.4. Executing OPT_CLEAN pass (remove unused cells and wires). +26.1.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \fifo.. Removed 0 unused cells and 18 unused wires. -16.33.5. Rerunning OPT passes. (Removed registers in this run.) +26.1.5. Rerunning OPT passes. (Removed registers in this run.) -yosys> opt_expr -mux_undef -undriven -fine - -16.33.6. Executing OPT_EXPR pass (perform const folding). +26.1.6. Executing OPT_EXPR pass (perform const folding). Optimizing module fifo. -yosys> opt_merge - -16.33.7. Executing OPT_MERGE pass (detect identical cells). +26.1.7. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\fifo'. Removed a total of 0 cells. -yosys> opt_dff +26.1.8. Executing OPT_DFF pass (perform DFF optimizations). -16.33.8. Executing OPT_DFF pass (perform DFF optimizations). - -yosys> opt_clean - -16.33.9. Executing OPT_CLEAN pass (remove unused cells and wires). +26.1.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \fifo.. -16.33.10. Finished fast OPT passes. +26.1.10. Finished fast OPT passes. -yosys> memory_map +26.2. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). -16.34. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). +26.3. Executing OPT pass (performing simple optimizations). -yosys> opt -undriven -fine - -16.35. Executing OPT pass (performing simple optimizations). - -yosys> opt_expr -undriven -fine - -16.35.1. Executing OPT_EXPR pass (perform const folding). +26.3.1. Executing OPT_EXPR pass (perform const folding). Optimizing module fifo. -yosys> opt_merge -nomux - -16.35.2. Executing OPT_MERGE pass (detect identical cells). +26.3.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\fifo'. Removed a total of 0 cells. -yosys> opt_muxtree - -16.35.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +26.3.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \fifo.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. @@ -1326,43 +1291,35 @@ Running muxtree optimizer on module \fifo.. Removed 0 multiplexer ports. -yosys> opt_reduce -fine - -16.35.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). +26.3.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \fifo. Performed a total of 0 changes. -yosys> opt_merge - -16.35.5. Executing OPT_MERGE pass (detect identical cells). +26.3.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\fifo'. Removed a total of 0 cells. -yosys> opt_dff +26.3.6. Executing OPT_DFF pass (perform DFF optimizations). -16.35.6. Executing OPT_DFF pass (perform DFF optimizations). - -yosys> opt_clean - -16.35.7. Executing OPT_CLEAN pass (remove unused cells and wires). +26.3.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \fifo.. -yosys> opt_expr -undriven -fine - -16.35.8. Executing OPT_EXPR pass (perform const folding). +26.3.8. Executing OPT_EXPR pass (perform const folding). Optimizing module fifo. -16.35.9. Finished OPT passes. (There is nothing left to do.) +26.3.9. Finished OPT passes. (There is nothing left to do.) -yosys> ice40_wrapcarry +27. Generating Graphviz representation of design. +Writing dot description to `rdata_map_ffram.dot'. +Dumping selected parts of module fifo to page 1. -16.36. Executing ICE40_WRAPCARRY pass (wrap carries). +28. Executing SYNTH_ICE40 pass. -yosys> techmap -map +/techmap.v -map +/ice40/arith_map.v +28.1. Executing ICE40_WRAPCARRY pass (wrap carries). -16.37. Executing TECHMAP pass (map to technology primitives). +28.2. Executing TECHMAP pass (map to technology primitives). -16.37.1. Executing Verilog-2005 frontend: /home/dawn/yosys/share/techmap.v +28.2.1. Executing Verilog-2005 frontend: /home/dawn/yosys/share/techmap.v Parsing Verilog input from `/home/dawn/yosys/share/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. @@ -1390,124 +1347,98 @@ Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. -16.37.2. Executing Verilog-2005 frontend: /home/dawn/yosys/share/ice40/arith_map.v +28.2.2. Executing Verilog-2005 frontend: /home/dawn/yosys/share/ice40/arith_map.v Parsing Verilog input from `/home/dawn/yosys/share/ice40/arith_map.v' to AST representation. Generating RTLIL representation for module `\_80_ice40_alu'. Successfully finished Verilog frontend. -16.37.3. Continuing TECHMAP pass. -Using template $paramod$c3cd1564c35d873179656addd6052d7ea8b6d991\_80_ice40_alu for cells of type $alu. +28.2.3. Continuing TECHMAP pass. +Using extmapper simplemap for cells of type $adffe. +Using template $paramod$53700bbee849b2010ad0b60a61ccd204a10e24ca\_80_ice40_alu for cells of type $alu. Using extmapper simplemap for cells of type $dff. Using extmapper simplemap for cells of type $logic_not. Using extmapper simplemap for cells of type $logic_and. +Using template $paramod$c3cd1564c35d873179656addd6052d7ea8b6d991\_80_ice40_alu for cells of type $alu. +Using extmapper simplemap for cells of type $reduce_bool. Using extmapper simplemap for cells of type $mux. +Using template $paramod$6f67705c43e5e94c02b6ebb52209ce5aa5ade4c1\_80_ice40_alu for cells of type $alu. Using extmapper simplemap for cells of type $eq. Using extmapper simplemap for cells of type $and. -Using extmapper simplemap for cells of type $adffe. -Using template $paramod$53700bbee849b2010ad0b60a61ccd204a10e24ca\_80_ice40_alu for cells of type $alu. -Using extmapper simplemap for cells of type $reduce_bool. -Using template $paramod$6f67705c43e5e94c02b6ebb52209ce5aa5ade4c1\_80_ice40_alu for cells of type $alu. Using extmapper simplemap for cells of type $xor. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $pos. No more expansions possible. -yosys> opt -fast +28.3. Executing OPT pass (performing simple optimizations). -16.38. Executing OPT pass (performing simple optimizations). - -yosys> opt_expr - -16.38.1. Executing OPT_EXPR pass (perform const folding). +28.3.1. Executing OPT_EXPR pass (perform const folding). Optimizing module fifo. -yosys> opt_merge - -16.38.2. Executing OPT_MERGE pass (detect identical cells). +28.3.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\fifo'. Removed a total of 27 cells. -yosys> opt_dff +28.3.3. Executing OPT_DFF pass (perform DFF optimizations). -16.38.3. Executing OPT_DFF pass (perform DFF optimizations). - -yosys> opt_clean - -16.38.4. Executing OPT_CLEAN pass (remove unused cells and wires). +28.3.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \fifo.. Removed 11 unused cells and 83 unused wires. -16.38.5. Finished fast OPT passes. +28.3.5. Finished fast OPT passes. -yosys> ice40_opt +28.4. Executing ICE40_OPT pass (performing simple optimizations). -16.39. Executing ICE40_OPT pass (performing simple optimizations). +28.4.1. Running ICE40 specific optimizations. +Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) fifo.$auto$alumacc.cc:485:replace_alu$591.slice[0].carry: CO=\count [0] +Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) fifo.$auto$alumacc.cc:485:replace_alu$594.slice[0].carry: CO=\fifo_reader.addr [0] +Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) fifo.$auto$alumacc.cc:485:replace_alu$597.slice[0].carry: CO=\fifo_writer.addr [0] +Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) fifo.$auto$alumacc.cc:485:replace_alu$600.slice[0].carry: CO=\count [0] -16.39.1. Running ICE40 specific optimizations. -Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) fifo.$auto$alumacc.cc:485:replace_alu$574.slice[0].carry: CO=\count [0] -Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) fifo.$auto$alumacc.cc:485:replace_alu$577.slice[0].carry: CO=\fifo_reader.addr [0] -Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) fifo.$auto$alumacc.cc:485:replace_alu$580.slice[0].carry: CO=\fifo_writer.addr [0] -Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) fifo.$auto$alumacc.cc:485:replace_alu$583.slice[0].carry: CO=\count [0] - -yosys> opt_expr -mux_undef -undriven - -16.39.2. Executing OPT_EXPR pass (perform const folding). +28.4.2. Executing OPT_EXPR pass (perform const folding). Optimizing module fifo. -yosys> opt_merge - -16.39.3. Executing OPT_MERGE pass (detect identical cells). +28.4.3. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\fifo'. Removed a total of 0 cells. -yosys> opt_dff +28.4.4. Executing OPT_DFF pass (perform DFF optimizations). -16.39.4. Executing OPT_DFF pass (perform DFF optimizations). - -yosys> opt_clean - -16.39.5. Executing OPT_CLEAN pass (remove unused cells and wires). +28.4.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \fifo.. -16.39.6. Rerunning OPT passes. (Removed registers in this run.) +28.4.6. Rerunning OPT passes. (Removed registers in this run.) -16.39.7. Running ICE40 specific optimizations. +28.4.7. Running ICE40 specific optimizations. -yosys> opt_expr -mux_undef -undriven - -16.39.8. Executing OPT_EXPR pass (perform const folding). +28.4.8. Executing OPT_EXPR pass (perform const folding). Optimizing module fifo. -yosys> opt_merge - -16.39.9. Executing OPT_MERGE pass (detect identical cells). +28.4.9. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\fifo'. Removed a total of 0 cells. -yosys> opt_dff +28.4.10. Executing OPT_DFF pass (perform DFF optimizations). -16.39.10. Executing OPT_DFF pass (perform DFF optimizations). - -yosys> opt_clean - -16.39.11. Executing OPT_CLEAN pass (remove unused cells and wires). +28.4.11. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \fifo.. -16.39.12. Finished OPT passes. (There is nothing left to do.) +28.4.12. Finished OPT passes. (There is nothing left to do.) -yosys> dfflegalize -cell $_DFF_?_ 0 -cell $_DFFE_?P_ 0 -cell $_DFF_?P?_ 0 -cell $_DFFE_?P?P_ 0 -cell $_SDFF_?P?_ 0 -cell $_SDFFCE_?P?P_ 0 -cell $_DLATCH_?_ x -mince -1 +29. Generating Graphviz representation of design. +Writing dot description to `rdata_map_gates.dot'. +Dumping selected parts of module fifo to page 1. -16.40. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). +30. Executing SYNTH_ICE40 pass. -yosys> techmap -map +/ice40/ff_map.v +30.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). -16.41. Executing TECHMAP pass (map to technology primitives). +30.2. Executing TECHMAP pass (map to technology primitives). -16.41.1. Executing Verilog-2005 frontend: /home/dawn/yosys/share/ice40/ff_map.v +30.2.1. Executing Verilog-2005 frontend: /home/dawn/yosys/share/ice40/ff_map.v Parsing Verilog input from `/home/dawn/yosys/share/ice40/ff_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. @@ -1531,218 +1462,146 @@ Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. Successfully finished Verilog frontend. -16.41.2. Continuing TECHMAP pass. -Using template \$_DFFE_PP0P_ for cells of type $_DFFE_PP0P_. +30.2.2. Continuing TECHMAP pass. Using template \$_DFF_P_ for cells of type $_DFF_P_. +Using template \$_DFFE_PP0P_ for cells of type $_DFFE_PP0P_. No more expansions possible. -yosys> opt_expr -mux_undef - -16.42. Executing OPT_EXPR pass (perform const folding). +30.3. Executing OPT_EXPR pass (perform const folding). Optimizing module fifo. -yosys> simplemap +30.4. Executing SIMPLEMAP pass (map simple cells to gate primitives). +Mapping fifo.$auto$alumacc.cc:485:replace_alu$594.slice[0].carry ($lut). +Mapping fifo.$auto$alumacc.cc:485:replace_alu$597.slice[0].carry ($lut). +Mapping fifo.$auto$alumacc.cc:485:replace_alu$600.slice[0].carry ($lut). +Mapping fifo.$auto$alumacc.cc:485:replace_alu$591.slice[0].carry ($lut). -16.43. Executing SIMPLEMAP pass (map simple cells to gate primitives). -Mapping fifo.$auto$alumacc.cc:485:replace_alu$577.slice[0].carry ($lut). -Mapping fifo.$auto$alumacc.cc:485:replace_alu$580.slice[0].carry ($lut). -Mapping fifo.$auto$alumacc.cc:485:replace_alu$583.slice[0].carry ($lut). -Mapping fifo.$auto$alumacc.cc:485:replace_alu$574.slice[0].carry ($lut). +30.5. Executing ICE40_OPT pass (performing simple optimizations). -yosys> ice40_opt -full +30.5.1. Running ICE40 specific optimizations. -16.44. Executing ICE40_OPT pass (performing simple optimizations). - -16.44.1. Running ICE40 specific optimizations. - -yosys> opt_expr -mux_undef -undriven -full - -16.44.2. Executing OPT_EXPR pass (perform const folding). +30.5.2. Executing OPT_EXPR pass (perform const folding). Optimizing module fifo. -yosys> opt_merge - -16.44.3. Executing OPT_MERGE pass (detect identical cells). +30.5.3. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\fifo'. Removed a total of 4 cells. -yosys> opt_dff +30.5.4. Executing OPT_DFF pass (perform DFF optimizations). -16.44.4. Executing OPT_DFF pass (perform DFF optimizations). - -yosys> opt_clean - -16.44.5. Executing OPT_CLEAN pass (remove unused cells and wires). +30.5.5. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \fifo.. Removed 0 unused cells and 270 unused wires. -16.44.6. Rerunning OPT passes. (Removed registers in this run.) +30.5.6. Rerunning OPT passes. (Removed registers in this run.) -16.44.7. Running ICE40 specific optimizations. +30.5.7. Running ICE40 specific optimizations. -yosys> opt_expr -mux_undef -undriven -full - -16.44.8. Executing OPT_EXPR pass (perform const folding). +30.5.8. Executing OPT_EXPR pass (perform const folding). Optimizing module fifo. -yosys> opt_merge - -16.44.9. Executing OPT_MERGE pass (detect identical cells). +30.5.9. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\fifo'. Removed a total of 0 cells. -yosys> opt_dff +30.5.10. Executing OPT_DFF pass (perform DFF optimizations). -16.44.10. Executing OPT_DFF pass (perform DFF optimizations). - -yosys> opt_clean - -16.44.11. Executing OPT_CLEAN pass (remove unused cells and wires). +30.5.11. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \fifo.. -16.44.12. Rerunning OPT passes. (Removed registers in this run.) +30.5.12. Rerunning OPT passes. (Removed registers in this run.) -16.44.13. Running ICE40 specific optimizations. +30.5.13. Running ICE40 specific optimizations. -yosys> opt_expr -mux_undef -undriven -full - -16.44.14. Executing OPT_EXPR pass (perform const folding). +30.5.14. Executing OPT_EXPR pass (perform const folding). Optimizing module fifo. -yosys> opt_merge - -16.44.15. Executing OPT_MERGE pass (detect identical cells). +30.5.15. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\fifo'. Removed a total of 0 cells. -yosys> opt_dff +30.5.16. Executing OPT_DFF pass (perform DFF optimizations). -16.44.16. Executing OPT_DFF pass (perform DFF optimizations). - -yosys> opt_clean - -16.44.17. Executing OPT_CLEAN pass (remove unused cells and wires). +30.5.17. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \fifo.. -16.44.18. Finished OPT passes. (There is nothing left to do.) +30.5.18. Finished OPT passes. (There is nothing left to do.) -yosys> techmap -map +/ice40/latches_map.v +31. Generating Graphviz representation of design. +Writing dot description to `rdata_map_ffs.dot'. +Dumping selected parts of module fifo to page 1. -16.45. Executing TECHMAP pass (map to technology primitives). +32. Executing SYNTH_ICE40 pass. -16.45.1. Executing Verilog-2005 frontend: /home/dawn/yosys/share/ice40/latches_map.v +32.1. Executing TECHMAP pass (map to technology primitives). + +32.1.1. Executing Verilog-2005 frontend: /home/dawn/yosys/share/ice40/latches_map.v Parsing Verilog input from `/home/dawn/yosys/share/ice40/latches_map.v' to AST representation. Generating RTLIL representation for module `\$_DLATCH_N_'. Generating RTLIL representation for module `\$_DLATCH_P_'. Successfully finished Verilog frontend. -16.45.2. Continuing TECHMAP pass. +32.1.2. Continuing TECHMAP pass. No more expansions possible. -yosys> read_verilog -D ICE40_HX -icells -lib -specify +/ice40/abc9_model.v - -16.46. Executing Verilog-2005 frontend: /home/dawn/yosys/share/ice40/abc9_model.v +32.2. Executing Verilog-2005 frontend: /home/dawn/yosys/share/ice40/abc9_model.v Parsing Verilog input from `/home/dawn/yosys/share/ice40/abc9_model.v' to AST representation. Generating RTLIL representation for module `$__ICE40_CARRY_WRAPPER'. Successfully finished Verilog frontend. -yosys> abc9 -W 250 +32.3. Executing ABC9 pass. -16.47. Executing ABC9 pass. +32.3.1. Executing ABC9_OPS pass (helper functions for ABC9). -yosys> abc9_ops -check +32.3.2. Executing ABC9_OPS pass (helper functions for ABC9). -16.47.1. Executing ABC9_OPS pass (helper functions for ABC9). - -yosys> abc9_ops -prep_hier - -16.47.2. Executing ABC9_OPS pass (helper functions for ABC9). - -yosys> scc -specify -set_attr abc9_scc_id {} - -16.47.3. Executing SCC pass (detecting logic loops). +32.3.3. Executing SCC pass (detecting logic loops). Found 0 SCCs in module fifo. Found 0 SCCs. -yosys> abc9_ops -prep_bypass +32.3.4. Executing ABC9_OPS pass (helper functions for ABC9). -16.47.4. Executing ABC9_OPS pass (helper functions for ABC9). +32.3.5. Executing PROC pass (convert processes to netlists). -yosys> design -stash $abc9 - -yosys> design -load $abc9_map - -yosys> proc - -16.47.5. Executing PROC pass (convert processes to netlists). - -yosys> proc_clean - -16.47.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +32.3.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. -yosys> proc_rmdead - -16.47.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +32.3.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. -yosys> proc_prune - -16.47.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +32.3.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. -yosys> proc_init +32.3.5.4. Executing PROC_INIT pass (extract init attributes). -16.47.5.4. Executing PROC_INIT pass (extract init attributes). +32.3.5.5. Executing PROC_ARST pass (detect async resets in processes). -yosys> proc_arst - -16.47.5.5. Executing PROC_ARST pass (detect async resets in processes). - -yosys> proc_rom - -16.47.5.6. Executing PROC_ROM pass (convert switches to ROMs). +32.3.5.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. -yosys> proc_mux +32.3.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers). -16.47.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers). +32.3.5.8. Executing PROC_DLATCH pass (convert process syncs to latches). -yosys> proc_dlatch +32.3.5.9. Executing PROC_DFF pass (convert process syncs to FFs). -16.47.5.8. Executing PROC_DLATCH pass (convert process syncs to latches). +32.3.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells). -yosys> proc_dff - -16.47.5.9. Executing PROC_DFF pass (convert process syncs to FFs). - -yosys> proc_memwr - -16.47.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells). - -yosys> proc_clean - -16.47.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). +32.3.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. -yosys> opt_expr -keepdc +32.3.5.12. Executing OPT_EXPR pass (perform const folding). -16.47.5.12. Executing OPT_EXPR pass (perform const folding). +32.3.6. Executing TECHMAP pass (map to technology primitives). -yosys> wbflip - -yosys> techmap -wb -map %$abc9 -map +/techmap.v A:abc9_flop - -16.47.6. Executing TECHMAP pass (map to technology primitives). - -16.47.6.1. Executing Verilog-2005 frontend: /home/dawn/yosys/share/techmap.v +32.3.6.1. Executing Verilog-2005 frontend: /home/dawn/yosys/share/techmap.v Parsing Verilog input from `/home/dawn/yosys/share/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. @@ -1770,85 +1629,55 @@ Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. -16.47.6.2. Continuing TECHMAP pass. +32.3.6.2. Continuing TECHMAP pass. No more expansions possible. -yosys> opt -nodffe -nosdff +32.3.7. Executing OPT pass (performing simple optimizations). -16.47.7. Executing OPT pass (performing simple optimizations). - -yosys> opt_expr - -16.47.7.1. Executing OPT_EXPR pass (perform const folding). +32.3.7.1. Executing OPT_EXPR pass (perform const folding). Optimizing module SB_DFFER. -yosys> opt_merge -nomux - -16.47.7.2. Executing OPT_MERGE pass (detect identical cells). +32.3.7.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\SB_DFFER'. Removed a total of 0 cells. -yosys> opt_muxtree - -16.47.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +32.3.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \SB_DFFER.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. -yosys> opt_reduce - -16.47.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). +32.3.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \SB_DFFER. Performed a total of 0 changes. -yosys> opt_merge - -16.47.7.5. Executing OPT_MERGE pass (detect identical cells). +32.3.7.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\SB_DFFER'. Removed a total of 0 cells. -yosys> opt_dff -nodffe -nosdff +32.3.7.6. Executing OPT_DFF pass (perform DFF optimizations). -16.47.7.6. Executing OPT_DFF pass (perform DFF optimizations). - -yosys> opt_clean - -16.47.7.7. Executing OPT_CLEAN pass (remove unused cells and wires). +32.3.7.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \SB_DFFER.. -yosys> opt_expr - -16.47.7.8. Executing OPT_EXPR pass (perform const folding). +32.3.7.8. Executing OPT_EXPR pass (perform const folding). Optimizing module SB_DFFER. -16.47.7.9. Finished OPT passes. (There is nothing left to do.) +32.3.7.9. Finished OPT passes. (There is nothing left to do.) -yosys> design -stash $abc9_map +32.3.8. Executing TECHMAP pass (map to technology primitives). -yosys> design -load $abc9 - -yosys> design -delete $abc9 - -yosys> techmap -wb -max_iter 1 -map %$abc9_map -map +/abc9_map.v a:abc9_scc_id %n - -16.47.8. Executing TECHMAP pass (map to technology primitives). - -16.47.8.1. Executing Verilog-2005 frontend: /home/dawn/yosys/share/abc9_map.v +32.3.8.1. Executing Verilog-2005 frontend: /home/dawn/yosys/share/abc9_map.v Parsing Verilog input from `/home/dawn/yosys/share/abc9_map.v' to AST representation. Successfully finished Verilog frontend. -16.47.8.2. Continuing TECHMAP pass. +32.3.8.2. Continuing TECHMAP pass. Using template SB_DFFER for cells of type SB_DFFER. No more expansions possible. -yosys> design -delete $abc9_map - -yosys> read_verilog -icells -lib -specify +/abc9_model.v - -16.47.9. Executing Verilog-2005 frontend: /home/dawn/yosys/share/abc9_model.v +32.3.9. Executing Verilog-2005 frontend: /home/dawn/yosys/share/abc9_model.v Parsing Verilog input from `/home/dawn/yosys/share/abc9_model.v' to AST representation. Generating RTLIL representation for module `$__ABC9_DELAY'. Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. @@ -1856,29 +1685,17 @@ Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. Successfully finished Verilog frontend. -yosys> abc9_ops -break_scc -prep_delays -prep_xaiger - -16.47.10. Executing ABC9_OPS pass (helper functions for ABC9). +32.3.10. Executing ABC9_OPS pass (helper functions for ABC9). -yosys> abc9_ops -prep_lut 0 +32.3.11. Executing ABC9_OPS pass (helper functions for ABC9). -16.47.11. Executing ABC9_OPS pass (helper functions for ABC9). - -yosys> abc9_ops -prep_box - -16.47.12. Executing ABC9_OPS pass (helper functions for ABC9). +32.3.12. Executing ABC9_OPS pass (helper functions for ABC9). -yosys> design -stash $abc9 +32.3.13. Executing TECHMAP pass (map to technology primitives). -yosys> design -load $abc9_holes - -yosys> techmap -wb -map %$abc9 -map +/techmap.v - -16.47.13. Executing TECHMAP pass (map to technology primitives). - -16.47.13.1. Executing Verilog-2005 frontend: /home/dawn/yosys/share/techmap.v +32.3.13.1. Executing Verilog-2005 frontend: /home/dawn/yosys/share/techmap.v Parsing Verilog input from `/home/dawn/yosys/share/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. @@ -1906,7 +1723,7 @@ Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. -16.47.13.2. Continuing TECHMAP pass. +32.3.13.2. Continuing TECHMAP pass. Using template $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1 for cells of type $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1. Using template $paramod\SB_LUT4\LUT_INIT=16'0110100110010110 for cells of type SB_LUT4. Using template SB_CARRY for cells of type SB_CARRY. @@ -1916,100 +1733,68 @@ Using extmapper simplemap for cells of type $logic_or. No more expansions possible. -yosys> opt -purge +32.3.14. Executing OPT pass (performing simple optimizations). -16.47.14. Executing OPT pass (performing simple optimizations). - -yosys> opt_expr - -16.47.14.1. Executing OPT_EXPR pass (perform const folding). +32.3.14.1. Executing OPT_EXPR pass (perform const folding). Optimizing module fifo. -yosys> opt_merge -nomux - -16.47.14.2. Executing OPT_MERGE pass (detect identical cells). +32.3.14.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\fifo'. Removed a total of 12 cells. -yosys> opt_muxtree - -16.47.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +32.3.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \fifo.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. -yosys> opt_reduce - -16.47.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). +32.3.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \fifo. Performed a total of 0 changes. -yosys> opt_merge - -16.47.14.5. Executing OPT_MERGE pass (detect identical cells). +32.3.14.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\fifo'. Removed a total of 0 cells. -yosys> opt_dff +32.3.14.6. Executing OPT_DFF pass (perform DFF optimizations). -16.47.14.6. Executing OPT_DFF pass (perform DFF optimizations). - -yosys> opt_clean -purge - -16.47.14.7. Executing OPT_CLEAN pass (remove unused cells and wires). +32.3.14.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \fifo.. Removed 0 unused cells and 24 unused wires. -yosys> opt_expr - -16.47.14.8. Executing OPT_EXPR pass (perform const folding). +32.3.14.8. Executing OPT_EXPR pass (perform const folding). Optimizing module fifo. -16.47.14.9. Rerunning OPT passes. (Maybe there is more to do..) +32.3.14.9. Rerunning OPT passes. (Maybe there is more to do..) -yosys> opt_muxtree - -16.47.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +32.3.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \fifo.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. -yosys> opt_reduce - -16.47.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). +32.3.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \fifo. Performed a total of 0 changes. -yosys> opt_merge - -16.47.14.12. Executing OPT_MERGE pass (detect identical cells). +32.3.14.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\fifo'. Removed a total of 0 cells. -yosys> opt_dff +32.3.14.13. Executing OPT_DFF pass (perform DFF optimizations). -16.47.14.13. Executing OPT_DFF pass (perform DFF optimizations). - -yosys> opt_clean -purge - -16.47.14.14. Executing OPT_CLEAN pass (remove unused cells and wires). +32.3.14.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \fifo.. -yosys> opt_expr - -16.47.14.15. Executing OPT_EXPR pass (perform const folding). +32.3.14.15. Executing OPT_EXPR pass (perform const folding). Optimizing module fifo. -16.47.14.16. Finished OPT passes. (There is nothing left to do.) +32.3.14.16. Finished OPT passes. (There is nothing left to do.) -yosys> aigmap - -16.47.15. Executing AIGMAP pass (map logic to AIG). +32.3.15. Executing AIGMAP pass (map logic to AIG). Module fifo: replaced 7 cells with 43 new cells, skipped 11 cells. replaced 2 cell types: 2 $_OR_ @@ -2019,15 +1804,7 @@ Module fifo: replaced 7 cells with 43 new cells, skipped 11 cells. 1 $_NOT_ 2 $_AND_ -yosys> design -stash $abc9_holes - -yosys> design -load $abc9 - -yosys> design -delete $abc9 - -yosys> aigmap - -16.47.16. Executing AIGMAP pass (map logic to AIG). +32.3.16. Executing AIGMAP pass (map logic to AIG). Module fifo: replaced 46 cells with 256 new cells, skipped 230 cells. replaced 3 cell types: 22 $_OR_ @@ -2039,36 +1816,28 @@ Module fifo: replaced 46 cells with 256 new cells, skipped 230 cells. 11 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000011100000 26 SB_DFF 25 SB_DFFER - 30 $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1 - 11 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000011001011 25 SB_DFFER_$abc9_byp - 1 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000001100010 - 2 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000100001011 + 1 $paramod$ba68a0420314c29d51ab7ddbd2ec9361aa29f018\SB_RAM40_4K + 11 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000011001011 + 30 $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1 16 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000010100001 1 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000010000101 - 1 $paramod$ba68a0420314c29d51ab7ddbd2ec9361aa29f018\SB_RAM40_4K + 1 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000001100010 16 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000100010010 26 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000000010101 + 2 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000100001011 -yosys*> abc9_ops -write_lut /tmp/yosys-abc-Sf9BQI/input.lut +32.3.16.1. Executing ABC9_OPS pass (helper functions for ABC9). -16.47.16.1. Executing ABC9_OPS pass (helper functions for ABC9). +32.3.16.2. Executing ABC9_OPS pass (helper functions for ABC9). -yosys*> abc9_ops -write_box /tmp/yosys-abc-Sf9BQI/input.box - -16.47.16.2. Executing ABC9_OPS pass (helper functions for ABC9). - -yosys*> write_xaiger -map /tmp/yosys-abc-Sf9BQI/input.sym /tmp/yosys-abc-Sf9BQI/input.xaig - -16.47.16.3. Executing XAIGER backend. +32.3.16.3. Executing XAIGER backend. Extracted 113 AND gates and 562 wires from module `fifo' to a netlist network with 71 inputs and 127 outputs. -yosys*> abc9_exe -W 250 -cwd /tmp/yosys-abc-Sf9BQI -lut /tmp/yosys-abc-Sf9BQI/input.lut -box /tmp/yosys-abc-Sf9BQI/input.box +32.3.16.4. Executing ABC9_EXE pass (technology mapping using ABC9). -16.47.16.4. Executing ABC9_EXE pass (technology mapping using ABC9). - -16.47.16.5. Executing ABC9. +32.3.16.5. Executing ABC9. Running ABC command: "/yosys-abc" -s -f /abc.script 2>&1 ABC: ABC command line: "source /abc.script". ABC: @@ -2108,58 +1877,38 @@ ABC: + &write -n /output.aig ABC: + time ABC: elapse: 0.01 seconds, total: 0.01 seconds -yosys*> read_aiger -xaiger -wideports -module_name fifo$abc9 -map /tmp/yosys-abc-Sf9BQI/input.sym /tmp/yosys-abc-Sf9BQI/output.aig - -16.47.16.6. Executing AIGER frontend. - -yosys> clean +32.3.16.6. Executing AIGER frontend. Removed 175 unused cells and 883 unused wires. -yosys*> abc9_ops -reintegrate - -16.47.16.7. Executing ABC9_OPS pass (helper functions for ABC9). +32.3.16.7. Executing ABC9_OPS pass (helper functions for ABC9). ABC RESULTS: $lut cells: 29 -ABC RESULTS: $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1 cells: 30 ABC RESULTS: \SB_DFFER_$abc9_byp cells: 25 +ABC RESULTS: $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1 cells: 30 ABC RESULTS: input signals: 36 ABC RESULTS: output signals: 91 Removing temp directory. -yosys> techmap -wb -map %$abc9_unmap -map +/abc9_unmap.v +32.3.17. Executing TECHMAP pass (map to technology primitives). -16.47.17. Executing TECHMAP pass (map to technology primitives). - -16.47.17.1. Executing Verilog-2005 frontend: /home/dawn/yosys/share/abc9_unmap.v +32.3.17.1. Executing Verilog-2005 frontend: /home/dawn/yosys/share/abc9_unmap.v Parsing Verilog input from `/home/dawn/yosys/share/abc9_unmap.v' to AST representation. Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'. Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'. Successfully finished Verilog frontend. -16.47.17.2. Continuing TECHMAP pass. +32.3.17.2. Continuing TECHMAP pass. Using template SB_DFFER_$abc9_byp for cells of type SB_DFFER_$abc9_byp. Using template $paramod$ba68a0420314c29d51ab7ddbd2ec9361aa29f018\SB_RAM40_4K for cells of type $paramod$ba68a0420314c29d51ab7ddbd2ec9361aa29f018\SB_RAM40_4K. Using template $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1 for cells of type $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1. No more expansions possible. -yosys> design -delete $abc9_unmap +32.4. Executing ICE40_WRAPCARRY pass (wrap carries). -yosys> design -delete $abc9_holes +32.5. Executing TECHMAP pass (map to technology primitives). -yosys> delete =*_$abc9_byp - -yosys> setattr -mod -unset abc9_box_id - -yosys> ice40_wrapcarry -unwrap - -16.48. Executing ICE40_WRAPCARRY pass (wrap carries). - -yosys> techmap -map +/ice40/ff_map.v - -16.49. Executing TECHMAP pass (map to technology primitives). - -16.49.1. Executing Verilog-2005 frontend: /home/dawn/yosys/share/ice40/ff_map.v +32.5.1. Executing Verilog-2005 frontend: /home/dawn/yosys/share/ice40/ff_map.v Parsing Verilog input from `/home/dawn/yosys/share/ice40/ff_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. @@ -2183,16 +1932,12 @@ Generating RTLIL representation for module `\$_SDFFCE_PP0P_'. Generating RTLIL representation for module `\$_SDFFCE_PP1P_'. Successfully finished Verilog frontend. -16.49.2. Continuing TECHMAP pass. +32.5.2. Continuing TECHMAP pass. No more expansions possible. - -yosys> clean Removed 7 unused cells and 1055 unused wires. -yosys> opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3 -dlogic SB_CARRY:CO=3 - -16.50. Executing OPT_LUT pass (optimize LUTs). +32.6. Executing OPT_LUT pass (optimize LUTs). Discovering LUTs. Number of LUTs: 58 1-LUT 3 @@ -2224,63 +1969,60 @@ Eliminated 0 LUTs. Combined 0 LUTs. -yosys> techmap -map +/ice40/cells_map.v +33. Generating Graphviz representation of design. +Writing dot description to `rdata_map_luts.dot'. +Dumping selected parts of module fifo to page 1. -16.51. Executing TECHMAP pass (map to technology primitives). +34. Executing SYNTH_ICE40 pass. -16.51.1. Executing Verilog-2005 frontend: /home/dawn/yosys/share/ice40/cells_map.v +34.1. Executing TECHMAP pass (map to technology primitives). + +34.1.1. Executing Verilog-2005 frontend: /home/dawn/yosys/share/ice40/cells_map.v Parsing Verilog input from `/home/dawn/yosys/share/ice40/cells_map.v' to AST representation. Generating RTLIL representation for module `\$lut'. Successfully finished Verilog frontend. -16.51.2. Continuing TECHMAP pass. -Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut. +34.1.2. Continuing TECHMAP pass. Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut. Using template $paramod$e87f431398fe61dc3cef677df705fdf1c11aa0f7\$lut for cells of type $lut. -Using template $paramod$8d7a8d6e3356de09670738ba85f2c6b874f6b06d\$lut for cells of type $lut. -Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. Using template $paramod$2b29ccbd5fb8b9c557f92ddec1023c75686f32ae\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut. Using template $paramod$ba7c22fadfbf9ee7abcb895a21403114111dd201\$lut for cells of type $lut. Using template $paramod$5c7d886f3b88971ac55fed4bca034a87bf180f7d\$lut for cells of type $lut. +Using template $paramod$8d7a8d6e3356de09670738ba85f2c6b874f6b06d\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut. Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001011 for cells of type $lut. +Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. -Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001011 for cells of type $lut. No more expansions possible. - + +Removed 0 unused cells and 129 unused wires. -yosys> clean -Removed 0 unused cells and 130 unused wires. +34.2. Executing AUTONAME pass. +Renamed 1278 objects in module fifo (21 iterations). + -yosys> autoname +34.3. Executing HIERARCHY pass (managing design hierarchy). -16.52. Executing AUTONAME pass. -Renamed 1254 objects in module fifo (21 iterations). - - -yosys> hierarchy -check - -16.53. Executing HIERARCHY pass (managing design hierarchy). - -16.53.1. Analyzing design hierarchy.. +34.3.1. Analyzing design hierarchy.. Top module: \fifo -16.53.2. Analyzing design hierarchy.. +34.3.2. Analyzing design hierarchy.. Top module: \fifo Removed 0 unused modules. -yosys> stat - -16.54. Printing statistics. +34.4. Printing statistics. === fifo === - Number of wires: 91 - Number of wire bits: 246 - Number of public wires: 91 - Number of public wire bits: 246 + Number of wires: 92 + Number of wire bits: 250 + Number of public wires: 92 + Number of public wire bits: 250 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 @@ -2291,41 +2033,10 @@ yosys> stat SB_LUT4 58 SB_RAM40_4K 1 - -yosys> check -noinit - -16.55. Executing CHECK pass (checking for obvious problems). +34.5. Executing CHECK pass (checking for obvious problems). Checking module fifo... Found and reported 0 problems. -yosys> blackbox =A:whitebox - -yosys> show -notitle -format dot -prefix fifo_synth - -17. Generating Graphviz representation of design. -Writing dot description to `fifo_synth.dot'. -Dumping module fifo to page 1. - -yosys> stat - -18. Printing statistics. - -=== fifo === - - Number of wires: 91 - Number of wire bits: 246 - Number of public wires: 91 - Number of public wire bits: 246 - Number of memories: 0 - Number of memory bits: 0 - Number of processes: 0 - Number of cells: 136 - SB_CARRY 26 - SB_DFF 26 - SB_DFFER 25 - SB_LUT4 58 - SB_RAM40_4K 1 - -End of script. Logfile hash: 7fbdf4b991, CPU: user 0.68s system 0.01s, MEM: 29.84 MB peak -Yosys 0.35+39 (git sha1 0cd4a10c8, clang 10.0.0-4ubuntu1 -fPIC -Os) -Time spent: 37% 27x read_verilog (0 sec), 33% 12x techmap (0 sec), ... +35. Generating Graphviz representation of design. +Writing dot description to `rdata_map_cells.dot'. +Dumping selected parts of module fifo to page 1. diff --git a/docs/source/code_examples/fifo/fifo.ys b/docs/source/code_examples/fifo/fifo.ys index 576704838..3bfc0468a 100644 --- a/docs/source/code_examples/fifo/fifo.ys +++ b/docs/source/code_examples/fifo/fifo.ys @@ -56,7 +56,51 @@ show -color maroon3 @new_cells -notitle -format dot -prefix rdata_alumacc o:rdat design -reset read_verilog fifo.v synth_ice40 -top fifo -run begin:map_ram -# memory_collect -# opt select -set new_cells t:$mem_v2 -show -color maroon3 @new_cells -notitle -format dot -prefix rdata_coarse o:rdata %ci* +select -set rdata_path @new_cells %ci*:-$mem_v2[WR_DATA,WR_ADDR,WR_EN] @new_cells %co* %% +show -color maroon3 @new_cells -notitle -format dot -prefix rdata_coarse @rdata_path + +# turn command echoes off to avoid randomly generated abc file names +echo off + +# ======================================================== + +synth_ice40 -top fifo -run map_ram:map_ffram +select -set new_cells t:SB_RAM40_4K +select -set rdata_path @new_cells %ci*:-SB_RAM40_4K[WDATA,WADDR,WE] @new_cells %co* %% +show -color maroon3 @new_cells -notitle -format dot -prefix rdata_map_ram @rdata_path + +# ======================================================== + +synth_ice40 -top fifo -run map_ffram:map_gates +select -set new_cells t:SB_RAM40_4K +select -set rdata_path @new_cells %ci*:-SB_RAM40_4K[WDATA,WADDR,WE] @new_cells %co* %% +show -color maroon3 @new_cells -notitle -format dot -prefix rdata_map_ffram @rdata_path + +# ======================================================== + +synth_ice40 -top fifo -run map_gates:map_ffs +select -set new_cells t:SB_RAM40_4K +select -set rdata_path @new_cells %ci*:-SB_RAM40_4K[WDATA,WADDR,WE] @new_cells %co* %% +show -color maroon3 @new_cells -notitle -format dot -prefix rdata_map_gates @rdata_path + +# ======================================================== + +synth_ice40 -top fifo -run map_ffs:map_luts +select -set new_cells t:SB_RAM40_4K +select -set rdata_path @new_cells %ci*:-SB_RAM40_4K[WDATA,WADDR,WE] @new_cells %co* %% +show -color maroon3 @new_cells -notitle -format dot -prefix rdata_map_ffs @rdata_path + +# ======================================================== + +synth_ice40 -top fifo -run map_luts:map_cells +select -set new_cells t:SB_RAM40_4K +select -set rdata_path @new_cells %ci*:-SB_RAM40_4K[WDATA,WADDR,WE] @new_cells %co* %% +show -color maroon3 @new_cells -notitle -format dot -prefix rdata_map_luts @rdata_path + +# ======================================================== + +synth_ice40 -top fifo -run map_cells: +select -set new_cells t:SB_RAM40_4K +select -set rdata_path @new_cells %ci*:-SB_RAM40_4K[WDATA,WADDR,WE] @new_cells %co* %% +show -color maroon3 @new_cells -notitle -format dot -prefix rdata_map_cells @rdata_path diff --git a/docs/source/getting_started/example_synth.rst b/docs/source/getting_started/example_synth.rst index a22ea1bf9..7fd48eb0c 100644 --- a/docs/source/getting_started/example_synth.rst +++ b/docs/source/getting_started/example_synth.rst @@ -299,24 +299,26 @@ optimizations and other transformations done previously. While the iCE40 flow had a :ref:`synth_flatten` and put :cmd:ref:`proc` in the :ref:`synth_begin`, some synthesis scripts will instead include these in - the :ref:`synth_coarse`. + this section. -In the iCE40 flow we get all the following commands: +Part 1 +^^^^^^ + +In the iCE40 flow, we start with the following commands: .. literalinclude:: /cmd/synth_ice40.rst :language: yoscrypt - :linenos: :start-after: coarse: - :end-before: map_ram: + :end-before: wreduce :dedent: - :caption: ``coarse`` section - :name: synth_coarse + :caption: ``coarse`` section (part 1) + :name: synth_coarse1 -The first few commands are relatively straightforward. We've already come +The first few commands are relatively straightforward, and we've already come across :cmd:ref:`opt_clean` and :cmd:ref:`opt_expr`. The :cmd:ref:`check` pass identifies a few obvious problems which will cause errors later. Calling it here lets us fail faster rather than wasting time on something we know is -impossible. +impossible. Next up is :yoscrypt:`opt -nodffe -nosdff` performing a set of simple optimizations on the design. This command also ensures that only a specific @@ -343,12 +345,30 @@ options is able to fold one of the ``$mux`` cells into the ``$adff`` to form an ``rdata`` output after :cmd:ref:`opt_dff` +.. seealso:: Advanced usage docs for + + - :doc:`/using_yosys/synthesis/fsm` + - :doc:`/using_yosys/synthesis/opt` + +Part 2 +^^^^^^ + +.. literalinclude:: /cmd/synth_ice40.rst + :language: yoscrypt + :start-at: wreduce + :end-before: t:$mul + :dedent: + :caption: ``coarse`` section (part 2) + :name: synth_coarse2 + The next three (new) commands are :doc:`/cmd/wreduce`, :doc:`/cmd/peepopt`, and :doc:`/cmd/share`. None of these affect our design either, so let's skip over them. :yoscrypt:`techmap -map +/cmp2lut.v -D LUT_WIDTH=4` optimizes certain comparison operators by converting them to LUTs instead. The usage of :cmd:ref:`techmap` is explored more in -:doc:`/using_yosys/synthesis/techmap_synth`. Our next command to run is +:doc:`/using_yosys/synthesis/techmap_synth`. + +Our next command to run is :doc:`/cmd/memory_dff`. .. literalinclude:: /code_examples/fifo/fifo.out @@ -365,10 +385,45 @@ comparison operators by converting them to LUTs instead. The usage of As the title suggests, :cmd:ref:`memory_dff` has merged the output ``$dff`` into the ``$memrd`` cell and converted it to a ``$memrd_v2`` (highlighted). -Following this is a series of commands for mapping to DSPs. + +.. seealso:: Advanced usage docs for + + - :doc:`/using_yosys/synthesis/opt` + - :doc:`/using_yosys/synthesis/techmap_synth` + - :doc:`/using_yosys/synthesis/memory` + +Part 3 +^^^^^^ + +The third part of the :cmd:ref:`synth_ice40` flow is a series of commands for +mapping to DSPs. + +.. literalinclude:: /cmd/synth_ice40.rst + :language: yoscrypt + :start-at: t:$mul + :end-before: alumacc + :dedent: + :caption: ``coarse`` section (part 3) + :name: synth_coarse3 .. TODO:: more on DSP mapping +.. seealso:: Advanced usage docs for + :doc:`/using_yosys/synthesis/techmap_synth` + +Part 4 +^^^^^^ + +That brings us to the fourth and final part for the iCE40 synthesis flow: + +.. literalinclude:: /cmd/synth_ice40.rst + :language: yoscrypt + :start-at: alumacc + :end-before: map_ram: + :dedent: + :caption: ``coarse`` section (part 4) + :name: synth_coarse4 + Where before each type of arithmetic operation had its own cell, e.g. ``$add``, we now want to extract these into ``$alu`` and ``$macc`` cells which can be mapped to hard blocks. We do this by running :cmd:ref:`alumacc`, which we can @@ -386,15 +441,7 @@ see produce the following changes in our example design: ``rdata`` output after :cmd:ref:`alumacc` -That brings us to the last commands, and a look at ``rdata`` at the end of the -:ref:`synth_coarse`. We could also have gotten here by running -:yoscrypt:`synth_ice40 -top fifo -run begin:map_ram` after loading the design. - -.. literalinclude:: /cmd/synth_ice40.rst - :language: yoscrypt - :start-at: memory -nomap - :end-before: map_ram: - :dedent: +.. TODO:: discuss :cmd:ref:`memory_collect` and ``$mem_v2`` .. figure:: /_images/code_examples/fifo/rdata_coarse.* :class: width-helper @@ -402,18 +449,26 @@ That brings us to the last commands, and a look at ``rdata`` at the end of the ``rdata`` output after :yoscrypt:`memory -nomap` -.. TODO:: discuss :cmd:ref:`memory_collect` and ``$mem_v2`` +We could also have gotten here by running :yoscrypt:`synth_ice40 -top fifo -run +begin:map_ram` after loading the design. .. seealso:: Advanced usage docs for - :doc:`/using_yosys/synthesis/fsm` - :doc:`/using_yosys/synthesis/opt` - :doc:`/using_yosys/synthesis/techmap_synth` :doc:`/using_yosys/synthesis/memory` Hardware mapping ~~~~~~~~~~~~~~~~ -.. TODO:: example_synth hardware mapping sections +The remaining sections each map a different type of hardware and are much more +architecture dependent than the previous sections. As such we will only be +looking at each section very briefly. + +Memory blocks +^^^^^^^^^^^^^ + +Mapping to hard memory blocks uses a combination of :cmd:ref:`memory_libmap`, +:cmd:ref:`memory_map`, and :cmd:ref:`techmap`. + +.. TODO:: ``$mem_v2`` -> ``SB_RAM40_4K`` .. literalinclude:: /cmd/synth_ice40.rst :language: yoscrypt @@ -423,6 +478,12 @@ Hardware mapping :name: map_ram :caption: ``map_ram`` section +.. figure:: /_images/code_examples/fifo/rdata_map_ram.* + :class: width-helper + :name: rdata_map_ram + + ``rdata`` output after :ref:`map_ram` + .. literalinclude:: /cmd/synth_ice40.rst :language: yoscrypt :start-after: map_ffram: @@ -431,6 +492,24 @@ Hardware mapping :name: map_ffram :caption: ``map_ffram`` section +.. figure:: /_images/code_examples/fifo/rdata_map_ffram.* + :class: width-helper + :name: rdata_map_ffram + + ``rdata`` output after :ref:`map_ffram` + +.. seealso:: Advanced usage docs for + + - :doc:`/using_yosys/synthesis/techmap_synth` + - :doc:`/using_yosys/synthesis/memory` + +Arithmetic +^^^^^^^^^^ + +Uses :cmd:ref:`techmap`. + +.. TODO:: example_synth/Arithmetic + .. literalinclude:: /cmd/synth_ice40.rst :language: yoscrypt :start-after: map_gates: @@ -439,6 +518,23 @@ Hardware mapping :name: map_gates :caption: ``map_gates`` section +.. figure:: /_images/code_examples/fifo/rdata_map_gates.* + :class: width-helper + :name: rdata_map_gates + + ``rdata`` output after :ref:`map_gates` + +.. seealso:: Advanced usage docs for + :doc:`/using_yosys/synthesis/techmap_synth` + +Flip-flops +^^^^^^^^^^ + +Convert FFs to the types supported in hardware with :cmd:ref:`dfflegalize`, and +then use :cmd:ref:`techmap` to map them. We also run :cmd:ref:`simplemap` here +to convert any remaining cells which could not be mapped to hardware into +gate-level primitives. + .. literalinclude:: /cmd/synth_ice40.rst :language: yoscrypt :start-after: map_ffs: @@ -447,6 +543,23 @@ Hardware mapping :name: map_ffs :caption: ``map_ffs`` section +.. figure:: /_images/code_examples/fifo/rdata_map_ffs.* + :class: width-helper + :name: rdata_map_ffs + + ``rdata`` output after :ref:`map_ffs` + +.. seealso:: Advanced usage docs for + :doc:`/using_yosys/synthesis/techmap_synth` + +LUTs +^^^^ + +:cmd:ref:`abc` and :cmd:ref:`techmap` are used to map LUTs. Note that the iCE40 +flow uses :cmd:ref:`abc` rather than :cmd:ref:`abc9`. For more on what these +do, and what the difference between these two commands are, refer to +:doc:`/using_yosys/synthesis/abc`. + .. literalinclude:: /cmd/synth_ice40.rst :language: yoscrypt :start-after: map_luts: @@ -455,6 +568,22 @@ Hardware mapping :name: map_luts :caption: ``map_luts`` section +.. figure:: /_images/code_examples/fifo/rdata_map_luts.* + :class: width-helper + :name: rdata_map_luts + + ``rdata`` output after :ref:`map_luts` + +.. seealso:: Advanced usage docs for + + - :doc:`/using_yosys/synthesis/techmap_synth` + - :doc:`/using_yosys/synthesis/abc` + +Other cells +^^^^^^^^^^^ + +Seems to be wide LUTs into individual LUTs using :cmd:ref:`techmap`. + .. literalinclude:: /cmd/synth_ice40.rst :language: yoscrypt :start-after: map_cells: @@ -463,9 +592,13 @@ Hardware mapping :name: map_cells :caption: ``map_cells`` section -:cmd:ref:`dfflibmap` - This command maps the internal register cell types to the register types - described in a liberty file. +.. figure:: /_images/code_examples/fifo/rdata_map_cells.* + :class: width-helper + :name: rdata_map_cells + + ``rdata`` output after :ref:`map_cells` + +.. TODO:: example_synth other cells :cmd:ref:`hilomap` Some architectures require special driver cells for driving a constant hi or @@ -476,12 +609,8 @@ Hardware mapping Top-level input/outputs must usually be implemented using special I/O-pad cells. This command inserts such cells to the design. -:cmd:ref:`dfflegalize` - Specify a set of supported FF cells/cell groups and convert all FFs to them. - .. seealso:: Advanced usage docs for - :doc:`/yosys_internals/techmap`, and - :doc:`/using_yosys/synthesis/memory`. + :doc:`/yosys_internals/techmap` Final steps ~~~~~~~~~~~~