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Clean whitespace and permissions in techlibs/intel

This commit is contained in:
Larry Doolittle 2017-10-04 17:01:30 -07:00 committed by Clifford Wolf
parent fc3378916d
commit 50bcd9a728
21 changed files with 190 additions and 190 deletions
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0
techlibs/intel/Makefile.inc Executable file → Normal file
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8
techlibs/intel/a10gx/cells_arith.v Executable file → Normal file
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@ -45,10 +45,10 @@ module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO);
//wire [Y_WIDTH:0] C = {CO, CI}; //wire [Y_WIDTH:0] C = {CO, CI};
wire [Y_WIDTH+1:0] COx; wire [Y_WIDTH+1:0] COx;
wire [Y_WIDTH+1:0] C = {COx, CI}; wire [Y_WIDTH+1:0] C = {COx, CI};
/* Start implementation */ /* Start implementation */
(* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1)); (* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
genvar i; genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
if(i==Y_WIDTH-1) begin if(i==Y_WIDTH-1) begin
@ -61,5 +61,5 @@ module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO);
endgenerate endgenerate
/* End implementation */ /* End implementation */
assign X = AA ^ BB; assign X = AA ^ BB;
endmodule endmodule

4
techlibs/intel/a10gx/cells_map.v Executable file → Normal file
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@ -31,13 +31,13 @@ module \$lut (A, Y);
parameter WIDTH = 0; parameter WIDTH = 0;
parameter LUT = 0; parameter LUT = 0;
input [WIDTH-1:0] A; input [WIDTH-1:0] A;
output Y; output Y;
generate generate
if (WIDTH == 1) begin if (WIDTH == 1) begin
assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
end else end else
if (WIDTH == 2) begin if (WIDTH == 2) begin
twentynm_lcell_comb #(.lut_mask({16{LUT}}), .shared_arith("off"), .extended_lut("off")) twentynm_lcell_comb #(.lut_mask({16{LUT}}), .shared_arith("off"), .extended_lut("off"))
_TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(1'b1),.datad(1'b1), .datae(1'b1), .dataf(1'b1), .datag(1'b1)); _TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(1'b1),.datad(1'b1), .datae(1'b1), .dataf(1'b1), .datag(1'b1));
end /*else end /*else
if(WIDTH == 3) begin if(WIDTH == 3) begin

2
techlibs/intel/a10gx/cells_sim.v Executable file → Normal file
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@ -38,7 +38,7 @@ endmodule // twentynm_io_obuf
/* Altera Arria 10 GX LUT Primitive */ /* Altera Arria 10 GX LUT Primitive */
module twentynm_lcell_comb (output combout, cout, sumout, module twentynm_lcell_comb (output combout, cout, sumout,
input dataa, datab, datac, datad, input dataa, datab, datac, datad,
input datae, dataf, datag, cin, input datae, dataf, datag, cin,
input sharein); input sharein);

8
techlibs/intel/common/altpll_bb.v
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@ -19,7 +19,7 @@
/* No clearbox model */ /* No clearbox model */
`ifdef NO_CLEARBOX `ifdef NO_CLEARBOX
(* blackbox *) (* blackbox *)
module altpll module altpll
( inclk, ( inclk,
fbin, fbin,
pllena, pllena,
@ -62,7 +62,7 @@ module altpll
c2, c2,
c3, c3,
c4); c4);
parameter intended_device_family = "MAX 10"; parameter intended_device_family = "MAX 10";
parameter operation_mode = "NORMAL"; parameter operation_mode = "NORMAL";
parameter pll_type = "AUTO"; parameter pll_type = "AUTO";
@ -340,7 +340,7 @@ module altpll
input phasestep; input phasestep;
input configupdate; input configupdate;
inout fbmimicbidir; inout fbmimicbidir;
output [width_clock-1:0] clk; output [width_clock-1:0] clk;
output [3:0] extclk; output [3:0] extclk;
@ -361,6 +361,6 @@ module altpll
output fref; output fref;
output icdrclk; output icdrclk;
output c0, c1, c2, c3, c4; output c0, c1, c2, c3, c4;
endmodule // altpll endmodule // altpll
`endif `endif

0
techlibs/intel/common/brams.txt Executable file → Normal file
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58
techlibs/intel/common/brams_map.v Executable file → Normal file
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@ -2,11 +2,11 @@ module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1A
parameter CFG_ABITS = 8; parameter CFG_ABITS = 8;
parameter CFG_DBITS = 36; parameter CFG_DBITS = 36;
parameter ABITS = "1"; parameter ABITS = "1";
parameter DBITS = "1"; parameter DBITS = "1";
parameter CLKPOL2 = 1; parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1; parameter CLKPOL3 = 1;
input CLK2; input CLK2;
input CLK3; input CLK3;
//Read data //Read data
@ -19,7 +19,7 @@ module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1A
input B1EN; input B1EN;
wire [CFG_DBITS-1:0] B1DATA_t; wire [CFG_DBITS-1:0] B1DATA_t;
localparam MODE = CFG_DBITS == 1 ? 1: localparam MODE = CFG_DBITS == 1 ? 1:
CFG_DBITS == 2 ? 2: CFG_DBITS == 2 ? 2:
CFG_DBITS == 4 ? 3: CFG_DBITS == 4 ? 3:
@ -30,7 +30,7 @@ module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1A
CFG_DBITS == 32 ? 8: CFG_DBITS == 32 ? 8:
CFG_DBITS == 36 ? 9: CFG_DBITS == 36 ? 9:
'bx; 'bx;
localparam NUMWORDS = CFG_DBITS == 1 ? 8192: localparam NUMWORDS = CFG_DBITS == 1 ? 8192:
CFG_DBITS == 2 ? 4096: CFG_DBITS == 2 ? 4096:
CFG_DBITS == 4 ? 2048: CFG_DBITS == 4 ? 2048:
@ -41,32 +41,32 @@ module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1A
CFG_DBITS == 32 ? 256: CFG_DBITS == 32 ? 256:
CFG_DBITS == 36 ? 256: CFG_DBITS == 36 ? 256:
'bx; 'bx;
altsyncram #(.clock_enable_input_b ("ALTERNATE" ), altsyncram #(.clock_enable_input_b ("ALTERNATE" ),
.clock_enable_input_a ("ALTERNATE" ), .clock_enable_input_a ("ALTERNATE" ),
.clock_enable_output_b ("NORMAL" ), .clock_enable_output_b ("NORMAL" ),
.clock_enable_output_a ("NORMAL" ), .clock_enable_output_a ("NORMAL" ),
.wrcontrol_aclr_a ("NONE" ), .wrcontrol_aclr_a ("NONE" ),
.indata_aclr_a ("NONE" ), .indata_aclr_a ("NONE" ),
.address_aclr_a ("NONE" ), .address_aclr_a ("NONE" ),
.outdata_aclr_a ("NONE" ), .outdata_aclr_a ("NONE" ),
.outdata_reg_a ("UNREGISTERED"), .outdata_reg_a ("UNREGISTERED"),
.operation_mode ("SINGLE_PORT" ), .operation_mode ("SINGLE_PORT" ),
.intended_device_family ("CYCLONE IVE" ), .intended_device_family ("CYCLONE IVE" ),
.outdata_reg_a ("UNREGISTERED"), .outdata_reg_a ("UNREGISTERED"),
.lpm_type ("altsyncram" ), .lpm_type ("altsyncram" ),
.init_type ("unused" ), .init_type ("unused" ),
.ram_block_type ("AUTO" ), .ram_block_type ("AUTO" ),
.lpm_hint ("ENABLE_RUNTIME_MOD=NO"), // Forced value .lpm_hint ("ENABLE_RUNTIME_MOD=NO"), // Forced value
.power_up_uninitialized ("FALSE"), .power_up_uninitialized ("FALSE"),
.read_during_write_mode_port_a ("NEW_DATA_NO_NBE_READ"), // Forced value .read_during_write_mode_port_a ("NEW_DATA_NO_NBE_READ"), // Forced value
.width_byteena_a (1), // Forced value .width_byteena_a (1), // Forced value
.numwords_b ( NUMWORDS ), .numwords_b ( NUMWORDS ),
.numwords_a ( NUMWORDS ), .numwords_a ( NUMWORDS ),
.widthad_b ( CFG_ABITS ), .widthad_b ( CFG_ABITS ),
.width_b ( CFG_DBITS ), .width_b ( CFG_DBITS ),
.widthad_a ( CFG_ABITS ), .widthad_a ( CFG_ABITS ),
.width_a ( CFG_DBITS ) .width_a ( CFG_DBITS )
) _TECHMAP_REPLACE_ ( ) _TECHMAP_REPLACE_ (
.data_a(B1DATA), .data_a(B1DATA),
.address_a(B1ADDR), .address_a(B1ADDR),
@ -78,16 +78,16 @@ module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1A
.wren_b(1'b0), .wren_b(1'b0),
.rden_b(1'b0), .rden_b(1'b0),
.q_b(1'b0), .q_b(1'b0),
.clock0(CLK2), .clock0(CLK2),
.clock1(1'b1), // Unused in single port mode .clock1(1'b1), // Unused in single port mode
.clocken0(1'b1), .clocken0(1'b1),
.clocken1(1'b1), .clocken1(1'b1),
.clocken2(1'b1), .clocken2(1'b1),
.clocken3(1'b1), .clocken3(1'b1),
.aclr0(1'b0), .aclr0(1'b0),
.aclr1(1'b0), .aclr1(1'b0),
.addressstall_a(1'b0), .addressstall_a(1'b0),
.addressstall_b(1'b0)); .addressstall_b(1'b0));
endmodule endmodule

12
techlibs/intel/common/m9k_bb.v Executable file → Normal file
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@ -17,10 +17,10 @@
* *
*/ */
(* blackbox *) (* blackbox *)
module altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b, wren_b, rden_b, module altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b, wren_b, rden_b,
q_b, clock0, clock1, clocken0, clocken1, clocken2, clocken3, aclr0, aclr1, q_b, clock0, clock1, clocken0, clocken1, clocken2, clocken3, aclr0, aclr1,
addressstall_a, addressstall_b); addressstall_a, addressstall_b);
parameter clock_enable_input_b = "ALTERNATE"; parameter clock_enable_input_b = "ALTERNATE";
parameter clock_enable_input_a = "ALTERNATE"; parameter clock_enable_input_a = "ALTERNATE";
parameter clock_enable_output_b = "NORMAL"; parameter clock_enable_output_b = "NORMAL";
@ -33,7 +33,7 @@ module altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b, wr
parameter operation_mode = "SINGLE_PORT"; parameter operation_mode = "SINGLE_PORT";
parameter intended_device_family = "MAX 10 FPGA"; parameter intended_device_family = "MAX 10 FPGA";
parameter outdata_reg_a = "UNREGISTERED"; parameter outdata_reg_a = "UNREGISTERED";
parameter lpm_type = "altsyncram"; parameter lpm_type = "altsyncram";
parameter init_type = "unused"; parameter init_type = "unused";
parameter ram_block_type = "AUTO"; parameter ram_block_type = "AUTO";
parameter lpm_hint = "ENABLE_RUNTIME_MOD=NO"; parameter lpm_hint = "ENABLE_RUNTIME_MOD=NO";
@ -46,7 +46,7 @@ module altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b, wr
parameter width_b = 1; parameter width_b = 1;
parameter widthad_a = 1; parameter widthad_a = 1;
parameter width_a = 1; parameter width_a = 1;
// Port A declarations // Port A declarations
output [35:0] q_a; output [35:0] q_a;
input [35:0] data_a; input [35:0] data_a;
@ -66,5 +66,5 @@ module altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b, wr
input addressstall_a; input addressstall_a;
input addressstall_b; input addressstall_b;
// TODO: Implement the correct simulation model // TODO: Implement the correct simulation model
endmodule // altsyncram endmodule // altsyncram

8
techlibs/intel/cycloneiv/cells_arith.v Executable file → Normal file
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@ -19,7 +19,7 @@
// NOTE: This is still WIP. // NOTE: This is still WIP.
(* techmap_celltype = "$alu" *) (* techmap_celltype = "$alu" *)
/* Uncomment this for LCU???? /* Uncomment this for LCU????
module _80_cycloneiv_alu (A, B, CI, BI, X, Y, CO); module _80_cycloneiv_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0; parameter A_SIGNED = 0;
parameter B_SIGNED = 0; parameter B_SIGNED = 0;
@ -46,7 +46,7 @@ module _80_cycloneiv_alu (A, B, CI, BI, X, Y, CO);
//wire [Y_WIDTH:0] C = {CO, CI}; //wire [Y_WIDTH:0] C = {CO, CI};
wire [Y_WIDTH+1:0] COx; wire [Y_WIDTH+1:0] COx;
wire [Y_WIDTH+1:0] C = {COx, CI}; wire [Y_WIDTH+1:0] C = {COx, CI};
/* Start implementation */ /* Start implementation */
//cycloneiv_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1)); //cycloneiv_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
/* /*
@ -61,7 +61,7 @@ module _80_cycloneiv_alu (A, B, CI, BI, X, Y, CO);
endgenerate endgenerate
/* End implementation */ /* End implementation */
/*assign X = AA ^ BB; /*assign X = AA ^ BB;
endmodule*/ endmodule*/
module _80_cycloneiv_alu (A, B, CI, BI, X, Y, CO); module _80_cycloneiv_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0; parameter A_SIGNED = 0;
@ -86,7 +86,7 @@ module _80_cycloneiv_alu (A, B, CI, BI, X, Y, CO);
wire [Y_WIDTH-1:0] AA = A_buf; wire [Y_WIDTH-1:0] AA = A_buf;
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
wire [Y_WIDTH:0] C = {CO, CI}; wire [Y_WIDTH:0] C = {CO, CI};
cycloneiv_lcell_comb #(.lut_mask(16'b0110_0110_1000_1000), .sum_lutc_input("cin")) carry_start (.cout(CO[0]), .dataa(BB[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1)); cycloneiv_lcell_comb #(.lut_mask(16'b0110_0110_1000_1000), .sum_lutc_input("cin")) carry_start (.cout(CO[0]), .dataa(BB[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
genvar i; genvar i;
generate for (i = 1; i < Y_WIDTH; i = i + 1) begin:slice generate for (i = 1; i < Y_WIDTH; i = i + 1) begin:slice

4
techlibs/intel/cycloneiv/cells_map.v Executable file → Normal file
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@ -39,7 +39,7 @@ module \$_DFF_PP0_ (input D, C, R, output Q);
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule endmodule
module \$__DFFE_PP0 (input D, C, E, R, output Q); module \$__DFFE_PP0 (input D, C, E, R, output Q);
parameter WYSIWYG="TRUE"; parameter WYSIWYG="TRUE";
wire E_i = ~ E; wire E_i = ~ E;
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0)); dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
@ -62,7 +62,7 @@ module \$lut (A, Y);
parameter WIDTH = 0; parameter WIDTH = 0;
parameter LUT = 0; parameter LUT = 0;
input [WIDTH-1:0] A; input [WIDTH-1:0] A;
output Y; output Y;
generate generate
if (WIDTH == 1) begin if (WIDTH == 1) begin
assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function

28
techlibs/intel/cycloneiv/cells_sim.v Executable file → Normal file
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@ -26,7 +26,7 @@ module GND (output G);
endmodule // GND endmodule // GND
/* Altera Cyclone IV (GX) devices Input Buffer Primitive */ /* Altera Cyclone IV (GX) devices Input Buffer Primitive */
module cycloneiv_io_ibuf module cycloneiv_io_ibuf
(output o, input i, input ibar); (output o, input i, input ibar);
assign ibar = ibar; assign ibar = ibar;
assign o = i; assign o = i;
@ -40,7 +40,7 @@ module cycloneiv_io_obuf
endmodule // fiftyfivenm_io_obuf endmodule // fiftyfivenm_io_obuf
/* Altera Cyclone IV (GX) 4-input non-fracturable LUT Primitive */ /* Altera Cyclone IV (GX) 4-input non-fracturable LUT Primitive */
module cycloneiv_lcell_comb module cycloneiv_lcell_comb
(output combout, cout, (output combout, cout,
input dataa, datab, datac, datad, cin); input dataa, datab, datac, datad, cin);
@ -113,7 +113,7 @@ module cycloneiv_lcell_comb
endmodule // cycloneiv_lcell_comb endmodule // cycloneiv_lcell_comb
/* Altera D Flip-Flop Primitive */ /* Altera D Flip-Flop Primitive */
module dffeas module dffeas
(output q, (output q,
input d, clk, clrn, prn, ena, input d, clk, clrn, prn, ena,
input asdata, aload, sclr, sload); input asdata, aload, sclr, sload);
@ -125,7 +125,7 @@ module dffeas
reg q_tmp; reg q_tmp;
wire reset; wire reset;
reg [7:0] debug_net; reg [7:0] debug_net;
assign reset = (prn && sclr && ~clrn && ena); assign reset = (prn && sclr && ~clrn && ena);
assign q = q_tmp & 1'b1; assign q = q_tmp & 1'b1;
@ -134,7 +134,7 @@ module dffeas
else q_tmp <= d; else q_tmp <= d;
end end
assign q = q_tmp; assign q = q_tmp;
endmodule // dffeas endmodule // dffeas
/* Cyclone IV GX altpll clearbox model */ /* Cyclone IV GX altpll clearbox model */
@ -177,9 +177,9 @@ module cycloneiv_pll
parameter bandwidth = 0; parameter bandwidth = 0;
parameter bandwidth_type = "auto"; parameter bandwidth_type = "auto";
parameter use_dc_coupling = "false"; parameter use_dc_coupling = "false";
parameter lock_high = 0; parameter lock_high = 0;
parameter lock_low = 0; parameter lock_low = 0;
parameter lock_window_ui = "0.05"; parameter lock_window_ui = "0.05";
parameter test_bypass_lock_detect = "off"; parameter test_bypass_lock_detect = "off";
parameter clk0_output_frequency = 0; parameter clk0_output_frequency = 0;
parameter clk0_multiply_by = 0; parameter clk0_multiply_by = 0;
@ -258,16 +258,16 @@ module cycloneiv_pll
parameter c4_test_source = -1; parameter c4_test_source = -1;
parameter vco_multiply_by = 0; parameter vco_multiply_by = 0;
parameter vco_divide_by = 0; parameter vco_divide_by = 0;
parameter vco_post_scale = 1; parameter vco_post_scale = 1;
parameter vco_frequency_control = "auto"; parameter vco_frequency_control = "auto";
parameter vco_phase_shift_step = 0; parameter vco_phase_shift_step = 0;
parameter charge_pump_current = 10; parameter charge_pump_current = 10;
parameter loop_filter_r = "1.0"; parameter loop_filter_r = "1.0";
parameter loop_filter_c = 0; parameter loop_filter_c = 0;
parameter pll_compensation_delay = 0; parameter pll_compensation_delay = 0;
parameter lpm_type = "cycloneiv_pll"; parameter lpm_type = "cycloneiv_pll";
parameter phase_counter_select_width = 3; parameter phase_counter_select_width = 3;
input [1:0] inclk; input [1:0] inclk;
input fbin; input fbin;
input clkswitch; input clkswitch;
@ -280,7 +280,7 @@ module cycloneiv_pll
input scanclkena; input scanclkena;
input scandata; input scandata;
input configupdate; input configupdate;
output [4:0] clk; output [4:0] clk;
output [1:0] clkbad; output [1:0] clkbad;
output activeclock; output activeclock;
@ -293,7 +293,7 @@ module cycloneiv_pll
output vcounderrange; output vcounderrange;
output fref; output fref;
output icdrclk; output icdrclk;
endmodule // cycloneive_pll endmodule // cycloneive_pll

4
techlibs/intel/cycloneive/arith_map.v Executable file → Normal file
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@ -40,7 +40,7 @@ module _80_cycloneive_alu (A, B, CI, BI, X, Y, CO);
wire [Y_WIDTH-1:0] AA = A_buf; wire [Y_WIDTH-1:0] AA = A_buf;
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
wire [Y_WIDTH:0] C = {CO, CI}; wire [Y_WIDTH:0] C = {CO, CI};
cycloneive_lcell_comb #(.lut_mask(16'b0110_0110_1000_1000), .sum_lutc_input("cin")) carry_start (.cout(CO[0]), .dataa(BB[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1)); cycloneive_lcell_comb #(.lut_mask(16'b0110_0110_1000_1000), .sum_lutc_input("cin")) carry_start (.cout(CO[0]), .dataa(BB[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
genvar i; genvar i;
generate for (i = 1; i < Y_WIDTH; i = i + 1) begin:slice generate for (i = 1; i < Y_WIDTH; i = i + 1) begin:slice
@ -48,5 +48,5 @@ module _80_cycloneive_alu (A, B, CI, BI, X, Y, CO);
end endgenerate end endgenerate
assign X = AA ^ BB; assign X = AA ^ BB;
endmodule endmodule

32
techlibs/intel/cycloneive/cells_map.v Executable file → Normal file
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@ -38,7 +38,7 @@ module \$_DFF_PP0_ (input D, C, R, output Q);
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule endmodule
module \$__DFFE_PP0 (input D, C, E, R, output Q); module \$__DFFE_PP0 (input D, C, E, R, output Q);
parameter WYSIWYG="TRUE"; parameter WYSIWYG="TRUE";
wire E_i = ~ E; wire E_i = ~ E;
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0)); dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
@ -61,38 +61,38 @@ module \$lut (A, Y);
parameter WIDTH = 0; parameter WIDTH = 0;
parameter LUT = 0; parameter LUT = 0;
input [WIDTH-1:0] A; input [WIDTH-1:0] A;
output Y; output Y;
generate generate
if (WIDTH == 1) begin if (WIDTH == 1) begin
assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
end else end else
if (WIDTH == 2) begin if (WIDTH == 2) begin
cycloneive_lcell_comb #(.lut_mask({4{LUT}}), cycloneive_lcell_comb #(.lut_mask({4{LUT}}),
.sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
.dataa(A[0]), .dataa(A[0]),
.datab(A[1]), .datab(A[1]),
.datac(1'b1), .datac(1'b1),
.datad(1'b1)); .datad(1'b1));
end else end else
if(WIDTH == 3) begin if(WIDTH == 3) begin
cycloneive_lcell_comb #(.lut_mask({2{LUT}}), cycloneive_lcell_comb #(.lut_mask({2{LUT}}),
.sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
.dataa(A[0]), .dataa(A[0]),
.datab(A[1]), .datab(A[1]),
.datac(A[2]), .datac(A[2]),
.datad(1'b1)); .datad(1'b1));
end else end else
if(WIDTH == 4) begin if(WIDTH == 4) begin
cycloneive_lcell_comb #(.lut_mask(LUT), cycloneive_lcell_comb #(.lut_mask(LUT),
.sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y), .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
.dataa(A[0]), .dataa(A[0]),
.datab(A[1]), .datab(A[1]),
.datac(A[2]), .datac(A[2]),
.datad(A[3])); .datad(A[3]));
end else end else
wire _TECHMAP_FAIL_ = 1; wire _TECHMAP_FAIL_ = 1;
endgenerate endgenerate
endmodule endmodule

28
techlibs/intel/cycloneive/cells_sim.v Executable file → Normal file
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@ -25,21 +25,21 @@ module GND (output G);
endmodule // GND endmodule // GND
/* Altera Cyclone IV (E) devices Input Buffer Primitive */ /* Altera Cyclone IV (E) devices Input Buffer Primitive */
module cycloneive_io_ibuf module cycloneive_io_ibuf
(output o, input i, input ibar); (output o, input i, input ibar);
assign ibar = ibar; assign ibar = ibar;
assign o = i; assign o = i;
endmodule // fiftyfivenm_io_ibuf endmodule // fiftyfivenm_io_ibuf
/* Altera Cyclone IV (E) devices Output Buffer Primitive */ /* Altera Cyclone IV (E) devices Output Buffer Primitive */
module cycloneive_io_obuf module cycloneive_io_obuf
(output o, input i, input oe); (output o, input i, input oe);
assign o = i; assign o = i;
assign oe = oe; assign oe = oe;
endmodule // fiftyfivenm_io_obuf endmodule // fiftyfivenm_io_obuf
/* Altera Cyclone IV (E) 4-input non-fracturable LUT Primitive */ /* Altera Cyclone IV (E) 4-input non-fracturable LUT Primitive */
module cycloneive_lcell_comb module cycloneive_lcell_comb
(output combout, cout, (output combout, cout,
input dataa, datab, datac, datad, cin); input dataa, datab, datac, datad, cin);
@ -112,7 +112,7 @@ module cycloneive_lcell_comb
endmodule // cycloneive_lcell_comb endmodule // cycloneive_lcell_comb
/* Altera D Flip-Flop Primitive */ /* Altera D Flip-Flop Primitive */
module dffeas module dffeas
(output q, (output q,
input d, clk, clrn, prn, ena, input d, clk, clrn, prn, ena,
input asdata, aload, sclr, sload); input asdata, aload, sclr, sload);
@ -124,7 +124,7 @@ module dffeas
reg q_tmp; reg q_tmp;
wire reset; wire reset;
reg [7:0] debug_net; reg [7:0] debug_net;
assign reset = (prn && sclr && ~clrn && ena); assign reset = (prn && sclr && ~clrn && ena);
assign q = q_tmp & 1'b1; assign q = q_tmp & 1'b1;
@ -133,7 +133,7 @@ module dffeas
else q_tmp <= d; else q_tmp <= d;
end end
assign q = q_tmp; assign q = q_tmp;
endmodule // dffeas endmodule // dffeas
/* Cyclone IV E altpll clearbox model */ /* Cyclone IV E altpll clearbox model */
@ -174,9 +174,9 @@ module cycloneive_pll
parameter bandwidth = 0; parameter bandwidth = 0;
parameter bandwidth_type = "auto"; parameter bandwidth_type = "auto";
parameter use_dc_coupling = "false"; parameter use_dc_coupling = "false";
parameter lock_high = 0; parameter lock_high = 0;
parameter lock_low = 0; parameter lock_low = 0;
parameter lock_window_ui = "0.05"; parameter lock_window_ui = "0.05";
parameter test_bypass_lock_detect = "off"; parameter test_bypass_lock_detect = "off";
parameter clk0_output_frequency = 0; parameter clk0_output_frequency = 0;
parameter clk0_multiply_by = 0; parameter clk0_multiply_by = 0;
@ -255,16 +255,16 @@ module cycloneive_pll
parameter c4_test_source = -1; parameter c4_test_source = -1;
parameter vco_multiply_by = 0; parameter vco_multiply_by = 0;
parameter vco_divide_by = 0; parameter vco_divide_by = 0;
parameter vco_post_scale = 1; parameter vco_post_scale = 1;
parameter vco_frequency_control = "auto"; parameter vco_frequency_control = "auto";
parameter vco_phase_shift_step = 0; parameter vco_phase_shift_step = 0;
parameter charge_pump_current = 10; parameter charge_pump_current = 10;
parameter loop_filter_r = "1.0"; parameter loop_filter_r = "1.0";
parameter loop_filter_c = 0; parameter loop_filter_c = 0;
parameter pll_compensation_delay = 0; parameter pll_compensation_delay = 0;
parameter lpm_type = "cycloneive_pll"; parameter lpm_type = "cycloneive_pll";
parameter phase_counter_select_width = 3; parameter phase_counter_select_width = 3;
input [1:0] inclk; input [1:0] inclk;
input fbin; input fbin;
input clkswitch; input clkswitch;
@ -288,5 +288,5 @@ module cycloneive_pll
output phasedone; output phasedone;
output vcooverrange; output vcooverrange;
output vcounderrange; output vcounderrange;
endmodule // cycloneive_pll endmodule // cycloneive_pll

8
techlibs/intel/cyclonev/cells_arith.v Executable file → Normal file
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@ -45,10 +45,10 @@ module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO);
//wire [Y_WIDTH:0] C = {CO, CI}; //wire [Y_WIDTH:0] C = {CO, CI};
wire [Y_WIDTH+1:0] COx; wire [Y_WIDTH+1:0] COx;
wire [Y_WIDTH+1:0] C = {COx, CI}; wire [Y_WIDTH+1:0] C = {COx, CI};
/* Start implementation */ /* Start implementation */
(* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1)); (* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
genvar i; genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
if(i==Y_WIDTH-1) begin if(i==Y_WIDTH-1) begin
@ -61,5 +61,5 @@ module _80_altera_a10gx_alu (A, B, CI, BI, X, Y, CO);
endgenerate endgenerate
/* End implementation */ /* End implementation */
assign X = AA ^ BB; assign X = AA ^ BB;
endmodule endmodule

110
techlibs/intel/cyclonev/cells_map.v Executable file → Normal file
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@ -39,7 +39,7 @@ module \$_DFF_PP0_ (input D, C, R, output Q);
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule endmodule
module \$__DFFE_PP0 (input D, C, E, R, output Q); module \$__DFFE_PP0 (input D, C, E, R, output Q);
parameter WYSIWYG="TRUE"; parameter WYSIWYG="TRUE";
wire E_i = ~ E; wire E_i = ~ E;
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0)); dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
@ -60,89 +60,89 @@ module \$lut (A, Y);
parameter WIDTH = 0; parameter WIDTH = 0;
parameter LUT = 0; parameter LUT = 0;
input [WIDTH-1:0] A; input [WIDTH-1:0] A;
output Y; output Y;
generate generate
if (WIDTH == 1) begin if (WIDTH == 1) begin
assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
end end
else else
if (WIDTH == 2) begin if (WIDTH == 2) begin
cyclonev_lcell_comb #(.lut_mask({16{LUT}}), .shared_arith("off"), .extended_lut("off")) cyclonev_lcell_comb #(.lut_mask({16{LUT}}), .shared_arith("off"), .extended_lut("off"))
_TECHMAP_REPLACE_ _TECHMAP_REPLACE_
(.combout(Y), (.combout(Y),
.dataa(A[0]), .dataa(A[0]),
.datab(A[1]), .datab(A[1]),
.datac(1'b1), .datac(1'b1),
.datad(1'b1), .datad(1'b1),
.datae(1'b1), .datae(1'b1),
.dataf(1'b1), .dataf(1'b1),
.datag(1'b1)); .datag(1'b1));
end end
else else
if(WIDTH == 3) begin if(WIDTH == 3) begin
cyclonev_lcell_comb #(.lut_mask({8{LUT}}), .shared_arith("off"), .extended_lut("off")) cyclonev_lcell_comb #(.lut_mask({8{LUT}}), .shared_arith("off"), .extended_lut("off"))
_TECHMAP_REPLACE_ _TECHMAP_REPLACE_
(.combout(Y), (.combout(Y),
.dataa(A[0]), .dataa(A[0]),
.datab(A[1]), .datab(A[1]),
.datac(A[2]), .datac(A[2]),
.datad(1'b1), .datad(1'b1),
.datae(1'b1), .datae(1'b1),
.dataf(1'b1), .dataf(1'b1),
.datag(1'b1)); .datag(1'b1));
end end
else else
if(WIDTH == 4) begin if(WIDTH == 4) begin
cyclonev_lcell_comb #(.lut_mask({4{LUT}}), .shared_arith("off"), .extended_lut("off")) cyclonev_lcell_comb #(.lut_mask({4{LUT}}), .shared_arith("off"), .extended_lut("off"))
_TECHMAP_REPLACE_ _TECHMAP_REPLACE_
(.combout(Y), (.combout(Y),
.dataa(A[0]), .dataa(A[0]),
.datab(A[1]), .datab(A[1]),
.datac(A[2]), .datac(A[2]),
.datad(A[3]), .datad(A[3]),
.datae(1'b1), .datae(1'b1),
.dataf(1'b1), .dataf(1'b1),
.datag(1'b1)); .datag(1'b1));
end end
else else
if(WIDTH == 5) begin if(WIDTH == 5) begin
cyclonev_lcell_comb #(.lut_mask({2{LUT}}), .shared_arith("off"), .extended_lut("off")) cyclonev_lcell_comb #(.lut_mask({2{LUT}}), .shared_arith("off"), .extended_lut("off"))
_TECHMAP_REPLACE_ _TECHMAP_REPLACE_
(.combout(Y), (.combout(Y),
.dataa(A[0]), .dataa(A[0]),
.datab(A[1]), .datab(A[1]),
.datac(A[2]), .datac(A[2]),
.datad(A[3]), .datad(A[3]),
.datae(A[4]), .datae(A[4]),
.dataf(1'b1), .dataf(1'b1),
.datag(1'b1)); .datag(1'b1));
end end
else else
if(WIDTH == 6) begin if(WIDTH == 6) begin
cyclonev_lcell_comb #(.lut_mask(LUT), .shared_arith("off"), .extended_lut("off")) cyclonev_lcell_comb #(.lut_mask(LUT), .shared_arith("off"), .extended_lut("off"))
_TECHMAP_REPLACE_ _TECHMAP_REPLACE_
(.combout(Y), (.combout(Y),
.dataa(A[0]), .dataa(A[0]),
.datab(A[1]), .datab(A[1]),
.datac(A[2]), .datac(A[2]),
.datad(A[3]), .datad(A[3]),
.datae(A[4]), .datae(A[4]),
.dataf(A[5]), .dataf(A[5]),
.datag(1'b1)); .datag(1'b1));
end end
else else
if(WIDTH == 7) begin if(WIDTH == 7) begin
cyclonev_lcell_comb #(.lut_mask(LUT), .shared_arith("off"), .extended_lut("off")) cyclonev_lcell_comb #(.lut_mask(LUT), .shared_arith("off"), .extended_lut("off"))
_TECHMAP_REPLACE_ _TECHMAP_REPLACE_
(.combout(Y), (.combout(Y),
.dataa(A[0]), .dataa(A[0]),
.datab(A[1]), .datab(A[1]),
.datac(A[2]), .datac(A[2]),
.datad(A[3]), .datad(A[3]),
.datae(A[4]), .datae(A[4]),
.dataf(A[5]), .dataf(A[5]),
.datag(A[6])); .datag(A[6]));
end end
else else
wire _TECHMAP_FAIL_ = 1; wire _TECHMAP_FAIL_ = 1;
endgenerate endgenerate

20
techlibs/intel/cyclonev/cells_sim.v Executable file → Normal file
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@ -25,23 +25,23 @@ module GND (output G);
endmodule // GND endmodule // GND
/* Altera Cyclone V devices Input Buffer Primitive */ /* Altera Cyclone V devices Input Buffer Primitive */
module cyclonev_io_ibuf module cyclonev_io_ibuf
(output o, input i, input ibar); (output o, input i, input ibar);
assign ibar = ibar; assign ibar = ibar;
assign o = i; assign o = i;
endmodule // cyclonev_io_ibuf endmodule // cyclonev_io_ibuf
/* Altera Cyclone V devices Output Buffer Primitive */ /* Altera Cyclone V devices Output Buffer Primitive */
module cyclonev_io_obuf module cyclonev_io_obuf
(output o, input i, input oe); (output o, input i, input oe);
assign o = i; assign o = i;
assign oe = oe; assign oe = oe;
endmodule // cyclonev_io_obuf endmodule // cyclonev_io_obuf
/* Altera Cyclone V LUT Primitive */ /* Altera Cyclone V LUT Primitive */
module cyclonev_lcell_comb module cyclonev_lcell_comb
(output combout, cout, sumout, shareout, (output combout, cout, sumout, shareout,
input dataa, datab, datac, datad, input dataa, datab, datac, datad,
input datae, dataf, datag, cin, input datae, dataf, datag, cin,
input sharein); input sharein);
@ -59,8 +59,8 @@ module cyclonev_lcell_comb
// Extended mode uses mux to define the output // Extended mode uses mux to define the output
wire mux_0, mux_1; wire mux_0, mux_1;
// Input for hold the shared LUT mode value // Input for hold the shared LUT mode value
wire shared_lut_alm; wire shared_lut_alm;
// Simulation model of 4-input LUT // Simulation model of 4-input LUT
function lut4; function lut4;
input [15:0] mask; input [15:0] mask;
@ -75,7 +75,7 @@ module cyclonev_lcell_comb
lut4 = dataa ? s1[1] : s1[0]; lut4 = dataa ? s1[1] : s1[0];
end end
endfunction // lut4 endfunction // lut4
// Simulation model of 5-input LUT // Simulation model of 5-input LUT
function lut5; function lut5;
input [31:0] mask; // wp-01003.pdf, page 3: "a 5-LUT can be built with two 4-LUTs and a multiplexer. input [31:0] mask; // wp-01003.pdf, page 3: "a 5-LUT can be built with two 4-LUTs and a multiplexer.
@ -119,7 +119,7 @@ endmodule // cyclonev_lcell_comb
/* Altera D Flip-Flop Primitive */ /* Altera D Flip-Flop Primitive */
module dffeas module dffeas
(output q, (output q,
input d, clk, clrn, prn, ena, input d, clk, clrn, prn, ena,
input asdata, aload, sclr, sload); input asdata, aload, sclr, sload);
@ -131,7 +131,7 @@ module dffeas
reg q_tmp; reg q_tmp;
wire reset; wire reset;
reg [7:0] debug_net; reg [7:0] debug_net;
assign reset = (prn && sclr && ~clrn && ena); assign reset = (prn && sclr && ~clrn && ena);
assign q = q_tmp & 1'b1; assign q = q_tmp & 1'b1;
@ -140,5 +140,5 @@ module dffeas
else q_tmp <= d; else q_tmp <= d;
end end
assign q = q_tmp; assign q = q_tmp;
endmodule // dffeas endmodule // dffeas

8
techlibs/intel/max10/cells_arith.v Executable file → Normal file
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@ -45,10 +45,10 @@ module _80_altera_max10_alu (A, B, CI, BI, X, Y, CO);
//wire [Y_WIDTH:0] C = {CO, CI}; //wire [Y_WIDTH:0] C = {CO, CI};
wire [Y_WIDTH+1:0] COx; wire [Y_WIDTH+1:0] COx;
wire [Y_WIDTH+1:0] C = {COx, CI}; wire [Y_WIDTH+1:0] C = {COx, CI};
/* Start implementation */ /* Start implementation */
(* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1)); (* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
genvar i; genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
if(i==Y_WIDTH-1) begin if(i==Y_WIDTH-1) begin
@ -61,5 +61,5 @@ module _80_altera_max10_alu (A, B, CI, BI, X, Y, CO);
endgenerate endgenerate
/* End implementation */ /* End implementation */
assign X = AA ^ BB; assign X = AA ^ BB;
endmodule endmodule

4
techlibs/intel/max10/cells_map.v Executable file → Normal file
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@ -39,7 +39,7 @@ module \$_DFF_PP0_ (input D, C, R, output Q);
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0)); dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule endmodule
module \$__DFFE_PP0 (input D, C, E, R, output Q); module \$__DFFE_PP0 (input D, C, E, R, output Q);
parameter WYSIWYG="TRUE"; parameter WYSIWYG="TRUE";
wire E_i = ~ E; wire E_i = ~ E;
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0)); dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
@ -62,7 +62,7 @@ module \$lut (A, Y);
parameter WIDTH = 0; parameter WIDTH = 0;
parameter LUT = 0; parameter LUT = 0;
input [WIDTH-1:0] A; input [WIDTH-1:0] A;
output Y; output Y;
generate generate
if (WIDTH == 1) begin if (WIDTH == 1) begin
assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function

28
techlibs/intel/max10/cells_sim.v Executable file → Normal file
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@ -26,21 +26,21 @@ module GND (output G);
endmodule // GND endmodule // GND
/* Altera MAX10 devices Input Buffer Primitive */ /* Altera MAX10 devices Input Buffer Primitive */
module fiftyfivenm_io_ibuf module fiftyfivenm_io_ibuf
(output o, input i, input ibar); (output o, input i, input ibar);
assign ibar = ibar; assign ibar = ibar;
assign o = i; assign o = i;
endmodule // fiftyfivenm_io_ibuf endmodule // fiftyfivenm_io_ibuf
/* Altera MAX10 devices Output Buffer Primitive */ /* Altera MAX10 devices Output Buffer Primitive */
module fiftyfivenm_io_obuf module fiftyfivenm_io_obuf
(output o, input i, input oe); (output o, input i, input oe);
assign o = i; assign o = i;
assign oe = oe; assign oe = oe;
endmodule // fiftyfivenm_io_obuf endmodule // fiftyfivenm_io_obuf
/* Altera MAX10 4-input non-fracturable LUT Primitive */ /* Altera MAX10 4-input non-fracturable LUT Primitive */
module fiftyfivenm_lcell_comb module fiftyfivenm_lcell_comb
(output combout, cout, (output combout, cout,
input dataa, datab, datac, datad, cin); input dataa, datab, datac, datad, cin);
@ -113,7 +113,7 @@ module fiftyfivenm_lcell_comb
endmodule // fiftyfivenm_lcell_comb endmodule // fiftyfivenm_lcell_comb
/* Altera D Flip-Flop Primitive */ /* Altera D Flip-Flop Primitive */
module dffeas module dffeas
(output q, (output q,
input d, clk, clrn, prn, ena, input d, clk, clrn, prn, ena,
input asdata, aload, sclr, sload); input asdata, aload, sclr, sload);
@ -125,7 +125,7 @@ module dffeas
reg q_tmp; reg q_tmp;
wire reset; wire reset;
reg [7:0] debug_net; reg [7:0] debug_net;
assign reset = (prn && sclr && ~clrn && ena); assign reset = (prn && sclr && ~clrn && ena);
assign q = q_tmp & 1'b1; assign q = q_tmp & 1'b1;
@ -134,7 +134,7 @@ module dffeas
else q_tmp <= d; else q_tmp <= d;
end end
assign q = q_tmp; assign q = q_tmp;
endmodule // dffeas endmodule // dffeas
/* MAX10 altpll clearbox model */ /* MAX10 altpll clearbox model */
@ -175,9 +175,9 @@ module fiftyfivenm_pll
parameter bandwidth = 0; parameter bandwidth = 0;
parameter bandwidth_type = "auto"; parameter bandwidth_type = "auto";
parameter use_dc_coupling = "false"; parameter use_dc_coupling = "false";
parameter lock_high = 0; parameter lock_high = 0;
parameter lock_low = 0; parameter lock_low = 0;
parameter lock_window_ui = "0.05"; parameter lock_window_ui = "0.05";
parameter test_bypass_lock_detect = "off"; parameter test_bypass_lock_detect = "off";
parameter clk0_output_frequency = 0; parameter clk0_output_frequency = 0;
parameter clk0_multiply_by = 0; parameter clk0_multiply_by = 0;
@ -256,16 +256,16 @@ module fiftyfivenm_pll
parameter c4_test_source = -1; parameter c4_test_source = -1;
parameter vco_multiply_by = 0; parameter vco_multiply_by = 0;
parameter vco_divide_by = 0; parameter vco_divide_by = 0;
parameter vco_post_scale = 1; parameter vco_post_scale = 1;
parameter vco_frequency_control = "auto"; parameter vco_frequency_control = "auto";
parameter vco_phase_shift_step = 0; parameter vco_phase_shift_step = 0;
parameter charge_pump_current = 10; parameter charge_pump_current = 10;
parameter loop_filter_r = "1.0"; parameter loop_filter_r = "1.0";
parameter loop_filter_c = 0; parameter loop_filter_c = 0;
parameter pll_compensation_delay = 0; parameter pll_compensation_delay = 0;
parameter lpm_type = "fiftyfivenm_pll"; parameter lpm_type = "fiftyfivenm_pll";
parameter phase_counter_select_width = 3; parameter phase_counter_select_width = 3;
input [1:0] inclk; input [1:0] inclk;
input fbin; input fbin;
input clkswitch; input clkswitch;
@ -288,5 +288,5 @@ module fiftyfivenm_pll
output phasedone; output phasedone;
output vcooverrange; output vcooverrange;
output vcounderrange; output vcounderrange;
endmodule // cycloneive_pll endmodule // cycloneive_pll

6
techlibs/intel/synth_intel.cc Executable file → Normal file
View File

@ -170,7 +170,7 @@ struct SynthIntelPass : public ScriptPass {
{ {
run("synth -run coarse"); run("synth -run coarse");
} }
if (!nobram && check_label("bram", "(skip if -nobram)")) if (!nobram && check_label("bram", "(skip if -nobram)"))
{ {
run("memory_bram -rules +/intel/common/brams.txt"); run("memory_bram -rules +/intel/common/brams.txt");
@ -179,7 +179,7 @@ struct SynthIntelPass : public ScriptPass {
if (check_label("fine")) if (check_label("fine"))
{ {
run("opt -fast -mux_undef -undriven -fine -full"); run("opt -fast -mux_undef -undriven -fine -full");
run("memory_map"); run("memory_map");
run("opt -undriven -fine"); run("opt -undriven -fine");
run("dffsr2dff"); run("dffsr2dff");
@ -209,7 +209,7 @@ struct SynthIntelPass : public ScriptPass {
run("techmap -map +/intel/max10/cells_map.v"); run("techmap -map +/intel/max10/cells_map.v");
else if(family_opt=="a10gx") else if(family_opt=="a10gx")
run("techmap -map +/intel/a10gx/cells_map.v"); run("techmap -map +/intel/a10gx/cells_map.v");
else if(family_opt=="cyclonev") else if(family_opt=="cyclonev")
run("techmap -map +/intel/cyclonev/cells_map.v"); run("techmap -map +/intel/cyclonev/cells_map.v");
else if(family_opt=="cycloneiv") else if(family_opt=="cycloneiv")
run("techmap -map +/intel/cycloneiv/cells_map.v"); run("techmap -map +/intel/cycloneiv/cells_map.v");