Clean whitespace and permissions in techlibs/intel

2017-10-04 17:01:30 -07:00 · 2017-10-04 17:01:30 -07:00 · 50bcd9a728
parent fc3378916d
commit 50bcd9a728
21 changed files with 190 additions and 190 deletions
--- a/techlibs/intel/Makefile.inc
+++ b/techlibs/intel/Makefile.inc
--- a/techlibs/intel/a10gx/cells_arith.v
+++ b/techlibs/intel/a10gx/cells_arith.v
--- a/techlibs/intel/a10gx/cells_map.v
+++ b/techlibs/intel/a10gx/cells_map.v
--- a/techlibs/intel/a10gx/cells_sim.v
+++ b/techlibs/intel/a10gx/cells_sim.v
--- a/techlibs/intel/common/brams.txt
+++ b/techlibs/intel/common/brams.txt
--- a/techlibs/intel/common/brams_map.v
+++ b/techlibs/intel/common/brams_map.v
--- a/techlibs/intel/common/m9k_bb.v
+++ b/techlibs/intel/common/m9k_bb.v
--- a/techlibs/intel/cycloneiv/cells_arith.v
+++ b/techlibs/intel/cycloneiv/cells_arith.v
--- a/techlibs/intel/cycloneiv/cells_map.v
+++ b/techlibs/intel/cycloneiv/cells_map.v
--- a/techlibs/intel/cycloneiv/cells_sim.v
+++ b/techlibs/intel/cycloneiv/cells_sim.v
--- a/techlibs/intel/cycloneive/arith_map.v
+++ b/techlibs/intel/cycloneive/arith_map.v
--- a/techlibs/intel/cycloneive/cells_map.v
+++ b/techlibs/intel/cycloneive/cells_map.v
--- a/techlibs/intel/cycloneive/cells_sim.v
+++ b/techlibs/intel/cycloneive/cells_sim.v
--- a/techlibs/intel/cyclonev/cells_arith.v
+++ b/techlibs/intel/cyclonev/cells_arith.v
--- a/techlibs/intel/cyclonev/cells_map.v
+++ b/techlibs/intel/cyclonev/cells_map.v
--- a/techlibs/intel/cyclonev/cells_sim.v
+++ b/techlibs/intel/cyclonev/cells_sim.v
--- a/techlibs/intel/max10/cells_arith.v
+++ b/techlibs/intel/max10/cells_arith.v
--- a/techlibs/intel/max10/cells_map.v
+++ b/techlibs/intel/max10/cells_map.v
--- a/techlibs/intel/max10/cells_sim.v
+++ b/techlibs/intel/max10/cells_sim.v
--- a/techlibs/intel/synth_intel.cc
+++ b/techlibs/intel/synth_intel.cc