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Merge pull request #1576 from YosysHQ/eddie/opt_merge_init 

opt_merge: discard \init of '$' cells with 'Q' port when merging
This commit is contained in:
Eddie Hung 2020-02-05 14:56:26 -08:00 committed by GitHub
parent 6eb7e925a1 a855f23f22
commit 505557e93e
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 65 additions and 1 deletions
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17
passes/opt/opt_merge.cc
View File

@ -222,7 +222,9 @@ struct OptMergeWorker
return true; return true;
} }
if (cell1->type.begins_with("$") && conn1.count(ID(Q)) != 0) { if (conn1.count(ID(Q)) != 0 && (cell1->type.begins_with("$dff") || cell1->type.begins_with("$dlatch") ||
cell1->type.begins_with("$_DFF") || cell1->type.begins_with("$_DLATCH") || cell1->type.begins_with("$_SR_") ||
cell1->type.in("$adff", "$sr", "$ff", "$_FF_"))) {
std::vector<RTLIL::SigBit> q1 = dff_init_map(cell1->getPort(ID(Q))).to_sigbit_vector(); std::vector<RTLIL::SigBit> q1 = dff_init_map(cell1->getPort(ID(Q))).to_sigbit_vector();
std::vector<RTLIL::SigBit> q2 = dff_init_map(cell2->getPort(ID(Q))).to_sigbit_vector(); std::vector<RTLIL::SigBit> q2 = dff_init_map(cell2->getPort(ID(Q))).to_sigbit_vector();
for (size_t i = 0; i < q1.size(); i++) for (size_t i = 0; i < q1.size(); i++)
@ -323,6 +325,19 @@ struct OptMergeWorker
log_signal(it.second), log_signal(other_sig)); log_signal(it.second), log_signal(other_sig));
module->connect(RTLIL::SigSig(it.second, other_sig)); module->connect(RTLIL::SigSig(it.second, other_sig));
assign_map.add(it.second, other_sig); assign_map.add(it.second, other_sig);
if (it.first == ID(Q) && (cell->type.begins_with("$dff") || cell->type.begins_with("$dlatch") ||
cell->type.begins_with("$_DFF") || cell->type.begins_with("$_DLATCH") || cell->type.begins_with("$_SR_") ||
cell->type.in("$adff", "$sr", "$ff", "$_FF_"))) {
for (auto c : it.second.chunks()) {
auto jt = c.wire->attributes.find(ID(init));
if (jt == c.wire->attributes.end())
continue;
for (int i = c.offset; i < c.offset + c.width; i++)
jt->second[i] = State::Sx;
}
dff_init_map.add(it.second, Const(State::Sx, GetSize(it.second)));
}
} }
} }
log_debug(" Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str()); log_debug(" Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str());

49
tests/opt/opt_merge_init.ys Normal file
View File

@ -0,0 +1,49 @@
read_verilog -icells <<EOT
module top(input clk, i, (* init = 1'b0 *) output o, p);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) ffo (
.CLK(clk),
.D(i),
.Q(o)
);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) ffp (
.CLK(clk),
.D(i),
.Q(p)
);
endmodule
EOT
opt_merge
select -assert-count 1 a:init=1'0
design -reset
read_verilog -icells <<EOT
module top(input clk, i, (* init = 2'b11 *) output [1:0] o);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) ff1 (
.CLK(clk),
.D(i),
.Q(o[1])
);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) ff0 (
.CLK(clk),
.D(i),
.Q(o[0])
);
endmodule
EOT
opt_merge
select -assert-count 1 a:init=2'bx1