riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Add "verilog_defines -list" and "verilog_defines -reset" 

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-10-21 13:35:31 +02:00
parent 4033ff8c2e
commit 5025aab8c9
1 changed files with 16 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
frontends/verilog/verilog_frontend.cc
View File

@ -553,6 +553,12 @@ struct VerilogDefines : public Pass {
log(" -Uname[=definition]\n");
log(" undefine the preprocessor symbol 'name'\n");
log("\n");
log(" -reset\n");
log(" clear list of defined preprocessor symbols\n");
log("\n");
log(" -list\n");
log(" list currently defined preprocessor symbols\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
@ -588,6 +594,16 @@ struct VerilogDefines : public Pass {
design->verilog_defines.erase(name);
continue;
}
if (arg == "-reset") {
design->verilog_defines.clear();
continue;
}
if (arg == "-list") {
for (auto &it : design->verilog_defines) {
log("`define %s%s %s\n", it.first.c_str(), it.second.second ? "()" : "", it.second.first.c_str());
}
continue;
}
break;
}