mirror of https://github.com/YosysHQ/yosys.git
Cope with abc9_arrival as string
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4eaa45091c
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5017be6445
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@ -199,6 +199,7 @@ struct XAigerWriter
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dict<SigBit, pool<IdString>> bit_drivers, bit_users;
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TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
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bool abc9_box_seen = false;
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std::vector<int> arrivals;
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for (auto cell : module->selected_cells()) {
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if (cell->type == "$_NOT_")
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@ -284,16 +285,20 @@ struct XAigerWriter
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}
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}
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if (is_output) {
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int arrival = 0;
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arrivals.clear();
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if (port_wire) {
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auto it = port_wire->attributes.find("\\abc9_arrival");
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if (it != port_wire->attributes.end()) {
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if (it->second.flags != 0)
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log_error("Attribute 'abc9_arrival' on port '%s' of module '%s' is not an integer.\n", log_id(port_wire), log_id(cell->type));
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arrival = it->second.as_int();
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if (it->second.flags == 0)
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arrivals.push_back(it->second.as_int());
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else
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for (const auto &tok : split_tokens(it->second.decode_string()))
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arrivals.push_back(atoi(tok.c_str()));
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}
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}
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log_assert(GetSize(arrivals) <= 1 || GetSize(arrivals) == GetSize(c.second));
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auto it = arrivals.begin();
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for (auto b : c.second) {
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Wire *w = b.wire;
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if (!w) continue;
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@ -303,8 +308,12 @@ struct XAigerWriter
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alias_map[O] = b;
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undriven_bits.erase(O);
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if (arrival)
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arrival_times[b] = arrival;
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if (!arrivals.empty()) {
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if (arrivals.size() == 1)
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arrival_times[b] = *it;
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else
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arrival_times[b] = *it++;
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}
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}
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}
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}
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