mirror of https://github.com/YosysHQ/yosys.git
Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4
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@ -111,20 +111,24 @@ struct Ice40WrapCarryPass : public Pass {
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auto carry = module->addCell(NEW_ID, ID(SB_CARRY));
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auto carry = module->addCell(NEW_ID, ID(SB_CARRY));
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carry->setPort(ID(I0), cell->getPort(ID(A)));
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carry->setPort(ID(I0), cell->getPort(ID(A)));
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carry->setPort(ID(I1), cell->getPort(ID(B)));
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carry->setPort(ID(I1), cell->getPort(ID(B)));
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carry->setPort(ID(CI), cell->getPort(ID(CO)));
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carry->setPort(ID(CI), cell->getPort(ID(CI)));
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carry->setPort(ID(CO), cell->getPort(ID(CO)));
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module->swap_names(carry, cell);
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module->swap_names(carry, cell);
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auto lut = module->addCell(cell->attributes.at(ID(SB_LUT4.name)).decode_string(), ID(SB_LUT4));
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auto lut_name = cell->attributes.at(ID(SB_LUT4.name), Const(NEW_ID.str())).decode_string();
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lut->setParam(ID(WIDTH), 4);
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auto lut = module->addCell(lut_name, ID(SB_LUT4));
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lut->setParam(ID(LUT), cell->getParam(ID(LUT)));
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lut->setParam(ID(LUT_INIT), cell->getParam(ID(LUT)));
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lut->setPort(ID(A), { cell->getPort(ID(I0)), cell->getPort(ID(A)), cell->getPort(ID(B)), cell->getPort(ID(I3)) });
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lut->setPort(ID(I0), cell->getPort(ID(I0)));
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lut->setPort(ID(Y), cell->getPort(ID(O)));
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lut->setPort(ID(I1), cell->getPort(ID(A)));
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lut->setPort(ID(I2), cell->getPort(ID(B)));
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lut->setPort(ID(I3), cell->getPort(ID(I3)));
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lut->setPort(ID(O), cell->getPort(ID(O)));
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for (const auto &a : cell->attributes)
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for (const auto &a : cell->attributes)
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if (a.first.begins_with("\\SB_CARRY.\\"))
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if (a.first.begins_with("\\SB_CARRY.\\"))
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carry->attributes[a.first.c_str() + strlen("\\SB_CARRY.")] = a.second;
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carry->attributes[a.first.c_str() + strlen("\\SB_CARRY.")] = a.second;
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else if (a.first.begins_with("\\SB_LUT4.\\"))
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else if (a.first.begins_with("\\SB_LUT4.\\"))
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lut->attributes[a.first.c_str() + strlen("\\SB_LUT4.")] = a.second;
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lut->attributes[a.first.c_str() + strlen("\\SB_LUT4.")] = a.second;
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else if (a.first.in(ID(SB_LUT4.name), ID::keep))
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else if (a.first.in(ID(SB_LUT4.name), ID::keep, ID(module_not_derived), ID(src)))
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continue;
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continue;
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else
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else
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log_abort();
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log_abort();
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@ -50,7 +50,7 @@ module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
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// A[2]: 1111 0000 1111 0000
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// A[2]: 1111 0000 1111 0000
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// A[3]: 1111 1111 0000 0000
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// A[3]: 1111 1111 0000 0000
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.LUT(16'b 0110_1001_1001_0110)
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.LUT(16'b 0110_1001_1001_0110)
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) fadd (
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) carry (
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.A(AA[i]),
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.A(AA[i]),
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.B(BB[i]),
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.B(BB[i]),
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.CI(C[i]),
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.CI(C[i]),
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