mirror of https://github.com/YosysHQ/yosys.git
genrtlil: add width detection for AST_PREFIX nodes
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@ -993,6 +993,14 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
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break;
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break;
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}
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}
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case AST_PREFIX:
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// Prefix nodes always resolve to identifiers in generate loops, so we
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// can simply perform the resolution to determine the sign and width.
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simplify(true, false, false, 1, -1, false, false);
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log_assert(type == AST_IDENTIFIER);
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detectSignWidthWorker(width_hint, sign_hint, found_real);
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break;
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case AST_FCALL:
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case AST_FCALL:
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if (str == "\\$anyconst" || str == "\\$anyseq" || str == "\\$allconst" || str == "\\$allseq") {
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if (str == "\\$anyconst" || str == "\\$anyseq" || str == "\\$allconst" || str == "\\$allseq") {
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if (GetSize(children) == 1) {
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if (GetSize(children) == 1) {
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@ -0,0 +1,18 @@
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module top(
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input wire x,
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output reg y
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);
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localparam I = 1;
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genvar i;
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generate
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for (i = 0; i < 1; i = i + 1) begin : blk
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wire [i:i] z = x;
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end
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endgenerate
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always @* begin
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case (blk[I - 1].z)
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1: y = 0;
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0: y = 1;
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endcase
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end
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endmodule
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