riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge 42e4610e3a into 18b616578a

This commit is contained in:
Aki 2024-11-20 21:30:26 +01:00 committed by GitHub
parent 18b616578a 42e4610e3a
commit 4fad7b0f83
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
2 changed files with 28 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
frontends/rtlil/rtlil_parser.y
View File

@ -187,7 +187,11 @@ wire_stmt:
wire_options: wire_options:
wire_options TOK_WIDTH TOK_INT { wire_options TOK_WIDTH TOK_INT {
if ($3 > 0x1000000) {
rtlil_frontend_yyerror("RTLIL error: invalid wire width, must be less than 2^24");
} else {
current_wire->width = $3; current_wire->width = $3;
}
} | } |
wire_options TOK_WIDTH TOK_INVALID { wire_options TOK_WIDTH TOK_INVALID {
rtlil_frontend_yyerror("RTLIL error: invalid wire width"); rtlil_frontend_yyerror("RTLIL error: invalid wire width");

23
kernel/rtlil.cc
View File

@ -216,6 +216,9 @@ std::string& Const::get_str() const {
RTLIL::Const::Const(const std::string &str) RTLIL::Const::Const(const std::string &str)
{ {
if (str.size() * 8 > 0x1000000)
log_error("RTLIL Const width must be less than 2^24");
flags = RTLIL::CONST_FLAG_STRING; flags = RTLIL::CONST_FLAG_STRING;
new ((void*)&str_) std::string(str); new ((void*)&str_) std::string(str);
tag = backing_tag::string; tag = backing_tag::string;
@ -223,6 +226,12 @@ RTLIL::Const::Const(const std::string &str)
RTLIL::Const::Const(long long val, int width) RTLIL::Const::Const(long long val, int width)
{ {
if (width < 0)
log_error("RTLIL Const width must not be negative");
if (width > 0x1000000)
log_error("RTLIL Const width must be less than 2^24");
flags = RTLIL::CONST_FLAG_NONE; flags = RTLIL::CONST_FLAG_NONE;
new ((void*)&bits_) bitvectype(); new ((void*)&bits_) bitvectype();
tag = backing_tag::bits; tag = backing_tag::bits;
@ -236,6 +245,12 @@ RTLIL::Const::Const(long long val, int width)
RTLIL::Const::Const(RTLIL::State bit, int width) RTLIL::Const::Const(RTLIL::State bit, int width)
{ {
if (width < 0)
log_error("RTLIL Const width must not be negative");
if (width > 0x1000000)
log_error("RTLIL Const width must be less than 2^24");
flags = RTLIL::CONST_FLAG_NONE; flags = RTLIL::CONST_FLAG_NONE;
new ((void*)&bits_) bitvectype(); new ((void*)&bits_) bitvectype();
tag = backing_tag::bits; tag = backing_tag::bits;
@ -247,6 +262,10 @@ RTLIL::Const::Const(RTLIL::State bit, int width)
RTLIL::Const::Const(const std::vector<bool> &bits) RTLIL::Const::Const(const std::vector<bool> &bits)
{ {
if (bits.size() > 0x1000000)
log_error("RTLIL Const width must be less than 2^24");
flags = RTLIL::CONST_FLAG_NONE; flags = RTLIL::CONST_FLAG_NONE;
new ((void*)&bits_) bitvectype(); new ((void*)&bits_) bitvectype();
tag = backing_tag::bits; tag = backing_tag::bits;
@ -446,6 +465,10 @@ std::string RTLIL::Const::as_string(const char* any) const
RTLIL::Const RTLIL::Const::from_string(const std::string &str) RTLIL::Const RTLIL::Const::from_string(const std::string &str)
{ {
if (str.size() > 0x1000000)
log_error("RTLIL width must be less than 2^24");
Const c; Const c;
bitvectype& bv = c.get_bits(); bitvectype& bv = c.get_bits();
bv.reserve(str.size()); bv.reserve(str.size());