mirror of https://github.com/YosysHQ/yosys.git
Fixed two bugs in mem2reg functionality in AST frontend
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79910a5547
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@ -801,7 +801,8 @@ skip_dynamic_range_lvalue_expansion:;
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while (wire_en->simplify(true, false, false, 1, -1, false)) { }
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std::vector<RTLIL::State> x_bits;
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x_bits.push_back(RTLIL::State::Sx);
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for (int i = 0; i < mem_width; i++)
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x_bits.push_back(RTLIL::State::Sx);
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AstNode *assign_addr = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_bits(x_bits, false));
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assign_addr->children[0]->str = id_addr;
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@ -1280,13 +1281,15 @@ void AstNode::mem2reg_as_needed_pass2(std::set<AstNode*> &mem2reg_set, AstNode *
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AstNode *wire_addr = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(addr_bits-1, true), mkconst_int(0, true)));
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wire_addr->str = id_addr;
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wire_addr->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
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if (block)
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wire_addr->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
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mod->children.push_back(wire_addr);
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while (wire_addr->simplify(true, false, false, 1, -1, false)) { }
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AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true)));
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wire_data->str = id_data;
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wire_data->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
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if (block)
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wire_data->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
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mod->children.push_back(wire_data);
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while (wire_data->simplify(true, false, false, 1, -1, false)) { }
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@ -1308,7 +1311,8 @@ void AstNode::mem2reg_as_needed_pass2(std::set<AstNode*> &mem2reg_set, AstNode *
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}
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std::vector<RTLIL::State> x_bits;
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x_bits.push_back(RTLIL::State::Sx);
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for (int i = 0; i < mem_width; i++)
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x_bits.push_back(RTLIL::State::Sx);
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AstNode *cond_node = new AstNode(AST_COND, new AstNode(AST_DEFAULT), new AstNode(AST_BLOCK));
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AstNode *assign_reg = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER), AstNode::mkconst_bits(x_bits, false));
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