verilog: support module scope identifiers in parametric modules

This commit is contained in:
Zachary Snow 2021-03-04 14:07:56 -05:00 committed by Zachary Snow
parent 3d9698153f
commit 4f187d53c5
2 changed files with 37 additions and 4 deletions

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@ -1691,11 +1691,15 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
if (type == AST_IDENTIFIER) { if (type == AST_IDENTIFIER) {
if (current_scope.count(str) == 0) { if (current_scope.count(str) == 0) {
AstNode *current_scope_ast = (current_ast_mod == nullptr) ? current_ast : current_ast_mod; AstNode *current_scope_ast = (current_ast_mod == nullptr) ? current_ast : current_ast_mod;
const std::string& mod_scope = current_scope_ast->str; size_t pos = str.find('.', 1);
if (str[0] == '\\' && str.substr(0, mod_scope.size()) == mod_scope) { if (str[0] == '\\' && pos != std::string::npos) {
std::string new_str = "\\" + str.substr(mod_scope.size() + 1); std::string new_str = "\\" + str.substr(pos + 1);
if (current_scope.count(new_str)) { if (current_scope.count(new_str)) {
str = new_str; std::string prefix = str.substr(0, pos);
auto it = current_scope_ast->attributes.find(ID::hdlname);
if ((it != current_scope_ast->attributes.end() && it->second->str == prefix)
|| prefix == current_scope_ast->str)
str = new_str;
} }
} }
for (auto node : current_scope_ast->children) { for (auto node : current_scope_ast->children) {

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@ -0,0 +1,29 @@
`default_nettype none
module Example(o1, o2);
parameter [31:0] v1 = 10;
parameter [31:0] v2 = 20;
output [31:0] o1, o2;
assign Example.o1 = Example.v1;
assign Example.o2 = Example.v2;
endmodule
module ExampleLong(o1, o2);
parameter [31:0] ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum1 = 10;
parameter [31:0] ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum2 = 20;
output [31:0] o1, o2;
assign ExampleLong.o1 = ExampleLong.ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum1;
assign ExampleLong.o2 = ExampleLong.ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum2;
endmodule
module top(
output [31:0] a1, a2, b1, b2, c1, c2,
output [31:0] d1, d2, e1, e2, f1, f2
);
Example a(a1, a2);
Example #(1) b(b1, b2);
Example #(1, 2) c(c1, c2);
ExampleLong d(d1, d2);
ExampleLong #(1) e(e1, e2);
ExampleLong #(1, 2) f(f1, f2);
endmodule