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Fix typo

This commit is contained in:
Eddie Hung 2019-07-23 13:58:56 -07:00
parent 33c984a044
commit 4f11ff8ebd
1 changed files with 21 additions and 13 deletions
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34
passes/pmgen/ice40_dsp.pmg
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@ -1,8 +1,8 @@
pattern ice40_dsp pattern ice40_dsp
state <SigBit> clock state <SigBit> clock
state <bool> clock_pol sigO_signed state <bool> clock_pol sigCD_signed
state <SigSpec> sigA sigB sigH sigO state <SigSpec> sigA sigB sigCD sigH sigO
state <Cell*> addAB muxAB state <Cell*> addAB muxAB
match mul match mul
@ -94,14 +94,16 @@ match addB
optional optional
endmatch endmatch
code addAB sigO sigO_signed code addAB sigCD sigCD_signed sigO
if (addA) { if (addA) {
addAB = addA; addAB = addA;
sigO_signed = param(addAB, \B_SIGNED).as_bool(); sigCD = port(addAB, \B);
sigCD_signed = param(addAB, \B_SIGNED).as_bool();
} }
if (addB) { if (addB) {
addAB = addB; addAB = addB;
sigO_signed = param(addAB, \A_SIGNED).as_bool(); sigCD = port(addAB, \A);
sigCD_signed = param(addAB, \A_SIGNED).as_bool();
} }
if (addAB) { if (addAB) {
int natural_mul_width = GetSize(sigA) + GetSize(sigB); int natural_mul_width = GetSize(sigA) + GetSize(sigB);
@ -118,30 +120,36 @@ code addAB sigO sigO_signed
endcode endcode
match muxA match muxA
if addAB if sigCD.empty()
select muxA->type.in($mux) select muxA->type.in($mux)
select nusers(port(muxA, \A)) == 2 select nusers(port(muxA, \A)) == 2
index <SigSpec> port(muxA, \A) === port(addAB, \Y) index <SigSpec> port(muxA, \A) === sigO
optional optional
endmatch endmatch
match muxB match muxB
if addAB if sigCD.empty()
if !muxA if !muxA
select muxB->type.in($mux) select muxB->type.in($mux)
select nusers(port(muxB, \B)) == 2 select nusers(port(muxB, \B)) == 2
index <SigSpec> port(muxB, \B) === port(addAB, \Y) index <SigSpec> port(muxB, \B) === sigO
optional optional
endmatch endmatch
code muxAB sigO code muxAB sigCD sigCD_signed sigO
muxAB = addAB; muxAB = addAB;
if (muxA) if (muxA) {
muxAB = muxA; muxAB = muxA;
if (muxB) sigCD = port(muxAB, \B);
}
if (muxB) {
muxAB = muxB; muxAB = muxB;
if (muxA || muxB) sigCD = port(muxAB, \A);
}
if (muxA || muxB) {
sigO = port(muxAB, \Y); sigO = port(muxAB, \Y);
sigCD_signed = addAB && param(addAB, \A_SIGNED).as_bool() && param(addAB, \B_SIGNED).as_bool();
}
endcode endcode
match ffO_lo match ffO_lo