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Merge pull request #1136 from YosysHQ/xaig_ice40_wire_del 

abc9: Add wire delays to synth_ice40
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Eddie Hung 2019-06-26 08:51:11 -07:00 committed by GitHub
parent 5db96b8aec 0dd850e655
commit 4f0cb34495
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1 changed files with 10 additions and 2 deletions
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12
techlibs/ice40/synth_ice40.cc
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@ -331,8 +331,16 @@ struct SynthIce40Pass : public ScriptPass
run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)"); run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
} }
if (!noabc) { if (!noabc) {
if (abc == "abc9") if (abc == "abc9") {
run(abc + stringf(" -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)"); int wire_delay;
if (device_opt == "lp")
wire_delay = 400;
else if (device_opt == "u")
wire_delay = 750;
else
wire_delay = 250;
run(abc + stringf(" -W %d -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
}
else else
run(abc + " -dress -lut 4", "(skip if -noabc)"); run(abc + " -dress -lut 4", "(skip if -noabc)");
} }