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Add tests for sub too

This commit is contained in:
Eddie Hung 2019-07-19 12:50:11 -07:00
parent 3839bd50f2
commit 4e9b1d36fa
1 changed files with 48 additions and 1 deletions
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49
tests/various/wreduce.ys
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@ -5,7 +5,7 @@ module wreduce_add_test(input [3:0] i, input [7:0] j, output [7:0] o);
endmodule endmodule
EOT EOT
hierarchy -top wreduce_add_test hierarchy -auto-top
proc proc
design -save gold design -save gold
@ -20,3 +20,50 @@ design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter sat -verify -prove-asserts -show-ports miter
### X - 0
read_verilog <<EOT
module wreduce_sub_test1(input [3:0] i, input [7:0] j, output [7:0] o);
assign o = j - (i << 4);
endmodule
EOT
hierarchy -auto-top
proc
design -save gold
prep
select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 %i %i
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
### 0 - X
read_verilog <<EOT
module wreduce_sub_test1(input [3:0] i, input [7:0] j, output [7:0] o);
assign o = (i << 4) - j;
endmodule
EOT
hierarchy -auto-top
proc
design -save gold
prep
select -assert-count 1 t:$sub r:A_WIDTH=8 r:B_WIDTH=8 %i %i
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter