riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fix in Verific SVA importer handling of until_with 

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-03-01 19:37:36 +01:00
parent 90ae426078
commit 4e5f1f59d6
1 changed files with 5 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
frontends/verific/verificsva.cc
View File

@ -974,11 +974,6 @@ struct VerificSvaImporter
SvaFsm until_fsm(module, clock, clockpol, disable_iff);
node = parse_sequence(&until_fsm, until_fsm.startNode, until_net);
if (until_with) {
int next_node = until_fsm.createNode();
until_fsm.createEdge(node, next_node);
node = next_node;
}
until_fsm.createLink(node, until_fsm.acceptNode);
SigBit until_match = until_fsm.getAccept();
@ -993,9 +988,12 @@ struct VerificSvaImporter
antecedent_match_q->attributes["\\init"] = Const(0, 1);
antecedent_match = module->Or(NEW_ID, antecedent_match, antecedent_match_q);
antecedent_match = module->And(NEW_ID, antecedent_match, not_until_match);
SigBit antecedent_match_filtered = module->And(NEW_ID, antecedent_match, not_until_match);
module->addDff(NEW_ID, clock, antecedent_match, antecedent_match_q, clockpol);
module->addDff(NEW_ID, clock, antecedent_match_filtered, antecedent_match_q, clockpol);
if (!until_with)
antecedent_match = antecedent_match_filtered;
}
SvaFsm consequent_fsm(module, clock, clockpol, disable_iff, antecedent_match);