riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Disconnect all ABC boxes too

This commit is contained in:
Eddie Hung 2019-05-27 19:40:27 -07:00
parent 428d7c8e11
commit 4df37c77fd
1 changed files with 9 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
passes/techmap/abc9.cc
View File

@ -867,21 +867,19 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
// module->connect(conn); // module->connect(conn);
// } // }
// Go through all AND and NOT output connections, // Go through all AND, NOT, and ABC box instances,
// and for those output ports driving wires // and disconnect their output connections in
// also driven by mapped_mod, disconnect them // preparation for stitching mapped_mod in
for (auto cell : module->cells()) { for (auto cell : module->cells()) {
if (!cell->type.in("$_AND_", "$_NOT_")) if (!cell->type.in("$_AND_", "$_NOT_")) {
RTLIL::Module* cell_module = design->module(cell->type);
if (!cell_module || !cell_module->attributes.count("\\abc_box_id"))
continue; continue;
}
for (auto &it : cell->connections_) { for (auto &it : cell->connections_) {
auto port_name = it.first; auto port_name = it.first;
if (!cell->output(port_name)) continue; if (!cell->output(port_name)) continue;
auto &signal = it.second; it.second = RTLIL::SigSpec();
auto bits = signal.bits();
for (auto &b : bits)
if (output_bits.count(b))
b = module->addWire(NEW_ID);
signal = std::move(bits);
} }
} }
// Do the same for module connections // Do the same for module connections