mirror of https://github.com/YosysHQ/yosys.git
Fix static initialization, fixes mingw build
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@ -34,26 +34,6 @@ struct LUTType {
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IdString output_param;
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};
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static const dict<IdString, LUTType> lut_types = {
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{ID(CC_LUT2), {{
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{ID(I0), {0, ID(INIT)}},
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{ID(I1), {1, ID(INIT)}},
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}, ID(INIT)}},
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{ID(CC_L2T4), {{
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{ID(I0), {0, ID(INIT_L00)}},
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{ID(I1), {1, ID(INIT_L00)}},
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{ID(I2), {0, ID(INIT_L01)}},
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{ID(I3), {1, ID(INIT_L01)}},
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}, ID(INIT_L10)}},
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{ID(CC_L2T5), {{
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{ID(I0), {0, ID(INIT_L02)}},
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{ID(I1), {1, ID(INIT_L02)}},
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{ID(I2), {0, ID(INIT_L03)}},
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{ID(I3), {1, ID(INIT_L03)}},
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{ID(I4), {0, ID(INIT_L20)}},
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}, ID(INIT_L20)}},
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};
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struct FoldInvWorker {
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FoldInvWorker(Module *module) : module(module), sigmap(module) {};
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Module *module;
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@ -64,6 +44,27 @@ struct FoldInvWorker {
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// Mapping from inverter input to inverter
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dict<SigBit, Cell*> inverter_input;
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const dict<IdString, LUTType> lut_types = {
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{ID(CC_LUT2), {{
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{ID(I0), {0, ID(INIT)}},
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{ID(I1), {1, ID(INIT)}},
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}, ID(INIT)}},
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{ID(CC_L2T4), {{
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{ID(I0), {0, ID(INIT_L00)}},
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{ID(I1), {1, ID(INIT_L00)}},
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{ID(I2), {0, ID(INIT_L01)}},
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{ID(I3), {1, ID(INIT_L01)}},
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}, ID(INIT_L10)}},
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{ID(CC_L2T5), {{
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{ID(I0), {0, ID(INIT_L02)}},
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{ID(I1), {1, ID(INIT_L02)}},
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{ID(I2), {0, ID(INIT_L03)}},
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{ID(I3), {1, ID(INIT_L03)}},
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{ID(I4), {0, ID(INIT_L20)}},
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}, ID(INIT_L20)}},
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};
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void find_inverted_bits()
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{
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for (auto cell : module->selected_cells()) {
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