mirror of https://github.com/YosysHQ/yosys.git
Added memory_unpack command
This commit is contained in:
Clifford Wolf
parent
11c7df40c3
commit
4d8318ad1b
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@ -2,5 +2,6 @@
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OBJS += passes/memory/memory.o
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OBJS += passes/memory/memory_dff.o
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OBJS += passes/memory/memory_collect.o
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OBJS += passes/memory/memory_unpack.o
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OBJS += passes/memory/memory_map.o
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@ -0,0 +1,116 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/log.h"
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#include <sstream>
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#include <algorithm>
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#include <stdlib.h>
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#include <assert.h>
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static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
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{
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log("Creating $memrd and $memwr for memory `%s' in module `%s':\n",
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memory->name.c_str(), module->name.c_str());
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RTLIL::IdString mem_name = RTLIL::escape_id(memory->parameters.at("\\MEMID").decode_string());
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if (module->memories.count(mem_name) != 0)
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log_error("Already found a memory object with the ID %s.\n", mem_name.c_str());
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RTLIL::Memory *mem = new RTLIL::Memory;
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mem->name = mem_name;
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mem->width = memory->parameters.at("\\WIDTH").as_int();
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mem->start_offset = memory->parameters.at("\\OFFSET").as_int();
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mem->size = memory->parameters.at("\\SIZE").as_int();
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module->memories[mem_name] = mem;
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int abits = memory->parameters.at("\\ABITS").as_int();
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int num_rd_ports = memory->parameters.at("\\RD_PORTS").as_int();
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int num_wr_ports = memory->parameters.at("\\WR_PORTS").as_int();
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for (int i = 0; i < num_rd_ports; i++)
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{
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RTLIL::Cell *cell = new RTLIL::Cell;
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cell->name = NEW_ID;
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cell->type = "$memrd";
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cell->parameters["\\MEMID"] = mem_name;
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cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS");
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cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH");
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cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_ENABLE")).extract(i, 1).as_const();
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cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_POLARITY")).extract(i, 1).as_const();
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cell->connections["\\CLK"] = memory->connections.at("\\RD_CLK").extract(i, 1);
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cell->connections["\\ADDR"] = memory->connections.at("\\RD_ADDR").extract(i*abits, abits);
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cell->connections["\\DATA"] = memory->connections.at("\\RD_DATA").extract(i*mem->width, mem->width);
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module->add(cell);
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}
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for (int i = 0; i < num_wr_ports; i++)
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{
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RTLIL::Cell *cell = new RTLIL::Cell;
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cell->name = NEW_ID;
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cell->type = "$memwr";
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cell->parameters["\\MEMID"] = mem_name;
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cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS");
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cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH");
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cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_ENABLE")).extract(i, 1).as_const();
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cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_POLARITY")).extract(i, 1).as_const();
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cell->parameters["\\PRIORITY"] = i;
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cell->connections["\\CLK"] = memory->connections.at("\\WR_CLK").extract(i, 1);
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cell->connections["\\EN"] = memory->connections.at("\\WR_EN").extract(i, 1);
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cell->connections["\\ADDR"] = memory->connections.at("\\WR_ADDR").extract(i*abits, abits);
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cell->connections["\\DATA"] = memory->connections.at("\\WR_DATA").extract(i*mem->width, mem->width);
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module->add(cell);
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}
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module->cells.erase(memory->name);
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delete memory;
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}
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static void handle_module(RTLIL::Design *design, RTLIL::Module *module)
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{
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std::vector<RTLIL::IdString> memcells;
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for (auto &cell_it : module->cells)
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if (cell_it.second->type == "$mem" && design->selected(module, cell_it.second))
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memcells.push_back(cell_it.first);
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for (auto &it : memcells)
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handle_memory(module, module->cells.at(it));
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}
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struct MemoryUnpackPass : public Pass {
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MemoryUnpackPass() : Pass("memory_unpack", "unpack multi-port memory cells") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" memory_unpack [selection]\n");
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log("\n");
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log("This pass converts the multi-port $mem memory cells into individual $memrd and\n");
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log("$memwr cells. It is the counterpart to the memory_collect pass.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
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log_header("Executing MEMORY_UNPACK pass (generating $memrd/$memwr cells form $mem cells).\n");
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extra_args(args, 1, design);
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for (auto &mod_it : design->modules)
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if (design->selected(mod_it.second))
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handle_module(design, mod_it.second);
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}
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} MemoryUnpackPass;
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