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Rename according to vendor doc TN1295

This commit is contained in:
Eddie Hung 2019-07-22 15:08:26 -07:00
parent 304cefbbe2
commit 4d71ab384d
3 changed files with 56 additions and 55 deletions
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48
passes/pmgen/ice40_dsp.cc
View File

@ -37,10 +37,10 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
log("ffA: %s\n", log_id(st.ffA, "--")); log("ffA: %s\n", log_id(st.ffA, "--"));
log("ffB: %s\n", log_id(st.ffB, "--")); log("ffB: %s\n", log_id(st.ffB, "--"));
log("mul: %s\n", log_id(st.mul, "--")); log("mul: %s\n", log_id(st.mul, "--"));
log("ffY: %s\n", log_id(st.ffY, "--")); log("ffH: %s\n", log_id(st.ffH, "--"));
log("addAB: %s\n", log_id(st.addAB, "--")); log("addAB: %s\n", log_id(st.addAB, "--"));
log("muxAB: %s\n", log_id(st.muxAB, "--")); log("muxAB: %s\n", log_id(st.muxAB, "--"));
log("ffS: %s\n", log_id(st.ffS, "--")); log("ffO: %s\n", log_id(st.ffO, "--"));
#endif #endif
log("Checking %s.%s for iCE40 DSP inference.\n", log_id(pm.module), log_id(st.mul)); log("Checking %s.%s for iCE40 DSP inference.\n", log_id(pm.module), log_id(st.mul));
@ -55,13 +55,13 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
return; return;
} }
if (GetSize(st.sigS) > 32) { if (GetSize(st.sigO) > 32) {
log(" accumulator (%s) is too large (%d > 32).\n", log_signal(st.sigS), GetSize(st.sigS)); log(" accumulator (%s) is too large (%d > 32).\n", log_signal(st.sigO), GetSize(st.sigO));
return; return;
} }
if (GetSize(st.sigY) > 32) { if (GetSize(st.sigH) > 32) {
log(" output (%s) is too large (%d > 32).\n", log_signal(st.sigY), GetSize(st.sigY)); log(" output (%s) is too large (%d > 32).\n", log_signal(st.sigH), GetSize(st.sigH));
return; return;
} }
@ -96,7 +96,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
else if (st.addB) else if (st.addB)
CD = st.addAB->getPort("\\A"); CD = st.addAB->getPort("\\A");
else log_abort(); else log_abort();
CD_signed = st.sigS_signed; CD_signed = st.sigO_signed;
} }
CD.extend_u0(32, CD_signed); CD.extend_u0(32, CD_signed);
@ -130,11 +130,11 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
if (st.ffB) if (st.ffB)
log(" ffB:%s", log_id(st.ffB)); log(" ffB:%s", log_id(st.ffB));
if (st.ffY) if (st.ffH)
log(" ffY:%s", log_id(st.ffY)); log(" ffH:%s", log_id(st.ffH));
if (st.ffS) if (st.ffO)
log(" ffS:%s", log_id(st.ffS)); log(" ffO:%s", log_id(st.ffO));
log("\n"); log("\n");
} }
@ -158,20 +158,20 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
// SB_MAC16 Output Interface // SB_MAC16 Output Interface
SigSpec O = st.ffS ? st.sigS : (st.addAB ? st.addAB->getPort("\\Y") : st.sigY); SigSpec O = st.ffO ? st.sigO : (st.addAB ? st.addAB->getPort("\\Y") : st.sigH);
if (GetSize(O) < 32) if (GetSize(O) < 32)
O.append(pm.module->addWire(NEW_ID, 32-GetSize(O))); O.append(pm.module->addWire(NEW_ID, 32-GetSize(O)));
cell->setPort("\\O", O); cell->setPort("\\O", O);
// MAC only if ffS exists and adder's other input (sigS) // MAC only if ffO exists and adder's other input (sigO)
// is output of ffS // is output of ffO
bool accum = false; bool accum = false;
if (st.addAB) { if (st.addAB) {
if (st.addA) if (st.addA)
accum = (st.ffS && st.addAB->getPort("\\B") == st.ffS->getPort("\\Q")); accum = (st.ffO && st.addAB->getPort("\\B") == st.ffO->getPort("\\Q"));
else if (st.addB) else if (st.addB)
accum = (st.ffS && st.addAB->getPort("\\A") == st.ffS->getPort("\\Q")); accum = (st.ffO && st.addAB->getPort("\\A") == st.ffO->getPort("\\Q"));
else log_abort(); else log_abort();
if (accum) if (accum)
log(" accumulator %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type)); log(" accumulator %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type));
@ -204,17 +204,17 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
cell->setParam("\\C_REG", State::S0); cell->setParam("\\C_REG", State::S0);
cell->setParam("\\D_REG", State::S0); cell->setParam("\\D_REG", State::S0);
cell->setParam("\\TOP_8x8_MULT_REG", st.ffY ? State::S1 : State::S0); cell->setParam("\\TOP_8x8_MULT_REG", st.ffH ? State::S1 : State::S0);
cell->setParam("\\BOT_8x8_MULT_REG", st.ffY ? State::S1 : State::S0); cell->setParam("\\BOT_8x8_MULT_REG", st.ffH ? State::S1 : State::S0);
cell->setParam("\\PIPELINE_16x16_MULT_REG1", st.ffY ? State::S1 : State::S0); cell->setParam("\\PIPELINE_16x16_MULT_REG1", st.ffH ? State::S1 : State::S0);
cell->setParam("\\PIPELINE_16x16_MULT_REG2", State::S0); cell->setParam("\\PIPELINE_16x16_MULT_REG2", State::S0);
cell->setParam("\\TOPOUTPUT_SELECT", Const(st.ffS ? 1 : (st.addAB ? 0 : 3), 2)); cell->setParam("\\TOPOUTPUT_SELECT", Const(st.ffO ? 1 : (st.addAB ? 0 : 3), 2));
cell->setParam("\\TOPADDSUB_LOWERINPUT", Const(2, 2)); cell->setParam("\\TOPADDSUB_LOWERINPUT", Const(2, 2));
cell->setParam("\\TOPADDSUB_UPPERINPUT", accum ? State::S0 : State::S1); cell->setParam("\\TOPADDSUB_UPPERINPUT", accum ? State::S0 : State::S1);
cell->setParam("\\TOPADDSUB_CARRYSELECT", Const(3, 2)); cell->setParam("\\TOPADDSUB_CARRYSELECT", Const(3, 2));
cell->setParam("\\BOTOUTPUT_SELECT", Const(st.ffS ? 1 : (st.addAB ? 0 : 3), 2)); cell->setParam("\\BOTOUTPUT_SELECT", Const(st.ffO ? 1 : (st.addAB ? 0 : 3), 2));
cell->setParam("\\BOTADDSUB_LOWERINPUT", Const(2, 2)); cell->setParam("\\BOTADDSUB_LOWERINPUT", Const(2, 2));
cell->setParam("\\BOTADDSUB_UPPERINPUT", accum ? State::S0 : State::S1); cell->setParam("\\BOTADDSUB_UPPERINPUT", accum ? State::S0 : State::S1);
cell->setParam("\\BOTADDSUB_CARRYSELECT", Const(0, 2)); cell->setParam("\\BOTADDSUB_CARRYSELECT", Const(0, 2));
@ -224,10 +224,10 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
cell->setParam("\\B_SIGNED", b_signed); cell->setParam("\\B_SIGNED", b_signed);
pm.autoremove(st.mul); pm.autoremove(st.mul);
pm.autoremove(st.ffY); pm.autoremove(st.ffH);
pm.autoremove(st.addAB); pm.autoremove(st.addAB);
if (st.ffS) if (st.ffO)
st.ffS->connections_.at("\\Q").replace(st.sigS, pm.module->addWire(NEW_ID, GetSize(st.sigS))); st.ffO->connections_.at("\\Q").replace(st.sigO, pm.module->addWire(NEW_ID, GetSize(st.sigO)));
} }
struct Ice40DspPass : public Pass { struct Ice40DspPass : public Pass {

62
passes/pmgen/ice40_dsp.pmg
View File

@ -1,8 +1,8 @@
pattern ice40_dsp pattern ice40_dsp
state <SigBit> clock state <SigBit> clock
state <bool> clock_pol sigS_signed state <bool> clock_pol sigO_signed
state <SigSpec> sigA sigB sigY sigS state <SigSpec> sigA sigB sigH sigO
state <Cell*> addAB muxAB state <Cell*> addAB muxAB
match mul match mul
@ -53,21 +53,21 @@ code sigB clock clock_pol
} }
endcode endcode
match ffY match ffH
select ffY->type.in($dff) select ffH->type.in($dff)
select nusers(port(ffY, \D)) == 2 select nusers(port(ffH, \D)) == 2
index <SigSpec> port(ffY, \D) === port(mul, \Y) index <SigSpec> port(ffH, \D) === port(mul, \Y)
optional optional
endmatch endmatch
code sigY clock clock_pol code sigH clock clock_pol
sigY = port(mul, \Y); sigH = port(mul, \Y);
if (ffY) { if (ffH) {
sigY = port(ffY, \Q); sigH = port(ffH, \Q);
SigBit c = port(ffY, \CLK).as_bit(); SigBit c = port(ffH, \CLK).as_bit();
bool cp = param(ffY, \CLK_POLARITY).as_bool(); bool cp = param(ffH, \CLK_POLARITY).as_bool();
if (clock != SigBit() && (c != clock || cp != clock_pol)) if (clock != SigBit() && (c != clock || cp != clock_pol))
reject; reject;
@ -80,7 +80,7 @@ endcode
match addA match addA
select addA->type.in($add) select addA->type.in($add)
select nusers(port(addA, \A)) == 2 select nusers(port(addA, \A)) == 2
index <SigSpec> port(addA, \A) === sigY index <SigSpec> port(addA, \A) === sigH
optional optional
endmatch endmatch
@ -88,25 +88,25 @@ match addB
if !addA if !addA
select addB->type.in($add, $sub) select addB->type.in($add, $sub)
select nusers(port(addB, \B)) == 2 select nusers(port(addB, \B)) == 2
index <SigSpec> port(addB, \B) === sigY index <SigSpec> port(addB, \B) === sigH
optional optional
endmatch endmatch
code addAB sigS sigS_signed code addAB sigO sigO_signed
if (addA) { if (addA) {
addAB = addA; addAB = addA;
sigS = port(addAB, \B); sigO = port(addAB, \B);
sigS_signed = param(addAB, \B_SIGNED).as_bool(); sigO_signed = param(addAB, \B_SIGNED).as_bool();
} }
if (addB) { if (addB) {
addAB = addB; addAB = addB;
sigS = port(addAB, \A); sigO = port(addAB, \A);
sigS_signed = param(addAB, \A_SIGNED).as_bool(); sigO_signed = param(addAB, \A_SIGNED).as_bool();
} }
if (addAB) { if (addAB) {
int natural_mul_width = GetSize(sigA) + GetSize(sigB); int natural_mul_width = GetSize(sigA) + GetSize(sigB);
int actual_mul_width = GetSize(sigY); int actual_mul_width = GetSize(sigH);
int actual_acc_width = GetSize(sigS); int actual_acc_width = GetSize(sigO);
if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width)) if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
reject; reject;
@ -140,22 +140,22 @@ code muxAB
muxAB = muxB; muxAB = muxB;
endcode endcode
match ffS match ffO
if muxAB if muxAB
select ffS->type.in($dff) select ffO->type.in($dff)
filter nusers(port(muxAB, \Y)) == 2 filter nusers(port(muxAB, \Y)) == 2
filter includes(port(ffS, \D).to_sigbit_set(), port(muxAB, \Y).to_sigbit_set()) filter includes(port(ffO, \D).to_sigbit_set(), port(muxAB, \Y).to_sigbit_set())
optional optional
endmatch endmatch
code clock clock_pol sigS code clock clock_pol sigO
if (ffS) { if (ffO) {
SigBit c = port(ffS, \CLK).as_bit(); SigBit c = port(ffO, \CLK).as_bit();
bool cp = param(ffS, \CLK_POLARITY).as_bool(); bool cp = param(ffO, \CLK_POLARITY).as_bool();
if (port(ffS, \Q) != sigS) { if (port(ffO, \Q) != sigO) {
sigS = port(muxAB, \Y); sigO = port(muxAB, \Y);
sigS.replace(port(ffS, \D), port(ffS, \Q)); sigO.replace(port(ffO, \D), port(ffO, \Q));
} }
if (clock != SigBit() && (c != clock || cp != clock_pol)) if (clock != SigBit() && (c != clock || cp != clock_pol))

1
techlibs/ice40/synth_ice40.cc
View File

@ -271,6 +271,7 @@ struct SynthIce40Pass : public ScriptPass
run("wreduce", " (if -dsp)"); run("wreduce", " (if -dsp)");
run("ice40_dsp", " (if -dsp)"); run("ice40_dsp", " (if -dsp)");
run("chtype -set $mul t:$__soft_mul","(if -dsp)"); run("chtype -set $mul t:$__soft_mul","(if -dsp)");
run("dump A:top");
} }
run("alumacc"); run("alumacc");
run("opt"); run("opt");