riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

abc9_ops: -prep_dff_map to error if async flop found

This commit is contained in:
Eddie Hung 2020-04-15 16:29:11 -07:00
parent 6c66030dfb
commit 4cec21b93e
2 changed files with 7 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
passes/techmap/abc9_ops.cc
View File

@ -181,7 +181,7 @@ void prep_dff_map(RTLIL::Design *design)
for (auto cell : module->cells()) for (auto cell : module->cells())
if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_))) { if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_))) {
if (dff_cell) if (dff_cell)
log_error("More than one $_DFF_[NP]_ cell found in module '%s' marked (* abc9_flop *)\n", log_id(module)); log_error("Module '%s' with (* abc9_flop *) contains more than one $_DFF_[NP]_ cell.\n", log_id(module));
dff_cell = cell; dff_cell = cell;
// Block sequential synthesis on cells with (* init *) != 1'b0 // Block sequential synthesis on cells with (* init *) != 1'b0
@ -207,10 +207,15 @@ void prep_dff_map(RTLIL::Design *design)
goto continue_outer_loop; goto continue_outer_loop;
} }
} }
else if (cell->type.in(ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_),
ID($__DFFE_NN0), ID($__DFFE_NN1), ID($__DFFE_NP0), ID($__DFFE_NP1),
ID($__DFFE_PN0), ID($__DFFE_PN1), ID($__DFFE_PP0), ID($__DFFE_PP1)))
log_error("Module '%s' with (* abc9_flop *) contains an asynchronous $_DFFE?_[NP][NP][01]_? cell, which is not supported for sequential synthesis.\n", log_id(module));
else if (cell->type.in(ID($specify2), ID($specify3), ID($specrule))) else if (cell->type.in(ID($specify2), ID($specify3), ID($specrule)))
specify_cells.emplace_back(cell); specify_cells.emplace_back(cell);
if (!dff_cell) if (!dff_cell)
log_error("$_DFF_[NP]_ cell not found in module '%s' marked (* abc9_flop *)\n", log_id(module)); log_error("Module '%s' with (* abc9_flop *) does not any contain $_DFF_[NP]_ cells.\n", log_id(module));
D = dff_cell->getPort(ID::D); D = dff_cell->getPort(ID::D);
@ -229,9 +234,6 @@ void prep_dff_map(RTLIL::Design *design)
D = w; D = w;
} }
if (GetSize(specify_cells) == 0)
log_error("Module '%s' marked (* abc9_flop *) contains no specify timing information.\n", log_id(module));
// Rewrite $specify cells that end with $_DFF_[NP]_.Q // Rewrite $specify cells that end with $_DFF_[NP]_.Q
// to $_DFF_[NP]_.D since it will be moved into // to $_DFF_[NP]_.D since it will be moved into
// the submodule // the submodule

4
techlibs/xilinx/cells_sim.v
View File

@ -656,7 +656,6 @@ module FDRSE (
Q <= d; Q <= d;
endmodule endmodule
(* lib_whitebox *)
module FDCE ( module FDCE (
output reg Q, output reg Q,
(* clkbuf_sink *) (* clkbuf_sink *)
@ -699,7 +698,6 @@ module FDCE (
endspecify endspecify
endmodule endmodule
(* lib_whitebox *)
module FDCE_1 ( module FDCE_1 (
output reg Q, output reg Q,
(* clkbuf_sink *) (* clkbuf_sink *)
@ -724,7 +722,6 @@ module FDCE_1 (
endspecify endspecify
endmodule endmodule
(* lib_whitebox *)
module FDPE ( module FDPE (
output reg Q, output reg Q,
(* clkbuf_sink *) (* clkbuf_sink *)
@ -766,7 +763,6 @@ module FDPE (
endspecify endspecify
endmodule endmodule
(* lib_whitebox *)
module FDPE_1 ( module FDPE_1 (
output reg Q, output reg Q,
(* clkbuf_sink *) (* clkbuf_sink *)