riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

shregmap -tech xilinx to delete $shiftx for var length SRL

This commit is contained in:
Eddie Hung 2019-03-19 15:05:08 -07:00
parent f239cb821e
commit 4cd8f02973
1 changed files with 3 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
passes/techmap/shregmap.cc
View File

@ -187,19 +187,12 @@ struct ShregmapTechXilinx7 : ShregmapTech
if (it == sigbit_to_shiftx_offset.end()) if (it == sigbit_to_shiftx_offset.end())
return true; return true;
auto cell_q = cell->getPort("\\Q");
log_assert(cell_q.is_bit());
Cell* shiftx = it->second.first; Cell* shiftx = it->second.first;
// FIXME: Hack to ensure that $shiftx gets optimised away
// Without this, Yosys will refuse to optimise away a $shiftx
// where \\A 's width is not perfectly \\B_WIDTH ** 2
// See YosysHQ/yosys#878
auto shiftx_bwidth = shiftx->getParam("\\B_WIDTH").as_int();
shiftx->setPort("\\A", cell_q.repeat(1 << shiftx_bwidth));
shiftx->setParam("\\A_WIDTH", 1 << shiftx_bwidth);
cell->setPort("\\L", shiftx->getPort("\\B")); cell->setPort("\\L", shiftx->getPort("\\B"));
cell->setPort("\\Q", shiftx->getPort("\\Y"));
cell->module->remove(shiftx);
return true; return true;
} }