riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

intel_alm: cleanup duplication

This commit is contained in:
Dan Ravensloft 2020-04-23 22:44:29 +01:00 committed by Marcelina Kościelnicka
parent b048afc3a6
commit 4ca5f9799b
5 changed files with 64 additions and 113 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
techlibs/intel_alm/Makefile.inc
View File

@ -15,9 +15,6 @@ $(foreach bramtype, $(bramtypes), $(eval $(call add_share_file,share/intel_alm/c
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/lutram_mlab.txt))
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/lutram_mlab_map.v))
families := cyclonev cyclone10gx
# Miscellaneous
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/megafunction_bb.v))
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/quartus_rename.v))
$(foreach family, $(families), $(eval $(call add_share_file,share/intel_alm/$(family),techlibs/intel_alm/$(family)/quartus_rename.v)))

63
techlibs/intel_alm/common/quartus_rename.v
View File

@ -1,3 +1,10 @@
`ifdef cyclonev
`define LCELL cyclonev_lcell_comb
`endif
`ifdef cyclone10gx
`define LCELL cyclone10gx_lcell_comb
`endif
module __MISTRAL_VCC(output Q);
MISTRAL_ALUT2 #(.LUT(4'b1111)) _TECHMAP_REPLACE_ (.A(1'b1), .B(1'b1), .Q(Q));
@ -17,3 +24,59 @@ module MISTRAL_FF(input DATAIN, CLK, ACLR, ENA, SCLR, SLOAD, SDATA, output reg Q
dffeas #(.power_up("low"), .is_wysiwyg("true")) _TECHMAP_REPLACE_ (.d(DATAIN), .clk(CLK), .clrn(ACLR), .ena(ENA), .sclr(SCLR), .sload(SLOAD), .asdata(SDATA), .q(Q));
endmodule
module MISTRAL_ALUT6(input A, B, C, D, E, F, output Q);
parameter [63:0] LUT = 64'h0000_0000_0000_0000;
`LCELL #(.lut_mask(LUT)) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .datae(E), .dataf(F), .combout(Q));
endmodule
module MISTRAL_ALUT5(input A, B, C, D, E, output Q);
parameter [31:0] LUT = 32'h0000_0000;
`LCELL #(.lut_mask({2{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .datae(E), .combout(Q));
endmodule
module MISTRAL_ALUT4(input A, B, C, D, output Q);
parameter [15:0] LUT = 16'h0000;
`LCELL #(.lut_mask({4{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .combout(Q));
endmodule
module MISTRAL_ALUT3(input A, B, C, output Q);
parameter [7:0] LUT = 8'h00;
`LCELL #(.lut_mask({8{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .combout(Q));
endmodule
module MISTRAL_ALUT2(input A, B, output Q);
parameter [3:0] LUT = 4'h0;
`LCELL #(.lut_mask({16{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .combout(Q));
endmodule
module MISTRAL_NOT(input A, output Q);
NOT _TECHMAP_REPLACE_ (.IN(A), .OUT(Q));
endmodule
module MISTRAL_ALUT_ARITH(input A, B, C, D0, D1, CI, output SO, CO);
parameter LUT0 = 16'h0000;
parameter LUT1 = 16'h0000;
`LCELL #(.lut_mask({16'h0, LUT1, 16'h0, LUT0})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D0), .dataf(D1), .cin(CI), .sumout(SO), .cout(CO));
endmodule

54
techlibs/intel_alm/cyclone10gx/quartus_rename.v
View File

@ -1,54 +0,0 @@
module MISTRAL_ALUT6(input A, B, C, D, E, F, output Q);
parameter LUT = 64'h0000_0000_0000_0000;
cyclone10gx_lcell_comb #(.lut_mask(LUT)) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .datae(E), .dataf(F), .combout(Q));
endmodule
module MISTRAL_ALUT5(input A, B, C, D, E, output Q);
parameter LUT = 32'h0000_0000;
cyclone10gx_lcell_comb #(.lut_mask({2{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .datae(E), .combout(Q));
endmodule
module MISTRAL_ALUT4(input A, B, C, D, output Q);
parameter LUT = 16'h0000;
cyclone10gx_lcell_comb #(.lut_mask({4{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .combout(Q));
endmodule
module MISTRAL_ALUT3(input A, B, C, output Q);
parameter LUT = 8'h00;
cyclone10gx_lcell_comb #(.lut_mask({8{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .combout(Q));
endmodule
module MISTRAL_ALUT2(input A, B, output Q);
parameter LUT = 4'h0;
cyclone10gx_lcell_comb #(.lut_mask({16{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .combout(Q));
endmodule
module MISTRAL_NOT(input A, output Q);
NOT _TECHMAP_REPLACE_ (.IN(A), .OUT(Q));
endmodule
module MISTRAL_ALUT_ARITH(input A, B, C, D0, D1, CI, output SO, CO);
parameter LUT0 = 16'h0000;
parameter LUT1 = 16'h0000;
cyclone10gx_lcell_comb #(.lut_mask({16'h0, LUT1, 16'h0, LUT0})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D0), .dataf(D1), .cin(CI), .sumout(SO), .cout(CO));
endmodule

54
techlibs/intel_alm/cyclonev/quartus_rename.v
View File

@ -1,54 +0,0 @@
module MISTRAL_ALUT6(input A, B, C, D, E, F, output Q);
parameter LUT = 64'h0000_0000_0000_0000;
cyclonev_lcell_comb #(.lut_mask(LUT)) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .datae(E), .dataf(F), .combout(Q));
endmodule
module MISTRAL_ALUT5(input A, B, C, D, E, output Q);
parameter LUT = 32'h0000_0000;
cyclonev_lcell_comb #(.lut_mask({2{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .datae(E), .combout(Q));
endmodule
module MISTRAL_ALUT4(input A, B, C, D, output Q);
parameter LUT = 16'h0000;
cyclonev_lcell_comb #(.lut_mask({4{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D), .combout(Q));
endmodule
module MISTRAL_ALUT3(input A, B, C, output Q);
parameter LUT = 8'h00;
cyclonev_lcell_comb #(.lut_mask({8{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .combout(Q));
endmodule
module MISTRAL_ALUT2(input A, B, output Q);
parameter LUT = 4'h0;
cyclonev_lcell_comb #(.lut_mask({16{LUT}})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .combout(Q));
endmodule
module MISTRAL_NOT(input A, output Q);
NOT _TECHMAP_REPLACE_ (.IN(A), .OUT(Q));
endmodule
module MISTRAL_ALUT_ARITH(input A, B, C, D0, D1, CI, output SO, CO);
parameter LUT0 = 16'h0000;
parameter LUT1 = 16'h0000;
cyclonev_lcell_comb #(.lut_mask({16'h0, LUT1, 16'h0, LUT0})) _TECHMAP_REPLACE_ (.dataa(A), .datab(B), .datac(C), .datad(D0), .dataf(D1), .cin(CI), .sumout(SO), .cout(CO));
endmodule

3
techlibs/intel_alm/synth_intel_alm.cc
View File

@ -235,8 +235,7 @@ struct SynthIntelALMPass : public ScriptPass {
// to constant driver cells, which Quartus accepts.
run("hilomap -singleton -hicell __MISTRAL_VCC Q -locell __MISTRAL_GND Q");
// Rename from Yosys-internal MISTRAL_* cells to Quartus cells.
run("techmap -map +/intel_alm/common/quartus_rename.v");
run(stringf("techmap -map +/intel_alm/%s/quartus_rename.v", family_opt.c_str()));
run(stringf("techmap -D %s -map +/intel_alm/common/quartus_rename.v", family_opt.c_str()));
}
}