riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Add -params mode to force undef parameters in selected cells. 

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman 2019-02-21 10:16:38 -08:00
parent 0e371109b0
commit 4c82ddf394
1 changed files with 29 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29
passes/cmds/setundef.cc
View File

@ -143,6 +143,9 @@ struct SetundefPass : public Pass {
log(" -init\n"); log(" -init\n");
log(" also create/update init values for flip-flops\n"); log(" also create/update init values for flip-flops\n");
log("\n"); log("\n");
log(" -params\n");
log(" replace undef in cell parameters\n");
log("\n");
} }
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
@ -150,6 +153,7 @@ struct SetundefPass : public Pass {
bool undriven_mode = false; bool undriven_mode = false;
bool expose_mode = false; bool expose_mode = false;
bool init_mode = false; bool init_mode = false;
bool params_mode = false;
SetundefWorker worker; SetundefWorker worker;
log_header(design, "Executing SETUNDEF pass (replace undef values with defined constants).\n"); log_header(design, "Executing SETUNDEF pass (replace undef values with defined constants).\n");
@ -199,6 +203,10 @@ struct SetundefPass : public Pass {
init_mode = true; init_mode = true;
continue; continue;
} }
if (args[argidx] == "-params") {
params_mode = true;
continue;
}
if (args[argidx] == "-random" && !got_value && argidx+1 < args.size()) { if (args[argidx] == "-random" && !got_value && argidx+1 < args.size()) {
got_value = true; got_value = true;
worker.next_bit_mode = MODE_RANDOM; worker.next_bit_mode = MODE_RANDOM;
@ -228,6 +236,27 @@ struct SetundefPass : public Pass {
for (auto module : design->selected_modules()) for (auto module : design->selected_modules())
{ {
if (params_mode)
{
for (auto *cell : module->cells())
{
// Only modify selected cells.
if (!design->selected(module, it)) {
continue;
}
for (auto &parameter : cell->parameters)
{
for (auto &bit : parameter.second.bits) {
if (bit > RTLIL::State::S1)
{
bit = worker.next_bit();
}
}
}
}
}
if (undriven_mode) if (undriven_mode)
{ {
if (!module->processes.empty()) if (!module->processes.empty())