mirror of https://github.com/YosysHQ/yosys.git
bugpoint: skip ports with (* keep *) on; add header
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@ -66,7 +66,8 @@ struct BugpointPass : public Pass {
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log(" try to remove modules.\n");
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log("\n");
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log(" -ports\n");
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log(" try to remove module ports.\n");
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log(" try to remove module ports. ports with a (* keep *) attribute will be\n");
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log(" skipped (useful for clocks, resets, etc.)\n");
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log("\n");
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log(" -cells\n");
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log(" try to remove cells.\n");
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@ -162,18 +163,21 @@ struct BugpointPass : public Pass {
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for (auto wire : mod->wires())
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{
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if (!wire->port_id)
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continue;
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if (!stage2 && wire->get_bool_attribute(ID($bugpoint)))
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continue;
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if (wire->port_input || wire->port_output)
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if (wire->get_bool_attribute(ID::keep))
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continue;
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if (index++ == seed)
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{
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if (index++ == seed)
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{
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log("Trying to remove module port %s.\n", log_signal(wire));
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wire->port_input = wire->port_output = false;
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mod->fixup_ports();
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return design_copy;
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}
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log("Trying to remove module port %s.\n", log_signal(wire));
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wire->port_input = wire->port_output = false;
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mod->fixup_ports();
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return design_copy;
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}
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}
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}
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@ -306,6 +310,9 @@ struct BugpointPass : public Pass {
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bool fast = false, clean = false;
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bool modules = false, ports = false, cells = false, connections = false, assigns = false, updates = false, has_part = false;
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log_header(design, "Executing BUGPOINT pass (minimize testcases).\n");
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log_push();
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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@ -449,6 +456,8 @@ struct BugpointPass : public Pass {
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design->add(module->clone());
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delete crashing_design;
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}
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log_pop();
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}
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} BugpointPass;
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