mirror of https://github.com/YosysHQ/yosys.git
synth_gowin: move splitnets to after iopadmap (#2435)
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@ -238,7 +238,6 @@ struct SynthGowinPass : public ScriptPass
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run("opt -fast");
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if (retime || help_mode)
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run("abc -dff -D 1", "(only if -retime)");
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run("splitnets");
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if (!noiopads || help_mode)
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run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O "
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"-toutpad $__GW_TBUF OE:I:O -tinoutpad $__GW_IOBUF OE:O:I:IO", "(unless -noiopads)");
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@ -278,6 +277,8 @@ struct SynthGowinPass : public ScriptPass
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run("opt_lut_ins -tech gowin");
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run("setundef -undriven -params -zero");
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run("hilomap -singleton -hicell VCC V -locell GND G");
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if (!vout_file.empty() || help_mode) // vendor output requires 1-bit wires
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run("splitnets -ports", "(only if -vout used)");
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run("clean");
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run("autoname");
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}
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@ -293,7 +294,7 @@ struct SynthGowinPass : public ScriptPass
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if (check_label("vout"))
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{
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if (!vout_file.empty() || help_mode)
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run(stringf("write_verilog -decimal -attr2comment -defparam -renameprefix gen %s",
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run(stringf("write_verilog -simple-lhs -decimal -attr2comment -defparam -renameprefix gen %s",
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help_mode ? "<file-name>" : vout_file.c_str()));
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if (!json_file.empty() || help_mode)
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run(stringf("write_json %s",
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