mirror of https://github.com/YosysHQ/yosys.git
Cleanups in handling of read_verilog -defer and -icells
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@ -759,7 +759,7 @@ static AstModule* process_module(AstNode *ast, bool defer)
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current_module = new AstModule;
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current_module = new AstModule;
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current_module->ast = NULL;
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current_module->ast = NULL;
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current_module->name = defer ? "$abstract" + ast->str : ast->str;
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current_module->name = ast->str;
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current_module->attributes["\\src"] = stringf("%s:%d", ast->filename.c_str(), ast->linenum);
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current_module->attributes["\\src"] = stringf("%s:%d", ast->filename.c_str(), ast->linenum);
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current_ast_mod = ast;
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current_ast_mod = ast;
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@ -857,7 +857,11 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
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assert(current_ast->type == AST_DESIGN);
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assert(current_ast->type == AST_DESIGN);
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for (auto it = current_ast->children.begin(); it != current_ast->children.end(); it++) {
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for (auto it = current_ast->children.begin(); it != current_ast->children.end(); it++) {
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if (design->modules.count((*it)->str) != 0 && design->modules.count("$abstract" + (*it)->str) != 0) {
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if (flag_icells && (*it)->str.substr(0, 2) == "\\$")
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(*it)->str = (*it)->str.substr(1);
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if (defer)
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(*it)->str = "$abstract" + (*it)->str;
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if (design->modules.count((*it)->str)) {
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if (!ignore_redef)
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if (!ignore_redef)
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log_error("Re-definition of module `%s' at %s:%d!\n",
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log_error("Re-definition of module `%s' at %s:%d!\n",
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(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
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(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
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@ -865,10 +869,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
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(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
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(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
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continue;
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continue;
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}
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}
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if (defer)
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design->modules[(*it)->str] = process_module(*it, defer);
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design->modules["$abstract" + (*it)->str] = process_module(*it, true);
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else
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design->modules[(*it)->str] = process_module(*it, false);
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}
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}
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}
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}
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